1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
5 * Copyright (C) 2013 ARM Limited
6 * Copyright (C) 2017 Red Hat
9 #include <linux/atomic.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-iommu.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
20 #include <linux/iopoll.h>
21 #include <linux/kconfig.h>
22 #include <linux/init.h>
23 #include <linux/mutex.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/of_iommu.h>
28 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/qcom_scm.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
35 #include "arm-smmu-regs.h"
37 #define SMMU_INTR_SEL_NS 0x2000
39 struct qcom_iommu_ctx;
41 struct qcom_iommu_dev {
42 /* IOMMU core code handle */
43 struct iommu_device iommu;
45 struct clk *iface_clk;
47 void __iomem *local_base;
50 struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */
53 struct qcom_iommu_ctx {
57 u8 asid; /* asid and ctx bank # are 1:1 */
58 struct iommu_domain *domain;
61 struct qcom_iommu_domain {
62 struct io_pgtable_ops *pgtbl_ops;
63 spinlock_t pgtbl_lock;
64 struct mutex init_mutex; /* Protects iommu pointer */
65 struct iommu_domain domain;
66 struct qcom_iommu_dev *iommu;
69 static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
71 return container_of(dom, struct qcom_iommu_domain, domain);
74 static const struct iommu_ops qcom_iommu_ops;
76 static struct qcom_iommu_dev * to_iommu(struct iommu_fwspec *fwspec)
78 if (!fwspec || fwspec->ops != &qcom_iommu_ops)
80 return fwspec->iommu_priv;
83 static struct qcom_iommu_ctx * to_ctx(struct iommu_fwspec *fwspec, unsigned asid)
85 struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
88 return qcom_iommu->ctxs[asid - 1];
92 iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
94 writel_relaxed(val, ctx->base + reg);
98 iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
100 writeq_relaxed(val, ctx->base + reg);
104 iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
106 return readl_relaxed(ctx->base + reg);
110 iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
112 return readq_relaxed(ctx->base + reg);
115 static void qcom_iommu_tlb_sync(void *cookie)
117 struct iommu_fwspec *fwspec = cookie;
120 for (i = 0; i < fwspec->num_ids; i++) {
121 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
122 unsigned int val, ret;
124 iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
126 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
127 (val & 0x1) == 0, 0, 5000000);
129 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
133 static void qcom_iommu_tlb_inv_context(void *cookie)
135 struct iommu_fwspec *fwspec = cookie;
138 for (i = 0; i < fwspec->num_ids; i++) {
139 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
140 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
143 qcom_iommu_tlb_sync(cookie);
146 static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
147 size_t granule, bool leaf, void *cookie)
149 struct iommu_fwspec *fwspec = cookie;
152 reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
154 for (i = 0; i < fwspec->num_ids; i++) {
155 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
161 iommu_writel(ctx, reg, iova);
163 } while (s -= granule);
167 static const struct iommu_gather_ops qcom_gather_ops = {
168 .tlb_flush_all = qcom_iommu_tlb_inv_context,
169 .tlb_add_flush = qcom_iommu_tlb_inv_range_nosync,
170 .tlb_sync = qcom_iommu_tlb_sync,
173 static irqreturn_t qcom_iommu_fault(int irq, void *dev)
175 struct qcom_iommu_ctx *ctx = dev;
179 fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
181 if (!(fsr & FSR_FAULT))
184 fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
185 iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
187 if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
188 dev_err_ratelimited(ctx->dev,
189 "Unhandled context fault: fsr=0x%x, "
190 "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
191 fsr, iova, fsynr, ctx->asid);
194 iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
195 iommu_writel(ctx, ARM_SMMU_CB_RESUME, RESUME_TERMINATE);
200 static int qcom_iommu_init_domain(struct iommu_domain *domain,
201 struct qcom_iommu_dev *qcom_iommu,
202 struct iommu_fwspec *fwspec)
204 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
205 struct io_pgtable_ops *pgtbl_ops;
206 struct io_pgtable_cfg pgtbl_cfg;
210 mutex_lock(&qcom_domain->init_mutex);
211 if (qcom_domain->iommu)
214 pgtbl_cfg = (struct io_pgtable_cfg) {
215 .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap,
218 .tlb = &qcom_gather_ops,
219 .iommu_dev = qcom_iommu->dev,
222 qcom_domain->iommu = qcom_iommu;
223 pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec);
225 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
227 goto out_clear_iommu;
230 /* Update the domain's page sizes to reflect the page table format */
231 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
232 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
233 domain->geometry.force_aperture = true;
235 for (i = 0; i < fwspec->num_ids; i++) {
236 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
238 if (!ctx->secure_init) {
239 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
241 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
242 goto out_clear_iommu;
244 ctx->secure_init = true;
248 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
249 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
250 ((u64)ctx->asid << TTBRn_ASID_SHIFT));
251 iommu_writeq(ctx, ARM_SMMU_CB_TTBR1,
252 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
253 ((u64)ctx->asid << TTBRn_ASID_SHIFT));
256 iommu_writel(ctx, ARM_SMMU_CB_TTBCR2,
257 (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
258 TTBCR2_SEP_UPSTREAM);
259 iommu_writel(ctx, ARM_SMMU_CB_TTBCR,
260 pgtbl_cfg.arm_lpae_s1_cfg.tcr);
262 /* MAIRs (stage-1 only) */
263 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
264 pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);
265 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
266 pgtbl_cfg.arm_lpae_s1_cfg.mair[1]);
269 reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |
270 SCTLR_M | SCTLR_S1_ASIDPNE | SCTLR_CFCFG;
272 if (IS_ENABLED(CONFIG_BIG_ENDIAN))
275 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
277 ctx->domain = domain;
280 mutex_unlock(&qcom_domain->init_mutex);
282 /* Publish page table ops for map/unmap */
283 qcom_domain->pgtbl_ops = pgtbl_ops;
288 qcom_domain->iommu = NULL;
290 mutex_unlock(&qcom_domain->init_mutex);
294 static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type)
296 struct qcom_iommu_domain *qcom_domain;
298 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
301 * Allocate the domain and initialise some of its data structures.
302 * We can't really do anything meaningful until we've added a
305 qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
309 if (type == IOMMU_DOMAIN_DMA &&
310 iommu_get_dma_cookie(&qcom_domain->domain)) {
315 mutex_init(&qcom_domain->init_mutex);
316 spin_lock_init(&qcom_domain->pgtbl_lock);
318 return &qcom_domain->domain;
321 static void qcom_iommu_domain_free(struct iommu_domain *domain)
323 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
325 if (WARN_ON(qcom_domain->iommu)) /* forgot to detach? */
328 iommu_put_dma_cookie(domain);
330 /* NOTE: unmap can be called after client device is powered off,
331 * for example, with GPUs or anything involving dma-buf. So we
332 * cannot rely on the device_link. Make sure the IOMMU is on to
333 * avoid unclocked accesses in the TLB inv path:
335 pm_runtime_get_sync(qcom_domain->iommu->dev);
337 free_io_pgtable_ops(qcom_domain->pgtbl_ops);
339 pm_runtime_put_sync(qcom_domain->iommu->dev);
344 static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
346 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
347 struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
348 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
352 dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
356 /* Ensure that the domain is finalized */
357 pm_runtime_get_sync(qcom_iommu->dev);
358 ret = qcom_iommu_init_domain(domain, qcom_iommu, fwspec);
359 pm_runtime_put_sync(qcom_iommu->dev);
364 * Sanity check the domain. We don't support domains across
367 if (qcom_domain->iommu != qcom_iommu) {
368 dev_err(dev, "cannot attach to IOMMU %s while already "
369 "attached to domain on IOMMU %s\n",
370 dev_name(qcom_domain->iommu->dev),
371 dev_name(qcom_iommu->dev));
378 static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev)
380 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
381 struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
382 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
385 if (!qcom_domain->iommu)
388 pm_runtime_get_sync(qcom_iommu->dev);
389 for (i = 0; i < fwspec->num_ids; i++) {
390 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
392 /* Disable the context bank: */
393 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
397 pm_runtime_put_sync(qcom_iommu->dev);
399 qcom_domain->iommu = NULL;
402 static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
403 phys_addr_t paddr, size_t size, int prot)
407 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
408 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
413 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
414 ret = ops->map(ops, iova, paddr, size, prot);
415 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
419 static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
424 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
425 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
430 /* NOTE: unmap can be called after client device is powered off,
431 * for example, with GPUs or anything involving dma-buf. So we
432 * cannot rely on the device_link. Make sure the IOMMU is on to
433 * avoid unclocked accesses in the TLB inv path:
435 pm_runtime_get_sync(qcom_domain->iommu->dev);
436 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
437 ret = ops->unmap(ops, iova, size);
438 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
439 pm_runtime_put_sync(qcom_domain->iommu->dev);
444 static void qcom_iommu_iotlb_sync(struct iommu_domain *domain)
446 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
447 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
448 struct io_pgtable, ops);
449 if (!qcom_domain->pgtbl_ops)
452 pm_runtime_get_sync(qcom_domain->iommu->dev);
453 qcom_iommu_tlb_sync(pgtable->cookie);
454 pm_runtime_put_sync(qcom_domain->iommu->dev);
457 static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
462 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
463 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
468 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
469 ret = ops->iova_to_phys(ops, iova);
470 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
475 static bool qcom_iommu_capable(enum iommu_cap cap)
478 case IOMMU_CAP_CACHE_COHERENCY:
480 * Return true here as the SMMU can always send out coherent
484 case IOMMU_CAP_NOEXEC:
491 static int qcom_iommu_add_device(struct device *dev)
493 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev_iommu_fwspec_get(dev));
494 struct iommu_group *group;
495 struct device_link *link;
501 * Establish the link between iommu and master, so that the
502 * iommu gets runtime enabled/disabled as per the master's
505 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
507 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
508 dev_name(qcom_iommu->dev), dev_name(dev));
512 group = iommu_group_get_for_dev(dev);
513 if (IS_ERR_OR_NULL(group))
514 return PTR_ERR_OR_ZERO(group);
516 iommu_group_put(group);
517 iommu_device_link(&qcom_iommu->iommu, dev);
522 static void qcom_iommu_remove_device(struct device *dev)
524 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev_iommu_fwspec_get(dev));
529 iommu_device_unlink(&qcom_iommu->iommu, dev);
530 iommu_group_remove_device(dev);
531 iommu_fwspec_free(dev);
534 static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
536 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
537 struct qcom_iommu_dev *qcom_iommu;
538 struct platform_device *iommu_pdev;
539 unsigned asid = args->args[0];
541 if (args->args_count != 1) {
542 dev_err(dev, "incorrect number of iommu params found for %s "
543 "(found %d, expected 1)\n",
544 args->np->full_name, args->args_count);
548 iommu_pdev = of_find_device_by_node(args->np);
549 if (WARN_ON(!iommu_pdev))
552 qcom_iommu = platform_get_drvdata(iommu_pdev);
554 /* make sure the asid specified in dt is valid, so we don't have
555 * to sanity check this elsewhere, since 'asid - 1' is used to
556 * index into qcom_iommu->ctxs:
558 if (WARN_ON(asid < 1) ||
559 WARN_ON(asid > qcom_iommu->num_ctxs))
562 if (!fwspec->iommu_priv) {
563 fwspec->iommu_priv = qcom_iommu;
565 /* make sure devices iommus dt node isn't referring to
566 * multiple different iommu devices. Multiple context
567 * banks are ok, but multiple devices are not:
569 if (WARN_ON(qcom_iommu != fwspec->iommu_priv))
573 return iommu_fwspec_add_ids(dev, &asid, 1);
576 static const struct iommu_ops qcom_iommu_ops = {
577 .capable = qcom_iommu_capable,
578 .domain_alloc = qcom_iommu_domain_alloc,
579 .domain_free = qcom_iommu_domain_free,
580 .attach_dev = qcom_iommu_attach_dev,
581 .detach_dev = qcom_iommu_detach_dev,
582 .map = qcom_iommu_map,
583 .unmap = qcom_iommu_unmap,
584 .flush_iotlb_all = qcom_iommu_iotlb_sync,
585 .iotlb_sync = qcom_iommu_iotlb_sync,
586 .iova_to_phys = qcom_iommu_iova_to_phys,
587 .add_device = qcom_iommu_add_device,
588 .remove_device = qcom_iommu_remove_device,
589 .device_group = generic_device_group,
590 .of_xlate = qcom_iommu_of_xlate,
591 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
594 static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu)
598 ret = clk_prepare_enable(qcom_iommu->iface_clk);
600 dev_err(qcom_iommu->dev, "Couldn't enable iface_clk\n");
604 ret = clk_prepare_enable(qcom_iommu->bus_clk);
606 dev_err(qcom_iommu->dev, "Couldn't enable bus_clk\n");
607 clk_disable_unprepare(qcom_iommu->iface_clk);
614 static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu)
616 clk_disable_unprepare(qcom_iommu->bus_clk);
617 clk_disable_unprepare(qcom_iommu->iface_clk);
620 static int qcom_iommu_sec_ptbl_init(struct device *dev)
623 unsigned int spare = 0;
627 static bool allocated = false;
633 ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
635 dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
640 dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
642 attrs = DMA_ATTR_NO_KERNEL_MAPPING;
644 cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
646 dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
651 ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
653 dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
661 dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
665 static int get_asid(const struct device_node *np)
669 /* read the "reg" property directly to get the relative address
670 * of the context bank, and calculate the asid from that:
672 if (of_property_read_u32_index(np, "reg", 0, ®))
675 return reg / 0x1000; /* context banks are 0x1000 apart */
678 static int qcom_iommu_ctx_probe(struct platform_device *pdev)
680 struct qcom_iommu_ctx *ctx;
681 struct device *dev = &pdev->dev;
682 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
683 struct resource *res;
686 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
691 platform_set_drvdata(pdev, ctx);
693 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
694 ctx->base = devm_ioremap_resource(dev, res);
695 if (IS_ERR(ctx->base))
696 return PTR_ERR(ctx->base);
698 irq = platform_get_irq(pdev, 0);
700 dev_err(dev, "failed to get irq\n");
704 /* clear IRQs before registering fault handler, just in case the
705 * boot-loader left us a surprise:
707 iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
709 ret = devm_request_irq(dev, irq,
715 dev_err(dev, "failed to request IRQ %u\n", irq);
719 ret = get_asid(dev->of_node);
721 dev_err(dev, "missing reg property\n");
727 dev_dbg(dev, "found asid %u\n", ctx->asid);
729 qcom_iommu->ctxs[ctx->asid - 1] = ctx;
734 static int qcom_iommu_ctx_remove(struct platform_device *pdev)
736 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
737 struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
739 platform_set_drvdata(pdev, NULL);
741 qcom_iommu->ctxs[ctx->asid - 1] = NULL;
746 static const struct of_device_id ctx_of_match[] = {
747 { .compatible = "qcom,msm-iommu-v1-ns" },
748 { .compatible = "qcom,msm-iommu-v1-sec" },
752 static struct platform_driver qcom_iommu_ctx_driver = {
754 .name = "qcom-iommu-ctx",
755 .of_match_table = of_match_ptr(ctx_of_match),
757 .probe = qcom_iommu_ctx_probe,
758 .remove = qcom_iommu_ctx_remove,
761 static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
763 struct device_node *child;
765 for_each_child_of_node(qcom_iommu->dev->of_node, child)
766 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec"))
772 static int qcom_iommu_device_probe(struct platform_device *pdev)
774 struct device_node *child;
775 struct qcom_iommu_dev *qcom_iommu;
776 struct device *dev = &pdev->dev;
777 struct resource *res;
778 int ret, sz, max_asid = 0;
780 /* find the max asid (which is 1:1 to ctx bank idx), so we know how
781 * many child ctx devices we have:
783 for_each_child_of_node(dev->of_node, child)
784 max_asid = max(max_asid, get_asid(child));
786 sz = sizeof(*qcom_iommu) + (max_asid * sizeof(qcom_iommu->ctxs[0]));
788 qcom_iommu = devm_kzalloc(dev, sz, GFP_KERNEL);
791 qcom_iommu->num_ctxs = max_asid;
792 qcom_iommu->dev = dev;
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
796 qcom_iommu->local_base = devm_ioremap_resource(dev, res);
798 qcom_iommu->iface_clk = devm_clk_get(dev, "iface");
799 if (IS_ERR(qcom_iommu->iface_clk)) {
800 dev_err(dev, "failed to get iface clock\n");
801 return PTR_ERR(qcom_iommu->iface_clk);
804 qcom_iommu->bus_clk = devm_clk_get(dev, "bus");
805 if (IS_ERR(qcom_iommu->bus_clk)) {
806 dev_err(dev, "failed to get bus clock\n");
807 return PTR_ERR(qcom_iommu->bus_clk);
810 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
811 &qcom_iommu->sec_id)) {
812 dev_err(dev, "missing qcom,iommu-secure-id property\n");
816 if (qcom_iommu_has_secure_context(qcom_iommu)) {
817 ret = qcom_iommu_sec_ptbl_init(dev);
819 dev_err(dev, "cannot init secure pg table(%d)\n", ret);
824 platform_set_drvdata(pdev, qcom_iommu);
826 pm_runtime_enable(dev);
828 /* register context bank devices, which are child nodes: */
829 ret = devm_of_platform_populate(dev);
831 dev_err(dev, "Failed to populate iommu contexts\n");
835 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
838 dev_err(dev, "Failed to register iommu in sysfs\n");
842 iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops);
843 iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode);
845 ret = iommu_device_register(&qcom_iommu->iommu);
847 dev_err(dev, "Failed to register iommu\n");
851 bus_set_iommu(&platform_bus_type, &qcom_iommu_ops);
853 if (qcom_iommu->local_base) {
854 pm_runtime_get_sync(dev);
855 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
856 pm_runtime_put_sync(dev);
862 static int qcom_iommu_device_remove(struct platform_device *pdev)
864 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
866 bus_set_iommu(&platform_bus_type, NULL);
868 pm_runtime_force_suspend(&pdev->dev);
869 platform_set_drvdata(pdev, NULL);
870 iommu_device_sysfs_remove(&qcom_iommu->iommu);
871 iommu_device_unregister(&qcom_iommu->iommu);
876 static int __maybe_unused qcom_iommu_resume(struct device *dev)
878 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
880 return qcom_iommu_enable_clocks(qcom_iommu);
883 static int __maybe_unused qcom_iommu_suspend(struct device *dev)
885 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
887 qcom_iommu_disable_clocks(qcom_iommu);
892 static const struct dev_pm_ops qcom_iommu_pm_ops = {
893 SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
894 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
895 pm_runtime_force_resume)
898 static const struct of_device_id qcom_iommu_of_match[] = {
899 { .compatible = "qcom,msm-iommu-v1" },
903 static struct platform_driver qcom_iommu_driver = {
905 .name = "qcom-iommu",
906 .of_match_table = of_match_ptr(qcom_iommu_of_match),
907 .pm = &qcom_iommu_pm_ops,
909 .probe = qcom_iommu_device_probe,
910 .remove = qcom_iommu_device_remove,
913 static int __init qcom_iommu_init(void)
917 ret = platform_driver_register(&qcom_iommu_ctx_driver);
921 ret = platform_driver_register(&qcom_iommu_driver);
923 platform_driver_unregister(&qcom_iommu_ctx_driver);
927 device_initcall(qcom_iommu_init);