1 menu "IRQ chip support"
9 select IRQ_DOMAIN_HIERARCHY
10 select GENERIC_IRQ_MULTI_HANDLER
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
21 default 2 if ARCH_REALVIEW
35 select GENERIC_IRQ_MULTI_HANDLER
36 select IRQ_DOMAIN_HIERARCHY
37 select PARTITION_PERCPU
38 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
42 select GENERIC_MSI_IRQ_DOMAIN
45 config ARM_GIC_V3_ITS_PCI
47 depends on ARM_GIC_V3_ITS
50 default ARM_GIC_V3_ITS
52 config ARM_GIC_V3_ITS_FSL_MC
54 depends on ARM_GIC_V3_ITS
56 default ARM_GIC_V3_ITS
60 select IRQ_DOMAIN_HIERARCHY
61 select GENERIC_IRQ_CHIP
66 select GENERIC_IRQ_MULTI_HANDLER
70 default 4 if ARCH_S5PV210
74 The maximum number of VICs available in the system, for
77 config ARMADA_370_XP_IRQ
79 select GENERIC_IRQ_CHIP
81 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
87 select GENERIC_IRQ_CHIP
91 select GENERIC_IRQ_CHIP
93 select GENERIC_IRQ_MULTI_HANDLER
98 select GENERIC_IRQ_CHIP
100 select GENERIC_IRQ_MULTI_HANDLER
107 config BCM6345_L1_IRQ
109 select GENERIC_IRQ_CHIP
111 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
113 config BCM7038_L1_IRQ
115 select GENERIC_IRQ_CHIP
117 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
119 config BCM7120_L2_IRQ
121 select GENERIC_IRQ_CHIP
124 config BRCMSTB_L2_IRQ
126 select GENERIC_IRQ_CHIP
131 select GENERIC_IRQ_CHIP
134 config DAVINCI_CP_INTC
136 select GENERIC_IRQ_CHIP
141 select GENERIC_IRQ_CHIP
144 config FARADAY_FTINTC010
147 select GENERIC_IRQ_MULTI_HANDLER
150 config HISILICON_IRQ_MBIGEN
153 select ARM_GIC_V3_ITS
157 select GENERIC_IRQ_CHIP
165 select GENERIC_IRQ_CHIP
166 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
168 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
169 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
171 config CLPS711X_IRQCHIP
173 depends on ARCH_CLPS711X
175 select GENERIC_IRQ_MULTI_HANDLER
188 select GENERIC_IRQ_CHIP
194 select GENERIC_IRQ_MULTI_HANDLER
198 select GENERIC_IRQ_CHIP
202 bool "J-Core integrated AIC" if COMPILE_TEST
206 Support for the J-Core integrated AIC.
212 config RENESAS_INTC_IRQPIN
218 select GENERIC_IRQ_CHIP
226 Enables SysCfg Controlled IRQs on STi based platforms.
231 select GENERIC_IRQ_CHIP
236 select GENERIC_IRQ_CHIP
239 tristate "TS-4800 IRQ controller"
242 depends on SOC_IMX51 || COMPILE_TEST
244 Support for the TS-4800 FPGA IRQ controller
246 config VERSATILE_FPGA_IRQ
250 config VERSATILE_FPGA_IRQ_NR
253 depends on VERSATILE_FPGA_IRQ
258 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
267 Support for a CROSSBAR ip that precedes the main interrupt controller.
268 The primary irqchip invokes the crossbar's callback which inturn allocates
269 a free irq and configures the IP. Thus the peripheral interrupts are
270 routed to one of the free irqchip interrupt lines.
273 tristate "Keystone 2 IRQ controller IP"
274 depends on ARCH_KEYSTONE
276 Support for Texas Instruments Keystone 2 IRQ controller IP which
277 is part of the Keystone 2 IPC mechanism
281 select GENERIC_IRQ_IPI
282 select IRQ_DOMAIN_HIERARCHY
287 depends on MACH_INGENIC
290 config RENESAS_H8300H_INTC
294 config RENESAS_H8S_INTC
302 Enables the wakeup IRQs for IMX platforms with GPCv2 block
305 def_bool y if MACH_ASM9260 || ARCH_MXS
309 config MSCC_OCELOT_IRQ
312 select GENERIC_IRQ_CHIP
322 select GENERIC_MSI_IRQ_DOMAIN
331 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
332 depends on PCI && PCI_MSI
334 config PARTITION_PERCPU
338 bool "NPS400 Global Interrupt Manager (GIM)"
339 depends on ARC || (COMPILE_TEST && !64BIT)
342 Support the EZchip NPS400 global interrupt controller
347 select GENERIC_IRQ_CHIP
349 config QCOM_IRQ_COMBINER
350 bool "QCOM IRQ combiner support"
351 depends on ARCH_QCOM && ACPI
352 select IRQ_DOMAIN_HIERARCHY
354 Say yes here to add support for the IRQ combiner devices embedded
355 in Qualcomm Technologies chips.
357 config IRQ_UNIPHIER_AIDET
358 bool "UniPhier AIDET support" if COMPILE_TEST
359 depends on ARCH_UNIPHIER || COMPILE_TEST
360 default ARCH_UNIPHIER
361 select IRQ_DOMAIN_HIERARCHY
363 Support for the UniPhier AIDET (ARM Interrupt Detector).
365 config MESON_IRQ_GPIO
366 bool "Meson GPIO Interrupt Multiplexer"
367 depends on ARCH_MESON
368 select IRQ_DOMAIN_HIERARCHY
370 Support Meson SoC Family GPIO Interrupt Multiplexer
373 bool "Goldfish programmable interrupt controller"
374 depends on MIPS && (GOLDFISH || COMPILE_TEST)
377 Say yes here to enable Goldfish interrupt controller driver used
378 for Goldfish based virtual platforms.
383 select IRQ_DOMAIN_HIERARCHY
385 Power Domain Controller driver to manage and configure wakeup
386 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
389 bool "C-SKY Multi Processor Interrupt Controller"
392 Say yes here to enable C-SKY SMP interrupt controller driver used
393 for C-SKY SMP system.
394 In fact it's not mmio map in hw and it use ld/st to visit the
395 controller's register inside CPU.
398 bool "C-SKY APB Interrupt Controller"
401 Say yes here to enable C-SKY APB interrupt controller driver used
402 by C-SKY single core SOC system. It use mmio map apb-bus to visit
403 the controller's register.
406 bool "i.MX IRQSTEER support"
407 depends on ARCH_MXC || COMPILE_TEST
411 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
414 bool "Loongson-1 Interrupt Controller"
415 depends on MACH_LOONGSON32
418 select GENERIC_IRQ_CHIP
420 Support for the Loongson-1 platform Interrupt Controller.
422 config TI_SCI_INTR_IRQCHIP
424 depends on TI_SCI_PROTOCOL
425 select IRQ_DOMAIN_HIERARCHY
427 This enables the irqchip driver support for K3 Interrupt router
428 over TI System Control Interface available on some new TI's SoCs.
429 If you wish to use interrupt router irq resources managed by the
430 TI System Controller, say Y here. Otherwise, say N.
432 config TI_SCI_INTA_IRQCHIP
434 depends on TI_SCI_PROTOCOL
435 select IRQ_DOMAIN_HIERARCHY
437 This enables the irqchip driver support for K3 Interrupt aggregator
438 over TI System Control Interface available on some new TI's SoCs.
439 If you wish to use interrupt aggregator irq resources managed by the
440 TI System Controller, say Y here. Otherwise, say N.
445 bool "SiFive Platform-Level Interrupt Controller"
448 This enables support for the PLIC chip found in SiFive (and
449 potentially other) RISC-V systems. The PLIC controls devices
450 interrupts and connects them to each core's local interrupt
451 controller. Aside from timer and software interrupts, all other
452 interrupt sources are subordinate to the PLIC.
454 If you don't know what to do here, say Y.