1 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_MULTI_HANDLER
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
22 default 2 if ARCH_REALVIEW
37 select GENERIC_IRQ_MULTI_HANDLER
38 select IRQ_DOMAIN_HIERARCHY
39 select PARTITION_PERCPU
40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
44 select GENERIC_MSI_IRQ_DOMAIN
47 config ARM_GIC_V3_ITS_PCI
49 depends on ARM_GIC_V3_ITS
52 default ARM_GIC_V3_ITS
54 config ARM_GIC_V3_ITS_FSL_MC
56 depends on ARM_GIC_V3_ITS
58 default ARM_GIC_V3_ITS
63 select IRQ_DOMAIN_HIERARCHY
64 select GENERIC_IRQ_CHIP
69 select GENERIC_IRQ_MULTI_HANDLER
73 default 4 if ARCH_S5PV210
77 The maximum number of VICs available in the system, for
80 config ARMADA_370_XP_IRQ
82 select GENERIC_IRQ_CHIP
84 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
90 select GENERIC_IRQ_CHIP
94 select GENERIC_IRQ_CHIP
96 select GENERIC_IRQ_MULTI_HANDLER
101 select GENERIC_IRQ_CHIP
103 select GENERIC_IRQ_MULTI_HANDLER
110 config BCM6345_L1_IRQ
112 select GENERIC_IRQ_CHIP
114 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
116 config BCM7038_L1_IRQ
118 select GENERIC_IRQ_CHIP
120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
122 config BCM7120_L2_IRQ
124 select GENERIC_IRQ_CHIP
127 config BRCMSTB_L2_IRQ
129 select GENERIC_IRQ_CHIP
134 select GENERIC_IRQ_CHIP
137 config FARADAY_FTINTC010
140 select GENERIC_IRQ_MULTI_HANDLER
143 config HISILICON_IRQ_MBIGEN
146 select ARM_GIC_V3_ITS
150 select GENERIC_IRQ_CHIP
158 select GENERIC_IRQ_CHIP
159 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
161 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
162 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
164 config CLPS711X_IRQCHIP
166 depends on ARCH_CLPS711X
168 select GENERIC_IRQ_MULTI_HANDLER
181 select GENERIC_IRQ_CHIP
187 select GENERIC_IRQ_MULTI_HANDLER
191 select GENERIC_IRQ_CHIP
195 bool "J-Core integrated AIC" if COMPILE_TEST
199 Support for the J-Core integrated AIC.
205 config RENESAS_INTC_IRQPIN
211 select GENERIC_IRQ_CHIP
219 Enables SysCfg Controlled IRQs on STi based platforms.
224 select GENERIC_IRQ_CHIP
229 select GENERIC_IRQ_CHIP
232 tristate "TS-4800 IRQ controller"
235 depends on SOC_IMX51 || COMPILE_TEST
237 Support for the TS-4800 FPGA IRQ controller
239 config VERSATILE_FPGA_IRQ
243 config VERSATILE_FPGA_IRQ_NR
246 depends on VERSATILE_FPGA_IRQ
251 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
260 Support for a CROSSBAR ip that precedes the main interrupt controller.
261 The primary irqchip invokes the crossbar's callback which inturn allocates
262 a free irq and configures the IP. Thus the peripheral interrupts are
263 routed to one of the free irqchip interrupt lines.
266 tristate "Keystone 2 IRQ controller IP"
267 depends on ARCH_KEYSTONE
269 Support for Texas Instruments Keystone 2 IRQ controller IP which
270 is part of the Keystone 2 IPC mechanism
274 select GENERIC_IRQ_IPI
275 select IRQ_DOMAIN_HIERARCHY
280 depends on MACH_INGENIC
283 config RENESAS_H8300H_INTC
287 config RENESAS_H8S_INTC
295 Enables the wakeup IRQs for IMX platforms with GPCv2 block
298 def_bool y if MACH_ASM9260 || ARCH_MXS
302 config MSCC_OCELOT_IRQ
305 select GENERIC_IRQ_CHIP
315 select GENERIC_MSI_IRQ_DOMAIN
324 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
325 depends on PCI && PCI_MSI
327 config PARTITION_PERCPU
331 bool "NPS400 Global Interrupt Manager (GIM)"
332 depends on ARC || (COMPILE_TEST && !64BIT)
335 Support the EZchip NPS400 global interrupt controller
340 select GENERIC_IRQ_CHIP
342 config QCOM_IRQ_COMBINER
343 bool "QCOM IRQ combiner support"
344 depends on ARCH_QCOM && ACPI
346 select IRQ_DOMAIN_HIERARCHY
348 Say yes here to add support for the IRQ combiner devices embedded
349 in Qualcomm Technologies chips.
351 config IRQ_UNIPHIER_AIDET
352 bool "UniPhier AIDET support" if COMPILE_TEST
353 depends on ARCH_UNIPHIER || COMPILE_TEST
354 default ARCH_UNIPHIER
355 select IRQ_DOMAIN_HIERARCHY
357 Support for the UniPhier AIDET (ARM Interrupt Detector).
359 config MESON_IRQ_GPIO
360 bool "Meson GPIO Interrupt Multiplexer"
361 depends on ARCH_MESON
363 select IRQ_DOMAIN_HIERARCHY
365 Support Meson SoC Family GPIO Interrupt Multiplexer
368 bool "Goldfish programmable interrupt controller"
369 depends on MIPS && (GOLDFISH || COMPILE_TEST)
372 Say yes here to enable Goldfish interrupt controller driver used
373 for Goldfish based virtual platforms.
379 select IRQ_DOMAIN_HIERARCHY
381 Power Domain Controller driver to manage and configure wakeup
382 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
385 bool "C-SKY Multi Processor Interrupt Controller"
388 Say yes here to enable C-SKY SMP interrupt controller driver used
389 for C-SKY SMP system.
390 In fact it's not mmio map in hw and it use ld/st to visit the
391 controller's register inside CPU.
394 bool "C-SKY APB Interrupt Controller"
397 Say yes here to enable C-SKY APB interrupt controller driver used
398 by C-SKY single core SOC system. It use mmio map apb-bus to visit
399 the controller's register.
402 bool "i.MX IRQSTEER support"
403 depends on ARCH_MXC || COMPILE_TEST
407 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
412 bool "SiFive Platform-Level Interrupt Controller"
415 This enables support for the PLIC chip found in SiFive (and
416 potentially other) RISC-V systems. The PLIC controls devices
417 interrupts and connects them to each core's local interrupt
418 controller. Aside from timer and software interrupts, all other
419 interrupt sources are subordinate to the PLIC.
421 If you don't know what to do here, say Y.