1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_MULTI_HANDLER
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
22 default 2 if ARCH_REALVIEW
36 select GENERIC_IRQ_MULTI_HANDLER
37 select IRQ_DOMAIN_HIERARCHY
38 select PARTITION_PERCPU
39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
43 select GENERIC_MSI_IRQ_DOMAIN
46 config ARM_GIC_V3_ITS_PCI
48 depends on ARM_GIC_V3_ITS
51 default ARM_GIC_V3_ITS
53 config ARM_GIC_V3_ITS_FSL_MC
55 depends on ARM_GIC_V3_ITS
57 default ARM_GIC_V3_ITS
61 select IRQ_DOMAIN_HIERARCHY
62 select GENERIC_IRQ_CHIP
67 select GENERIC_IRQ_MULTI_HANDLER
71 default 4 if ARCH_S5PV210
75 The maximum number of VICs available in the system, for
78 config ARMADA_370_XP_IRQ
80 select GENERIC_IRQ_CHIP
82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
88 select GENERIC_IRQ_CHIP
92 select GENERIC_IRQ_CHIP
94 select GENERIC_IRQ_MULTI_HANDLER
99 select GENERIC_IRQ_CHIP
101 select GENERIC_IRQ_MULTI_HANDLER
108 config BCM6345_L1_IRQ
110 select GENERIC_IRQ_CHIP
112 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
114 config BCM7038_L1_IRQ
116 select GENERIC_IRQ_CHIP
118 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
120 config BCM7120_L2_IRQ
122 select GENERIC_IRQ_CHIP
125 config BRCMSTB_L2_IRQ
127 select GENERIC_IRQ_CHIP
132 select GENERIC_IRQ_CHIP
135 config DAVINCI_CP_INTC
137 select GENERIC_IRQ_CHIP
142 select GENERIC_IRQ_CHIP
145 config FARADAY_FTINTC010
148 select GENERIC_IRQ_MULTI_HANDLER
151 config HISILICON_IRQ_MBIGEN
154 select ARM_GIC_V3_ITS
158 select GENERIC_IRQ_CHIP
164 select GENERIC_IRQ_MULTI_HANDLER
172 select GENERIC_IRQ_CHIP
173 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
175 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
178 config CLPS711X_IRQCHIP
180 depends on ARCH_CLPS711X
182 select GENERIC_IRQ_MULTI_HANDLER
195 select GENERIC_IRQ_CHIP
201 select GENERIC_IRQ_MULTI_HANDLER
205 select GENERIC_IRQ_CHIP
209 bool "J-Core integrated AIC" if COMPILE_TEST
213 Support for the J-Core integrated AIC.
219 config RENESAS_INTC_IRQPIN
225 select GENERIC_IRQ_CHIP
233 Enables SysCfg Controlled IRQs on STi based platforms.
238 select GENERIC_IRQ_CHIP
243 select GENERIC_IRQ_CHIP
246 tristate "TS-4800 IRQ controller"
249 depends on SOC_IMX51 || COMPILE_TEST
251 Support for the TS-4800 FPGA IRQ controller
253 config VERSATILE_FPGA_IRQ
257 config VERSATILE_FPGA_IRQ_NR
260 depends on VERSATILE_FPGA_IRQ
265 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
274 Support for a CROSSBAR ip that precedes the main interrupt controller.
275 The primary irqchip invokes the crossbar's callback which inturn allocates
276 a free irq and configures the IP. Thus the peripheral interrupts are
277 routed to one of the free irqchip interrupt lines.
280 tristate "Keystone 2 IRQ controller IP"
281 depends on ARCH_KEYSTONE
283 Support for Texas Instruments Keystone 2 IRQ controller IP which
284 is part of the Keystone 2 IPC mechanism
288 select GENERIC_IRQ_IPI
289 select IRQ_DOMAIN_HIERARCHY
294 depends on MACH_INGENIC
297 config RENESAS_H8300H_INTC
301 config RENESAS_H8S_INTC
309 Enables the wakeup IRQs for IMX platforms with GPCv2 block
312 def_bool y if MACH_ASM9260 || ARCH_MXS
316 config MSCC_OCELOT_IRQ
319 select GENERIC_IRQ_CHIP
329 select GENERIC_MSI_IRQ_DOMAIN
338 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
339 depends on PCI && PCI_MSI
341 config PARTITION_PERCPU
345 bool "NPS400 Global Interrupt Manager (GIM)"
346 depends on ARC || (COMPILE_TEST && !64BIT)
349 Support the EZchip NPS400 global interrupt controller
354 select GENERIC_IRQ_CHIP
356 config QCOM_IRQ_COMBINER
357 bool "QCOM IRQ combiner support"
358 depends on ARCH_QCOM && ACPI
359 select IRQ_DOMAIN_HIERARCHY
361 Say yes here to add support for the IRQ combiner devices embedded
362 in Qualcomm Technologies chips.
364 config IRQ_UNIPHIER_AIDET
365 bool "UniPhier AIDET support" if COMPILE_TEST
366 depends on ARCH_UNIPHIER || COMPILE_TEST
367 default ARCH_UNIPHIER
368 select IRQ_DOMAIN_HIERARCHY
370 Support for the UniPhier AIDET (ARM Interrupt Detector).
372 config MESON_IRQ_GPIO
373 bool "Meson GPIO Interrupt Multiplexer"
374 depends on ARCH_MESON
375 select IRQ_DOMAIN_HIERARCHY
377 Support Meson SoC Family GPIO Interrupt Multiplexer
380 bool "Goldfish programmable interrupt controller"
381 depends on MIPS && (GOLDFISH || COMPILE_TEST)
384 Say yes here to enable Goldfish interrupt controller driver used
385 for Goldfish based virtual platforms.
390 select IRQ_DOMAIN_HIERARCHY
392 Power Domain Controller driver to manage and configure wakeup
393 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
396 bool "C-SKY Multi Processor Interrupt Controller"
399 Say yes here to enable C-SKY SMP interrupt controller driver used
400 for C-SKY SMP system.
401 In fact it's not mmio map in hw and it use ld/st to visit the
402 controller's register inside CPU.
405 bool "C-SKY APB Interrupt Controller"
408 Say yes here to enable C-SKY APB interrupt controller driver used
409 by C-SKY single core SOC system. It use mmio map apb-bus to visit
410 the controller's register.
413 bool "i.MX IRQSTEER support"
414 depends on ARCH_MXC || COMPILE_TEST
418 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
421 bool "Loongson-1 Interrupt Controller"
422 depends on MACH_LOONGSON32
425 select GENERIC_IRQ_CHIP
427 Support for the Loongson-1 platform Interrupt Controller.
429 config TI_SCI_INTR_IRQCHIP
431 depends on TI_SCI_PROTOCOL
432 select IRQ_DOMAIN_HIERARCHY
434 This enables the irqchip driver support for K3 Interrupt router
435 over TI System Control Interface available on some new TI's SoCs.
436 If you wish to use interrupt router irq resources managed by the
437 TI System Controller, say Y here. Otherwise, say N.
439 config TI_SCI_INTA_IRQCHIP
441 depends on TI_SCI_PROTOCOL
442 select IRQ_DOMAIN_HIERARCHY
443 select TI_SCI_INTA_MSI_DOMAIN
445 This enables the irqchip driver support for K3 Interrupt aggregator
446 over TI System Control Interface available on some new TI's SoCs.
447 If you wish to use interrupt aggregator irq resources managed by the
448 TI System Controller, say Y here. Otherwise, say N.
453 bool "SiFive Platform-Level Interrupt Controller"
456 This enables support for the PLIC chip found in SiFive (and
457 potentially other) RISC-V systems. The PLIC controls devices
458 interrupts and connects them to each core's local interrupt
459 controller. Aside from timer and software interrupts, all other
460 interrupt sources are subordinate to the PLIC.
462 If you don't know what to do here, say Y.