1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_MULTI_HANDLER
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
22 default 2 if ARCH_REALVIEW
36 select GENERIC_IRQ_MULTI_HANDLER
37 select IRQ_DOMAIN_HIERARCHY
38 select PARTITION_PERCPU
39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
43 select GENERIC_MSI_IRQ_DOMAIN
46 config ARM_GIC_V3_ITS_PCI
48 depends on ARM_GIC_V3_ITS
51 default ARM_GIC_V3_ITS
53 config ARM_GIC_V3_ITS_FSL_MC
55 depends on ARM_GIC_V3_ITS
57 default ARM_GIC_V3_ITS
61 select IRQ_DOMAIN_HIERARCHY
62 select GENERIC_IRQ_CHIP
67 select GENERIC_IRQ_MULTI_HANDLER
71 default 4 if ARCH_S5PV210
75 The maximum number of VICs available in the system, for
78 config ARMADA_370_XP_IRQ
80 select GENERIC_IRQ_CHIP
82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
88 select GENERIC_IRQ_CHIP
91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
92 depends on OF || COMPILE_TEST
93 select GENERIC_IRQ_CHIP
96 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
100 select GENERIC_IRQ_CHIP
102 select GENERIC_IRQ_MULTI_HANDLER
105 config ATMEL_AIC5_IRQ
107 select GENERIC_IRQ_CHIP
109 select GENERIC_IRQ_MULTI_HANDLER
116 config BCM6345_L1_IRQ
118 select GENERIC_IRQ_CHIP
120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
122 config BCM7038_L1_IRQ
124 select GENERIC_IRQ_CHIP
126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
128 config BCM7120_L2_IRQ
130 select GENERIC_IRQ_CHIP
133 config BRCMSTB_L2_IRQ
135 select GENERIC_IRQ_CHIP
140 select GENERIC_IRQ_CHIP
143 config DAVINCI_CP_INTC
145 select GENERIC_IRQ_CHIP
150 select GENERIC_IRQ_CHIP
153 config FARADAY_FTINTC010
156 select GENERIC_IRQ_MULTI_HANDLER
159 config HISILICON_IRQ_MBIGEN
162 select ARM_GIC_V3_ITS
166 select GENERIC_IRQ_CHIP
172 select GENERIC_IRQ_MULTI_HANDLER
180 select GENERIC_IRQ_CHIP
181 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
183 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
184 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
186 config CLPS711X_IRQCHIP
188 depends on ARCH_CLPS711X
190 select GENERIC_IRQ_MULTI_HANDLER
203 select GENERIC_IRQ_CHIP
209 select GENERIC_IRQ_MULTI_HANDLER
213 select GENERIC_IRQ_CHIP
217 bool "J-Core integrated AIC" if COMPILE_TEST
221 Support for the J-Core integrated AIC.
227 config RENESAS_INTC_IRQPIN
228 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
231 Enable support for the Renesas Interrupt Controller for external
232 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
235 bool "Renesas R-Mobile APE6 and R-Car IRQC support" if COMPILE_TEST
236 select GENERIC_IRQ_CHIP
239 Enable support for the Renesas Interrupt Controller for external
240 devices, as found on R-Mobile APE6, R-Car Gen2, and R-Car Gen3 SoCs.
242 config RENESAS_RZA1_IRQC
243 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
244 select IRQ_DOMAIN_HIERARCHY
246 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
247 to 8 external interrupts with configurable sense select.
254 Enables SysCfg Controlled IRQs on STi based platforms.
259 select GENERIC_IRQ_CHIP
264 select GENERIC_IRQ_CHIP
267 tristate "TS-4800 IRQ controller"
270 depends on SOC_IMX51 || COMPILE_TEST
272 Support for the TS-4800 FPGA IRQ controller
274 config VERSATILE_FPGA_IRQ
278 config VERSATILE_FPGA_IRQ_NR
281 depends on VERSATILE_FPGA_IRQ
286 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
295 Support for a CROSSBAR ip that precedes the main interrupt controller.
296 The primary irqchip invokes the crossbar's callback which inturn allocates
297 a free irq and configures the IP. Thus the peripheral interrupts are
298 routed to one of the free irqchip interrupt lines.
301 tristate "Keystone 2 IRQ controller IP"
302 depends on ARCH_KEYSTONE
304 Support for Texas Instruments Keystone 2 IRQ controller IP which
305 is part of the Keystone 2 IPC mechanism
309 select GENERIC_IRQ_IPI
310 select IRQ_DOMAIN_HIERARCHY
315 depends on MACH_INGENIC
318 config RENESAS_H8300H_INTC
322 config RENESAS_H8S_INTC
323 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
326 Enable support for the Renesas H8/300 Interrupt Controller, as found
333 Enables the wakeup IRQs for IMX platforms with GPCv2 block
336 def_bool y if MACH_ASM9260 || ARCH_MXS
340 config MSCC_OCELOT_IRQ
343 select GENERIC_IRQ_CHIP
353 select GENERIC_MSI_IRQ_DOMAIN
362 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
363 depends on PCI && PCI_MSI
365 config PARTITION_PERCPU
369 bool "NPS400 Global Interrupt Manager (GIM)"
370 depends on ARC || (COMPILE_TEST && !64BIT)
373 Support the EZchip NPS400 global interrupt controller
378 select GENERIC_IRQ_CHIP
380 config QCOM_IRQ_COMBINER
381 bool "QCOM IRQ combiner support"
382 depends on ARCH_QCOM && ACPI
383 select IRQ_DOMAIN_HIERARCHY
385 Say yes here to add support for the IRQ combiner devices embedded
386 in Qualcomm Technologies chips.
388 config IRQ_UNIPHIER_AIDET
389 bool "UniPhier AIDET support" if COMPILE_TEST
390 depends on ARCH_UNIPHIER || COMPILE_TEST
391 default ARCH_UNIPHIER
392 select IRQ_DOMAIN_HIERARCHY
394 Support for the UniPhier AIDET (ARM Interrupt Detector).
396 config MESON_IRQ_GPIO
397 bool "Meson GPIO Interrupt Multiplexer"
398 depends on ARCH_MESON
399 select IRQ_DOMAIN_HIERARCHY
401 Support Meson SoC Family GPIO Interrupt Multiplexer
404 bool "Goldfish programmable interrupt controller"
405 depends on MIPS && (GOLDFISH || COMPILE_TEST)
408 Say yes here to enable Goldfish interrupt controller driver used
409 for Goldfish based virtual platforms.
414 select IRQ_DOMAIN_HIERARCHY
416 Power Domain Controller driver to manage and configure wakeup
417 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
420 bool "C-SKY Multi Processor Interrupt Controller"
423 Say yes here to enable C-SKY SMP interrupt controller driver used
424 for C-SKY SMP system.
425 In fact it's not mmio map in hw and it use ld/st to visit the
426 controller's register inside CPU.
429 bool "C-SKY APB Interrupt Controller"
432 Say yes here to enable C-SKY APB interrupt controller driver used
433 by C-SKY single core SOC system. It use mmio map apb-bus to visit
434 the controller's register.
437 bool "i.MX IRQSTEER support"
438 depends on ARCH_MXC || COMPILE_TEST
442 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
445 bool "Loongson-1 Interrupt Controller"
446 depends on MACH_LOONGSON32
449 select GENERIC_IRQ_CHIP
451 Support for the Loongson-1 platform Interrupt Controller.
453 config TI_SCI_INTR_IRQCHIP
455 depends on TI_SCI_PROTOCOL
456 select IRQ_DOMAIN_HIERARCHY
458 This enables the irqchip driver support for K3 Interrupt router
459 over TI System Control Interface available on some new TI's SoCs.
460 If you wish to use interrupt router irq resources managed by the
461 TI System Controller, say Y here. Otherwise, say N.
463 config TI_SCI_INTA_IRQCHIP
465 depends on TI_SCI_PROTOCOL
466 select IRQ_DOMAIN_HIERARCHY
467 select TI_SCI_INTA_MSI_DOMAIN
469 This enables the irqchip driver support for K3 Interrupt aggregator
470 over TI System Control Interface available on some new TI's SoCs.
471 If you wish to use interrupt aggregator irq resources managed by the
472 TI System Controller, say Y here. Otherwise, say N.
477 bool "SiFive Platform-Level Interrupt Controller"
480 This enables support for the PLIC chip found in SiFive (and
481 potentially other) RISC-V systems. The PLIC controls devices
482 interrupts and connects them to each core's local interrupt
483 controller. Aside from timer and software interrupts, all other
484 interrupt sources are subordinate to the PLIC.
486 If you don't know what to do here, say Y.