1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
6 #include <linux/bitfield.h>
8 #include <linux/irqchip.h>
9 #include <linux/irqchip/chained_irq.h>
10 #include <linux/irqdomain.h>
11 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
17 #define AL_FIC_CAUSE 0x00
18 #define AL_FIC_MASK 0x10
19 #define AL_FIC_CONTROL 0x28
21 #define CONTROL_TRIGGER_RISING BIT(3)
22 #define CONTROL_MASK_MSI_X BIT(5)
24 #define NR_FIC_IRQS 32
26 MODULE_AUTHOR("Talel Shenhar");
27 MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
28 MODULE_LICENSE("GPL v2");
31 AL_FIC_UNCONFIGURED = 0,
32 AL_FIC_CONFIGURED_LEVEL,
33 AL_FIC_CONFIGURED_RISING_EDGE,
38 struct irq_domain *domain;
40 unsigned int parent_irq;
41 enum al_fic_state state;
44 static void al_fic_set_trigger(struct al_fic *fic,
45 struct irq_chip_generic *gc,
46 enum al_fic_state new_state)
48 irq_flow_handler_t handler;
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL);
51 if (new_state == AL_FIC_CONFIGURED_LEVEL) {
52 handler = handle_level_irq;
53 control &= ~CONTROL_TRIGGER_RISING;
55 handler = handle_edge_irq;
56 control |= CONTROL_TRIGGER_RISING;
58 gc->chip_types->handler = handler;
59 fic->state = new_state;
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL);
63 static int al_fic_irq_set_type(struct irq_data *data, unsigned int flow_type)
65 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
66 struct al_fic *fic = gc->private;
67 enum al_fic_state new_state;
72 if (((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH) &&
73 ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)) {
74 pr_debug("fic doesn't support flow type %d\n", flow_type);
79 new_state = (flow_type & IRQ_TYPE_LEVEL_HIGH) ?
80 AL_FIC_CONFIGURED_LEVEL : AL_FIC_CONFIGURED_RISING_EDGE;
83 * A given FIC instance can be either all level or all edge triggered.
84 * This is generally fixed depending on what pieces of HW it's wired up
87 * We configure it based on the sensitivity of the first source
88 * being setup, and reject any subsequent attempt at configuring it in a
91 if (fic->state == AL_FIC_UNCONFIGURED) {
92 al_fic_set_trigger(fic, gc, new_state);
93 } else if (fic->state != new_state) {
94 pr_debug("fic %s state already configured to %d\n",
95 fic->name, fic->state);
106 static void al_fic_irq_handler(struct irq_desc *desc)
108 struct al_fic *fic = irq_desc_get_handler_data(desc);
109 struct irq_domain *domain = fic->domain;
110 struct irq_chip *irqchip = irq_desc_get_chip(desc);
111 struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
112 unsigned long pending;
116 chained_irq_enter(irqchip, desc);
118 pending = readl_relaxed(fic->base + AL_FIC_CAUSE);
119 pending &= ~gc->mask_cache;
121 for_each_set_bit(hwirq, &pending, NR_FIC_IRQS) {
122 irq = irq_find_mapping(domain, hwirq);
123 generic_handle_irq(irq);
126 chained_irq_exit(irqchip, desc);
129 static int al_fic_register(struct device_node *node,
132 struct irq_chip_generic *gc;
135 fic->domain = irq_domain_add_linear(node,
137 &irq_generic_chip_ops,
140 pr_err("fail to add irq domain\n");
144 ret = irq_alloc_domain_generic_chips(fic->domain,
148 0, 0, IRQ_GC_INIT_MASK_CACHE);
150 pr_err("fail to allocate generic chip (%d)\n", ret);
151 goto err_domain_remove;
154 gc = irq_get_domain_generic_chip(fic->domain, 0);
155 gc->reg_base = fic->base;
156 gc->chip_types->regs.mask = AL_FIC_MASK;
157 gc->chip_types->regs.ack = AL_FIC_CAUSE;
158 gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit;
159 gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit;
160 gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit;
161 gc->chip_types->chip.irq_set_type = al_fic_irq_set_type;
162 gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE;
165 irq_set_chained_handler_and_data(fic->parent_irq,
171 irq_domain_remove(fic->domain);
177 * al_fic_wire_init() - initialize and configure fic in wire mode
178 * @of_node: optional pointer to interrupt controller's device tree node.
179 * @base: mmio to fic register
180 * @name: name of the fic
181 * @parent_irq: interrupt of parent
183 * This API will configure the fic hardware to to work in wire mode.
184 * In wire mode, fic hardware is generating a wire ("wired") interrupt.
185 * Interrupt can be generated based on positive edge or level - configuration is
186 * to be determined based on connected hardware to this fic.
188 static struct al_fic *al_fic_wire_init(struct device_node *node,
191 unsigned int parent_irq)
195 u32 control = CONTROL_MASK_MSI_X;
197 fic = kzalloc(sizeof(*fic), GFP_KERNEL);
199 return ERR_PTR(-ENOMEM);
202 fic->parent_irq = parent_irq;
205 /* mask out all interrupts */
206 writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK);
208 /* clear any pending interrupt */
209 writel_relaxed(0, fic->base + AL_FIC_CAUSE);
211 writel_relaxed(control, fic->base + AL_FIC_CONTROL);
213 ret = al_fic_register(node, fic);
215 pr_err("fail to register irqchip\n");
219 pr_debug("%s initialized successfully in Legacy mode (parent-irq=%u)\n",
220 fic->name, parent_irq);
229 static int __init al_fic_init_dt(struct device_node *node,
230 struct device_node *parent)
234 unsigned int parent_irq;
238 pr_err("%s: unsupported - device require a parent\n",
243 base = of_iomap(node, 0);
245 pr_err("%s: fail to map memory\n", node->name);
249 parent_irq = irq_of_parse_and_map(node, 0);
251 pr_err("%s: fail to map irq\n", node->name);
256 fic = al_fic_wire_init(node,
261 pr_err("%s: fail to initialize irqchip (%lu)\n",
265 goto err_irq_dispose;
271 irq_dispose_mapping(parent_irq);
278 IRQCHIP_DECLARE(al_fic, "amazon,al-fic", al_fic_init_dt);