1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7038 style Level 1 interrupt controller driver
5 * Copyright (C) 2014 Broadcom Corporation
6 * Author: Kevin Cernekee
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/bitops.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/module.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_address.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/smp.h>
27 #include <linux/types.h>
28 #include <linux/irqchip.h>
29 #include <linux/irqchip/chained_irq.h>
31 #define IRQS_PER_WORD 32
32 #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
35 struct bcm7038_l1_cpu;
37 struct bcm7038_l1_chip {
40 struct irq_domain *domain;
41 struct bcm7038_l1_cpu *cpus[NR_CPUS];
42 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
45 struct bcm7038_l1_cpu {
46 void __iomem *map_base;
51 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
54 * 0x1000_1400: W0_STATUS
55 * 0x1000_1404: W1_STATUS
56 * 0x1000_1408: W0_MASK_STATUS
57 * 0x1000_140c: W1_MASK_STATUS
58 * 0x1000_1410: W0_MASK_SET
59 * 0x1000_1414: W1_MASK_SET
60 * 0x1000_1418: W0_MASK_CLEAR
61 * 0x1000_141c: W1_MASK_CLEAR
64 * 0xf03e_1500: W0_STATUS
65 * 0xf03e_1504: W1_STATUS
66 * 0xf03e_1508: W2_STATUS
67 * 0xf03e_150c: W3_STATUS
68 * 0xf03e_1510: W4_STATUS
69 * 0xf03e_1514: W0_MASK_STATUS
70 * 0xf03e_1518: W1_MASK_STATUS
74 static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
77 return (0 * intc->n_words + word) * sizeof(u32);
80 static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
83 return (1 * intc->n_words + word) * sizeof(u32);
86 static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
89 return (2 * intc->n_words + word) * sizeof(u32);
92 static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
95 return (3 * intc->n_words + word) * sizeof(u32);
98 static inline u32 l1_readl(void __iomem *reg)
100 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
101 return ioread32be(reg);
106 static inline void l1_writel(u32 val, void __iomem *reg)
108 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
109 iowrite32be(val, reg);
114 static void bcm7038_l1_irq_handle(struct irq_desc *desc)
116 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
117 struct bcm7038_l1_cpu *cpu;
118 struct irq_chip *chip = irq_desc_get_chip(desc);
122 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
127 chained_irq_enter(chip, desc);
129 for (idx = 0; idx < intc->n_words; idx++) {
130 int base = idx * IRQS_PER_WORD;
131 unsigned long pending, flags;
134 raw_spin_lock_irqsave(&intc->lock, flags);
135 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
136 ~cpu->mask_cache[idx];
137 raw_spin_unlock_irqrestore(&intc->lock, flags);
139 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
140 generic_handle_irq(irq_find_mapping(intc->domain,
145 chained_irq_exit(chip, desc);
148 static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
150 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
151 u32 word = d->hwirq / IRQS_PER_WORD;
152 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
154 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
155 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
156 reg_mask_clr(intc, word));
159 static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
161 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
162 u32 word = d->hwirq / IRQS_PER_WORD;
163 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
165 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
166 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
167 reg_mask_set(intc, word));
170 static void bcm7038_l1_unmask(struct irq_data *d)
172 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
175 raw_spin_lock_irqsave(&intc->lock, flags);
176 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
177 raw_spin_unlock_irqrestore(&intc->lock, flags);
180 static void bcm7038_l1_mask(struct irq_data *d)
182 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
185 raw_spin_lock_irqsave(&intc->lock, flags);
186 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
187 raw_spin_unlock_irqrestore(&intc->lock, flags);
190 static int bcm7038_l1_set_affinity(struct irq_data *d,
191 const struct cpumask *dest,
194 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
196 irq_hw_number_t hw = d->hwirq;
197 u32 word = hw / IRQS_PER_WORD;
198 u32 mask = BIT(hw % IRQS_PER_WORD);
199 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
202 raw_spin_lock_irqsave(&intc->lock, flags);
204 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
206 __bcm7038_l1_mask(d, intc->affinity[hw]);
207 intc->affinity[hw] = first_cpu;
209 __bcm7038_l1_unmask(d, first_cpu);
211 raw_spin_unlock_irqrestore(&intc->lock, flags);
212 irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
218 static void bcm7038_l1_cpu_offline(struct irq_data *d)
220 struct cpumask *mask = irq_data_get_affinity_mask(d);
221 int cpu = smp_processor_id();
222 cpumask_t new_affinity;
224 /* This CPU was not on the affinity mask */
225 if (!cpumask_test_cpu(cpu, mask))
228 if (cpumask_weight(mask) > 1) {
230 * Multiple CPU affinity, remove this CPU from the affinity
233 cpumask_copy(&new_affinity, mask);
234 cpumask_clear_cpu(cpu, &new_affinity);
236 /* Only CPU, put on the lowest online CPU */
237 cpumask_clear(&new_affinity);
238 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
240 irq_set_affinity_locked(d, &new_affinity, false);
244 static int __init bcm7038_l1_init_one(struct device_node *dn,
246 struct bcm7038_l1_chip *intc)
250 struct bcm7038_l1_cpu *cpu;
251 unsigned int i, n_words, parent_irq;
253 if (of_address_to_resource(dn, idx, &res))
255 sz = resource_size(&res);
256 n_words = sz / REG_BYTES_PER_IRQ_WORD;
258 if (n_words > MAX_WORDS)
260 else if (!intc->n_words)
261 intc->n_words = n_words;
262 else if (intc->n_words != n_words)
265 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
270 cpu->map_base = ioremap(res.start, sz);
274 for (i = 0; i < n_words; i++) {
275 l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
276 cpu->mask_cache[i] = 0xffffffff;
279 parent_irq = irq_of_parse_and_map(dn, idx);
281 pr_err("failed to map parent interrupt %d\n", parent_irq);
284 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
290 static struct irq_chip bcm7038_l1_irq_chip = {
291 .name = "bcm7038-l1",
292 .irq_mask = bcm7038_l1_mask,
293 .irq_unmask = bcm7038_l1_unmask,
294 .irq_set_affinity = bcm7038_l1_set_affinity,
296 .irq_cpu_offline = bcm7038_l1_cpu_offline,
300 static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
301 irq_hw_number_t hw_irq)
303 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
304 irq_set_chip_data(virq, d->host_data);
305 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
309 static const struct irq_domain_ops bcm7038_l1_domain_ops = {
310 .xlate = irq_domain_xlate_onecell,
311 .map = bcm7038_l1_map,
314 int __init bcm7038_l1_of_init(struct device_node *dn,
315 struct device_node *parent)
317 struct bcm7038_l1_chip *intc;
320 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
324 raw_spin_lock_init(&intc->lock);
325 for_each_possible_cpu(idx) {
326 ret = bcm7038_l1_init_one(dn, idx, intc);
330 pr_err("failed to remap intc L1 registers\n");
335 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
336 &bcm7038_l1_domain_ops,
343 pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
344 dn, IRQS_PER_WORD * intc->n_words);
349 for_each_possible_cpu(idx) {
350 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
354 iounmap(cpu->map_base);
363 IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);