2 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
4 * Copyright (C) 2014-2017 Broadcom
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18 #include <linux/init.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/of_platform.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
30 #include <linux/irqdomain.h>
31 #include <linux/irqchip.h>
32 #include <linux/irqchip/chained_irq.h>
34 struct brcmstb_intc_init_params {
35 irq_flow_handler_t handler;
43 /* Register offsets in the L2 latched interrupt controller */
44 static const struct brcmstb_intc_init_params l2_edge_intc_init = {
45 .handler = handle_edge_irq,
48 .cpu_mask_status = 0x0c,
50 .cpu_mask_clear = 0x14
53 /* Register offsets in the L2 level interrupt controller */
54 static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
55 .handler = handle_level_irq,
57 .cpu_clear = -1, /* Register not present */
58 .cpu_mask_status = 0x04,
60 .cpu_mask_clear = 0x0C
63 /* L2 intc private data structure */
64 struct brcmstb_l2_intc_data {
65 struct irq_domain *domain;
66 struct irq_chip_generic *gc;
70 u32 saved_mask; /* for suspend/resume */
74 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
77 * Chip has separate enable/disable registers instead of a single mask
78 * register and pending interrupt is acknowledged by setting a bit.
80 * Note: This function is generic and could easily be added to the
81 * generic irqchip implementation if there ever becomes a will to do so.
82 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
84 * e.g.: https://patchwork.kernel.org/patch/9831047/
86 static void brcmstb_l2_mask_and_ack(struct irq_data *d)
88 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
89 struct irq_chip_type *ct = irq_data_get_chip_type(d);
93 irq_reg_writel(gc, mask, ct->regs.disable);
94 *ct->mask_cache &= ~mask;
95 irq_reg_writel(gc, mask, ct->regs.ack);
99 static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
101 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
102 struct irq_chip *chip = irq_desc_get_chip(desc);
106 chained_irq_enter(chip, desc);
108 status = irq_reg_readl(b->gc, b->status_offset) &
109 ~(irq_reg_readl(b->gc, b->mask_offset));
112 raw_spin_lock(&desc->lock);
113 handle_bad_irq(desc);
114 raw_spin_unlock(&desc->lock);
119 irq = ffs(status) - 1;
120 status &= ~(1 << irq);
121 generic_handle_irq(irq_linear_revmap(b->domain, irq));
124 chained_irq_exit(chip, desc);
127 static void brcmstb_l2_intc_suspend(struct irq_data *d)
129 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
130 struct irq_chip_type *ct = irq_data_get_chip_type(d);
131 struct brcmstb_l2_intc_data *b = gc->private;
134 irq_gc_lock_irqsave(gc, flags);
135 /* Save the current mask */
136 b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
139 /* Program the wakeup mask */
140 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
141 irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
143 irq_gc_unlock_irqrestore(gc, flags);
146 static void brcmstb_l2_intc_resume(struct irq_data *d)
148 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
149 struct irq_chip_type *ct = irq_data_get_chip_type(d);
150 struct brcmstb_l2_intc_data *b = gc->private;
153 irq_gc_lock_irqsave(gc, flags);
154 if (ct->chip.irq_ack) {
155 /* Clear unmasked non-wakeup interrupts */
156 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
160 /* Restore the saved mask */
161 irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
162 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
163 irq_gc_unlock_irqrestore(gc, flags);
166 static int __init brcmstb_l2_intc_of_init(struct device_node *np,
167 struct device_node *parent,
168 const struct brcmstb_intc_init_params
171 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
172 struct brcmstb_l2_intc_data *data;
173 struct irq_chip_type *ct;
179 data = kzalloc(sizeof(*data), GFP_KERNEL);
183 base = of_iomap(np, 0);
185 pr_err("failed to remap intc L2 registers\n");
190 /* Disable all interrupts by default */
191 writel(0xffffffff, base + init_params->cpu_mask_set);
193 /* Wakeup interrupts may be retained from S5 (cold boot) */
194 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
195 if (!data->can_wake && (init_params->cpu_clear >= 0))
196 writel(0xffffffff, base + init_params->cpu_clear);
198 parent_irq = irq_of_parse_and_map(np, 0);
200 pr_err("failed to find parent interrupt\n");
205 data->domain = irq_domain_add_linear(np, 32,
206 &irq_generic_chip_ops, NULL);
212 /* MIPS chips strapped for BE will automagically configure the
213 * peripheral registers for CPU-native byte order.
216 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
217 flags |= IRQ_GC_BE_IO;
219 /* Allocate a single Generic IRQ chip for this node */
220 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
221 np->full_name, init_params->handler, clr, 0, flags);
223 pr_err("failed to allocate generic irq chip\n");
224 goto out_free_domain;
227 /* Set the IRQ chaining logic */
228 irq_set_chained_handler_and_data(parent_irq,
229 brcmstb_l2_intc_irq_handle, data);
231 data->gc = irq_get_domain_generic_chip(data->domain, 0);
232 data->gc->reg_base = base;
233 data->gc->private = data;
234 data->status_offset = init_params->cpu_status;
235 data->mask_offset = init_params->cpu_mask_status;
237 ct = data->gc->chip_types;
239 if (init_params->cpu_clear >= 0) {
240 ct->regs.ack = init_params->cpu_clear;
241 ct->chip.irq_ack = irq_gc_ack_set_bit;
242 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
244 /* No Ack - but still slightly more efficient to define this */
245 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
248 ct->chip.irq_mask = irq_gc_mask_disable_reg;
249 ct->regs.disable = init_params->cpu_mask_set;
250 ct->regs.mask = init_params->cpu_mask_status;
252 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
253 ct->regs.enable = init_params->cpu_mask_clear;
255 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
256 ct->chip.irq_resume = brcmstb_l2_intc_resume;
257 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
259 if (data->can_wake) {
260 /* This IRQ chip can wake the system, set all child interrupts
261 * in wake_enabled mask
263 data->gc->wake_enabled = 0xffffffff;
264 ct->chip.irq_set_wake = irq_gc_set_wake;
270 irq_domain_remove(data->domain);
278 static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
279 struct device_node *parent)
281 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
283 IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
285 static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
286 struct device_node *parent)
288 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
290 IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
291 brcmstb_l2_lvl_intc_of_init);