1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 #include <linux/interrupt.h>
9 #include <linux/irqchip/arm-gic.h>
11 #include "irq-gic-common.h"
13 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
15 static const struct gic_kvm_info *gic_kvm_info;
17 const struct gic_kvm_info *gic_get_kvm_info(void)
22 void gic_set_kvm_info(const struct gic_kvm_info *info)
24 BUG_ON(gic_kvm_info != NULL);
28 void gic_enable_of_quirks(const struct device_node *np,
29 const struct gic_quirk *quirks, void *data)
31 for (; quirks->desc; quirks++) {
32 if (!of_device_is_compatible(np, quirks->compatible))
34 if (quirks->init(data))
35 pr_info("GIC: enabling workaround for %s\n",
40 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
43 for (; quirks->desc; quirks++) {
44 if (quirks->iidr != (quirks->mask & iidr))
46 if (quirks->init(data))
47 pr_info("GIC: enabling workaround for %s\n",
52 int gic_configure_irq(unsigned int irq, unsigned int type,
53 void __iomem *base, void (*sync_access)(void))
55 u32 confmask = 0x2 << ((irq % 16) * 2);
56 u32 confoff = (irq / 16) * 4;
62 * Read current configuration register, and insert the config
63 * for "irq", depending on "type".
65 raw_spin_lock_irqsave(&irq_controller_lock, flags);
66 val = oldval = readl_relaxed(base + confoff);
67 if (type & IRQ_TYPE_LEVEL_MASK)
69 else if (type & IRQ_TYPE_EDGE_BOTH)
72 /* If the current configuration is the same, then we are done */
74 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
79 * Write back the new configuration, and possibly re-enable
80 * the interrupt. If we fail to write a new configuration for
81 * an SPI then WARN and return an error. If we fail to write the
82 * configuration for a PPI this is most likely because the GIC
83 * does not allow us to set the configuration or we are in a
84 * non-secure mode, and hence it may not be catastrophic.
86 writel_relaxed(val, base + confoff);
87 if (readl_relaxed(base + confoff) != val)
90 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
98 void gic_dist_config(void __iomem *base, int gic_irqs,
99 void (*sync_access)(void))
104 * Set all global interrupts to be level triggered, active low.
106 for (i = 32; i < gic_irqs; i += 16)
107 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
108 base + GIC_DIST_CONFIG + i / 4);
111 * Set priority on all global interrupts.
113 for (i = 32; i < gic_irqs; i += 4)
114 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
117 * Deactivate and disable all SPIs. Leave the PPI and SGIs
118 * alone as they are in the redistributor registers on GICv3.
120 for (i = 32; i < gic_irqs; i += 32) {
121 writel_relaxed(GICD_INT_EN_CLR_X32,
122 base + GIC_DIST_ACTIVE_CLEAR + i / 8);
123 writel_relaxed(GICD_INT_EN_CLR_X32,
124 base + GIC_DIST_ENABLE_CLEAR + i / 8);
131 void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void))
136 * Deal with the banked PPI and SGI interrupts - disable all
137 * private interrupts. Make sure everything is deactivated.
139 for (i = 0; i < nr; i += 32) {
140 writel_relaxed(GICD_INT_EN_CLR_X32,
141 base + GIC_DIST_ACTIVE_CLEAR + i / 8);
142 writel_relaxed(GICD_INT_EN_CLR_X32,
143 base + GIC_DIST_ENABLE_CLEAR + i / 8);
147 * Set priority on PPI and SGI interrupts
149 for (i = 0; i < nr; i += 4)
150 writel_relaxed(GICD_INT_DEF_PRI_X4,
151 base + GIC_DIST_PRI + i * 4 / 4);
153 /* Ensure all SGI interrupts are now enabled */
154 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);