1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <linux/acpi.h>
8 #include <linux/acpi_iort.h>
9 #include <linux/bitmap.h>
10 #include <linux/cpu.h>
11 #include <linux/crash_dump.h>
12 #include <linux/delay.h>
13 #include <linux/dma-iommu.h>
14 #include <linux/efi.h>
15 #include <linux/interrupt.h>
16 #include <linux/irqdomain.h>
17 #include <linux/list.h>
18 #include <linux/log2.h>
19 #include <linux/memblock.h>
21 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/percpu.h>
28 #include <linux/slab.h>
29 #include <linux/syscore_ops.h>
31 #include <linux/irqchip.h>
32 #include <linux/irqchip/arm-gic-v3.h>
33 #include <linux/irqchip/arm-gic-v4.h>
35 #include <asm/cputype.h>
36 #include <asm/exception.h>
38 #include "irq-gic-common.h"
40 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
41 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
42 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
43 #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3)
45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
46 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
48 static u32 lpi_id_bits;
51 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
52 * deal with (one configuration byte per interrupt). PENDBASE has to
53 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
55 #define LPI_NRBITS lpi_id_bits
56 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
57 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
59 #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
62 * Collection structure - just an ID, and a redistributor address to
63 * ping. We use one per CPU as a bag of interrupts assigned to this
66 struct its_collection {
72 * The ITS_BASER structure - contains memory information, cached
73 * value of BASER register configuration and ITS page size.
85 * The ITS structure - contains most of the infrastructure, with the
86 * top-level MSI domain, the command queue, the collections, and the
87 * list of devices writing to it.
89 * dev_alloc_lock has to be taken for device allocations, while the
90 * spinlock must be taken to parse data structures such as the device
95 struct mutex dev_alloc_lock;
96 struct list_head entry;
98 phys_addr_t phys_base;
99 struct its_cmd_block *cmd_base;
100 struct its_cmd_block *cmd_write;
101 struct its_baser tables[GITS_BASER_NR_REGS];
102 struct its_collection *collections;
103 struct fwnode_handle *fwnode_handle;
104 u64 (*get_msi_base)(struct its_device *its_dev);
107 struct list_head its_device_list;
109 unsigned long list_nr;
113 unsigned int msi_domain_flags;
114 u32 pre_its_base; /* for Socionext Synquacer */
116 int vlpi_redist_offset;
119 #define ITS_ITT_ALIGN SZ_256
121 /* The maximum number of VPEID bits supported by VLPI commands */
122 #define ITS_MAX_VPEID_BITS (16)
123 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
125 /* Convert page order to size in bytes */
126 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
128 struct event_lpi_map {
129 unsigned long *lpi_map;
131 irq_hw_number_t lpi_base;
133 struct mutex vlpi_lock;
135 struct its_vlpi_map *vlpi_maps;
140 * The ITS view of a device - belongs to an ITS, owns an interrupt
141 * translation table, and a list of interrupts. If it some of its
142 * LPIs are injected into a guest (GICv4), the event_map.vm field
143 * indicates which one.
146 struct list_head entry;
147 struct its_node *its;
148 struct event_lpi_map event_map;
157 struct its_device *dev;
158 struct its_vpe **vpes;
162 static LIST_HEAD(its_nodes);
163 static DEFINE_RAW_SPINLOCK(its_lock);
164 static struct rdists *gic_rdists;
165 static struct irq_domain *its_parent;
167 static unsigned long its_list_map;
168 static u16 vmovp_seq_num;
169 static DEFINE_RAW_SPINLOCK(vmovp_lock);
171 static DEFINE_IDA(its_vpeid_ida);
173 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
174 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
175 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
176 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
178 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
181 struct its_node *its = its_dev->its;
183 return its->collections + its_dev->event_map.col_map[event];
186 static struct its_collection *valid_col(struct its_collection *col)
188 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(0, 15)))
194 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
196 if (valid_col(its->collections + vpe->col_idx))
203 * ITS command descriptors - parameters to be encoded in a command
206 struct its_cmd_desc {
209 struct its_device *dev;
214 struct its_device *dev;
219 struct its_device *dev;
224 struct its_device *dev;
229 struct its_collection *col;
234 struct its_device *dev;
240 struct its_device *dev;
241 struct its_collection *col;
246 struct its_device *dev;
251 struct its_collection *col;
260 struct its_collection *col;
266 struct its_device *dev;
274 struct its_device *dev;
281 struct its_collection *col;
289 * The ITS command block, which is what the ITS actually parses.
291 struct its_cmd_block {
295 #define ITS_CMD_QUEUE_SZ SZ_64K
296 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
298 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
299 struct its_cmd_block *,
300 struct its_cmd_desc *);
302 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
303 struct its_cmd_block *,
304 struct its_cmd_desc *);
306 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
308 u64 mask = GENMASK_ULL(h, l);
310 *raw_cmd |= (val << l) & mask;
313 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
315 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
318 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
320 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
323 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
325 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
328 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
330 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
333 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
335 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
338 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
340 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
343 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
345 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
348 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
350 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
353 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
355 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
358 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
360 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
363 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
365 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
368 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
370 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
373 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
375 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
378 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
380 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
383 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
385 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
388 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
390 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
393 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
395 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
398 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
400 /* Let's fixup BE commands */
401 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
402 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
403 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
404 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
407 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
408 struct its_cmd_block *cmd,
409 struct its_cmd_desc *desc)
411 unsigned long itt_addr;
412 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
414 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
415 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
417 its_encode_cmd(cmd, GITS_CMD_MAPD);
418 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
419 its_encode_size(cmd, size - 1);
420 its_encode_itt(cmd, itt_addr);
421 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
428 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
429 struct its_cmd_block *cmd,
430 struct its_cmd_desc *desc)
432 its_encode_cmd(cmd, GITS_CMD_MAPC);
433 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
434 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
435 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
439 return desc->its_mapc_cmd.col;
442 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
443 struct its_cmd_block *cmd,
444 struct its_cmd_desc *desc)
446 struct its_collection *col;
448 col = dev_event_to_col(desc->its_mapti_cmd.dev,
449 desc->its_mapti_cmd.event_id);
451 its_encode_cmd(cmd, GITS_CMD_MAPTI);
452 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
453 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
454 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
455 its_encode_collection(cmd, col->col_id);
459 return valid_col(col);
462 static struct its_collection *its_build_movi_cmd(struct its_node *its,
463 struct its_cmd_block *cmd,
464 struct its_cmd_desc *desc)
466 struct its_collection *col;
468 col = dev_event_to_col(desc->its_movi_cmd.dev,
469 desc->its_movi_cmd.event_id);
471 its_encode_cmd(cmd, GITS_CMD_MOVI);
472 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
473 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
474 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
478 return valid_col(col);
481 static struct its_collection *its_build_discard_cmd(struct its_node *its,
482 struct its_cmd_block *cmd,
483 struct its_cmd_desc *desc)
485 struct its_collection *col;
487 col = dev_event_to_col(desc->its_discard_cmd.dev,
488 desc->its_discard_cmd.event_id);
490 its_encode_cmd(cmd, GITS_CMD_DISCARD);
491 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
492 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
496 return valid_col(col);
499 static struct its_collection *its_build_inv_cmd(struct its_node *its,
500 struct its_cmd_block *cmd,
501 struct its_cmd_desc *desc)
503 struct its_collection *col;
505 col = dev_event_to_col(desc->its_inv_cmd.dev,
506 desc->its_inv_cmd.event_id);
508 its_encode_cmd(cmd, GITS_CMD_INV);
509 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
510 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
514 return valid_col(col);
517 static struct its_collection *its_build_int_cmd(struct its_node *its,
518 struct its_cmd_block *cmd,
519 struct its_cmd_desc *desc)
521 struct its_collection *col;
523 col = dev_event_to_col(desc->its_int_cmd.dev,
524 desc->its_int_cmd.event_id);
526 its_encode_cmd(cmd, GITS_CMD_INT);
527 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
528 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
532 return valid_col(col);
535 static struct its_collection *its_build_clear_cmd(struct its_node *its,
536 struct its_cmd_block *cmd,
537 struct its_cmd_desc *desc)
539 struct its_collection *col;
541 col = dev_event_to_col(desc->its_clear_cmd.dev,
542 desc->its_clear_cmd.event_id);
544 its_encode_cmd(cmd, GITS_CMD_CLEAR);
545 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
546 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
550 return valid_col(col);
553 static struct its_collection *its_build_invall_cmd(struct its_node *its,
554 struct its_cmd_block *cmd,
555 struct its_cmd_desc *desc)
557 its_encode_cmd(cmd, GITS_CMD_INVALL);
558 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
565 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
566 struct its_cmd_block *cmd,
567 struct its_cmd_desc *desc)
569 its_encode_cmd(cmd, GITS_CMD_VINVALL);
570 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
574 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
577 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
578 struct its_cmd_block *cmd,
579 struct its_cmd_desc *desc)
581 unsigned long vpt_addr;
584 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
585 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
587 its_encode_cmd(cmd, GITS_CMD_VMAPP);
588 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
589 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
590 its_encode_target(cmd, target);
591 its_encode_vpt_addr(cmd, vpt_addr);
592 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
596 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
599 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
600 struct its_cmd_block *cmd,
601 struct its_cmd_desc *desc)
605 if (desc->its_vmapti_cmd.db_enabled)
606 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
610 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
611 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
612 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
613 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
614 its_encode_db_phys_id(cmd, db);
615 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
619 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
622 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
623 struct its_cmd_block *cmd,
624 struct its_cmd_desc *desc)
628 if (desc->its_vmovi_cmd.db_enabled)
629 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
633 its_encode_cmd(cmd, GITS_CMD_VMOVI);
634 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
635 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
636 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
637 its_encode_db_phys_id(cmd, db);
638 its_encode_db_valid(cmd, true);
642 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
645 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
646 struct its_cmd_block *cmd,
647 struct its_cmd_desc *desc)
651 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
652 its_encode_cmd(cmd, GITS_CMD_VMOVP);
653 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
654 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
655 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
656 its_encode_target(cmd, target);
660 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
663 static u64 its_cmd_ptr_to_offset(struct its_node *its,
664 struct its_cmd_block *ptr)
666 return (ptr - its->cmd_base) * sizeof(*ptr);
669 static int its_queue_full(struct its_node *its)
674 widx = its->cmd_write - its->cmd_base;
675 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
677 /* This is incredibly unlikely to happen, unless the ITS locks up. */
678 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
684 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
686 struct its_cmd_block *cmd;
687 u32 count = 1000000; /* 1s! */
689 while (its_queue_full(its)) {
692 pr_err_ratelimited("ITS queue not draining\n");
699 cmd = its->cmd_write++;
701 /* Handle queue wrapping */
702 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
703 its->cmd_write = its->cmd_base;
714 static struct its_cmd_block *its_post_commands(struct its_node *its)
716 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
718 writel_relaxed(wr, its->base + GITS_CWRITER);
720 return its->cmd_write;
723 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
726 * Make sure the commands written to memory are observable by
729 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
730 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
735 static int its_wait_for_range_completion(struct its_node *its,
736 struct its_cmd_block *from,
737 struct its_cmd_block *to)
739 u64 rd_idx, from_idx, to_idx;
740 u32 count = 1000000; /* 1s! */
742 from_idx = its_cmd_ptr_to_offset(its, from);
743 to_idx = its_cmd_ptr_to_offset(its, to);
746 rd_idx = readl_relaxed(its->base + GITS_CREADR);
749 if (from_idx < to_idx && rd_idx >= to_idx)
753 if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx)
758 pr_err_ratelimited("ITS queue timeout (%llu %llu %llu)\n",
759 from_idx, to_idx, rd_idx);
769 /* Warning, macro hell follows */
770 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
771 void name(struct its_node *its, \
773 struct its_cmd_desc *desc) \
775 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
776 synctype *sync_obj; \
777 unsigned long flags; \
779 raw_spin_lock_irqsave(&its->lock, flags); \
781 cmd = its_allocate_entry(its); \
782 if (!cmd) { /* We're soooooo screewed... */ \
783 raw_spin_unlock_irqrestore(&its->lock, flags); \
786 sync_obj = builder(its, cmd, desc); \
787 its_flush_cmd(its, cmd); \
790 sync_cmd = its_allocate_entry(its); \
794 buildfn(its, sync_cmd, sync_obj); \
795 its_flush_cmd(its, sync_cmd); \
799 next_cmd = its_post_commands(its); \
800 raw_spin_unlock_irqrestore(&its->lock, flags); \
802 if (its_wait_for_range_completion(its, cmd, next_cmd)) \
803 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
806 static void its_build_sync_cmd(struct its_node *its,
807 struct its_cmd_block *sync_cmd,
808 struct its_collection *sync_col)
810 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
811 its_encode_target(sync_cmd, sync_col->target_address);
813 its_fixup_cmd(sync_cmd);
816 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
817 struct its_collection, its_build_sync_cmd)
819 static void its_build_vsync_cmd(struct its_node *its,
820 struct its_cmd_block *sync_cmd,
821 struct its_vpe *sync_vpe)
823 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
824 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
826 its_fixup_cmd(sync_cmd);
829 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
830 struct its_vpe, its_build_vsync_cmd)
832 static void its_send_int(struct its_device *dev, u32 event_id)
834 struct its_cmd_desc desc;
836 desc.its_int_cmd.dev = dev;
837 desc.its_int_cmd.event_id = event_id;
839 its_send_single_command(dev->its, its_build_int_cmd, &desc);
842 static void its_send_clear(struct its_device *dev, u32 event_id)
844 struct its_cmd_desc desc;
846 desc.its_clear_cmd.dev = dev;
847 desc.its_clear_cmd.event_id = event_id;
849 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
852 static void its_send_inv(struct its_device *dev, u32 event_id)
854 struct its_cmd_desc desc;
856 desc.its_inv_cmd.dev = dev;
857 desc.its_inv_cmd.event_id = event_id;
859 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
862 static void its_send_mapd(struct its_device *dev, int valid)
864 struct its_cmd_desc desc;
866 desc.its_mapd_cmd.dev = dev;
867 desc.its_mapd_cmd.valid = !!valid;
869 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
872 static void its_send_mapc(struct its_node *its, struct its_collection *col,
875 struct its_cmd_desc desc;
877 desc.its_mapc_cmd.col = col;
878 desc.its_mapc_cmd.valid = !!valid;
880 its_send_single_command(its, its_build_mapc_cmd, &desc);
883 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
885 struct its_cmd_desc desc;
887 desc.its_mapti_cmd.dev = dev;
888 desc.its_mapti_cmd.phys_id = irq_id;
889 desc.its_mapti_cmd.event_id = id;
891 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
894 static void its_send_movi(struct its_device *dev,
895 struct its_collection *col, u32 id)
897 struct its_cmd_desc desc;
899 desc.its_movi_cmd.dev = dev;
900 desc.its_movi_cmd.col = col;
901 desc.its_movi_cmd.event_id = id;
903 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
906 static void its_send_discard(struct its_device *dev, u32 id)
908 struct its_cmd_desc desc;
910 desc.its_discard_cmd.dev = dev;
911 desc.its_discard_cmd.event_id = id;
913 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
916 static void its_send_invall(struct its_node *its, struct its_collection *col)
918 struct its_cmd_desc desc;
920 desc.its_invall_cmd.col = col;
922 its_send_single_command(its, its_build_invall_cmd, &desc);
925 static void its_send_vmapti(struct its_device *dev, u32 id)
927 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
928 struct its_cmd_desc desc;
930 desc.its_vmapti_cmd.vpe = map->vpe;
931 desc.its_vmapti_cmd.dev = dev;
932 desc.its_vmapti_cmd.virt_id = map->vintid;
933 desc.its_vmapti_cmd.event_id = id;
934 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
936 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
939 static void its_send_vmovi(struct its_device *dev, u32 id)
941 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
942 struct its_cmd_desc desc;
944 desc.its_vmovi_cmd.vpe = map->vpe;
945 desc.its_vmovi_cmd.dev = dev;
946 desc.its_vmovi_cmd.event_id = id;
947 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
949 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
952 static void its_send_vmapp(struct its_node *its,
953 struct its_vpe *vpe, bool valid)
955 struct its_cmd_desc desc;
957 desc.its_vmapp_cmd.vpe = vpe;
958 desc.its_vmapp_cmd.valid = valid;
959 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
961 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
964 static void its_send_vmovp(struct its_vpe *vpe)
966 struct its_cmd_desc desc;
967 struct its_node *its;
969 int col_id = vpe->col_idx;
971 desc.its_vmovp_cmd.vpe = vpe;
972 desc.its_vmovp_cmd.its_list = (u16)its_list_map;
975 its = list_first_entry(&its_nodes, struct its_node, entry);
976 desc.its_vmovp_cmd.seq_num = 0;
977 desc.its_vmovp_cmd.col = &its->collections[col_id];
978 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
983 * Yet another marvel of the architecture. If using the
984 * its_list "feature", we need to make sure that all ITSs
985 * receive all VMOVP commands in the same order. The only way
986 * to guarantee this is to make vmovp a serialization point.
990 raw_spin_lock_irqsave(&vmovp_lock, flags);
992 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
995 list_for_each_entry(its, &its_nodes, entry) {
999 if (!vpe->its_vm->vlpi_count[its->list_nr])
1002 desc.its_vmovp_cmd.col = &its->collections[col_id];
1003 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1006 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1009 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1011 struct its_cmd_desc desc;
1013 desc.its_vinvall_cmd.vpe = vpe;
1014 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1018 * irqchip functions - assumes MSI, mostly.
1021 static inline u32 its_get_event_id(struct irq_data *d)
1023 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1024 return d->hwirq - its_dev->event_map.lpi_base;
1027 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1029 irq_hw_number_t hwirq;
1033 if (irqd_is_forwarded_to_vcpu(d)) {
1034 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1035 u32 event = its_get_event_id(d);
1036 struct its_vlpi_map *map;
1038 va = page_address(its_dev->event_map.vm->vprop_page);
1039 map = &its_dev->event_map.vlpi_maps[event];
1040 hwirq = map->vintid;
1042 /* Remember the updated property */
1043 map->properties &= ~clr;
1044 map->properties |= set | LPI_PROP_GROUP1;
1046 va = gic_rdists->prop_table_va;
1050 cfg = va + hwirq - 8192;
1052 *cfg |= set | LPI_PROP_GROUP1;
1055 * Make the above write visible to the redistributors.
1056 * And yes, we're flushing exactly: One. Single. Byte.
1059 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1060 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1065 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1067 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1069 lpi_write_config(d, clr, set);
1070 its_send_inv(its_dev, its_get_event_id(d));
1073 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1075 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1076 u32 event = its_get_event_id(d);
1078 if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1081 its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1084 * More fun with the architecture:
1086 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1087 * value or to 1023, depending on the enable bit. But that
1088 * would be issueing a mapping for an /existing/ DevID+EventID
1089 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1090 * to the /same/ vPE, using this opportunity to adjust the
1091 * doorbell. Mouahahahaha. We loves it, Precious.
1093 its_send_vmovi(its_dev, event);
1096 static void its_mask_irq(struct irq_data *d)
1098 if (irqd_is_forwarded_to_vcpu(d))
1099 its_vlpi_set_doorbell(d, false);
1101 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1104 static void its_unmask_irq(struct irq_data *d)
1106 if (irqd_is_forwarded_to_vcpu(d))
1107 its_vlpi_set_doorbell(d, true);
1109 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1112 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1116 const struct cpumask *cpu_mask = cpu_online_mask;
1117 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1118 struct its_collection *target_col;
1119 u32 id = its_get_event_id(d);
1121 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1122 if (irqd_is_forwarded_to_vcpu(d))
1125 /* lpi cannot be routed to a redistributor that is on a foreign node */
1126 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1127 if (its_dev->its->numa_node >= 0) {
1128 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1129 if (!cpumask_intersects(mask_val, cpu_mask))
1134 cpu = cpumask_any_and(mask_val, cpu_mask);
1136 if (cpu >= nr_cpu_ids)
1139 /* don't set the affinity when the target cpu is same as current one */
1140 if (cpu != its_dev->event_map.col_map[id]) {
1141 target_col = &its_dev->its->collections[cpu];
1142 its_send_movi(its_dev, target_col, id);
1143 its_dev->event_map.col_map[id] = cpu;
1144 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1147 return IRQ_SET_MASK_OK_DONE;
1150 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1152 struct its_node *its = its_dev->its;
1154 return its->phys_base + GITS_TRANSLATER;
1157 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1159 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1160 struct its_node *its;
1164 addr = its->get_msi_base(its_dev);
1166 msg->address_lo = lower_32_bits(addr);
1167 msg->address_hi = upper_32_bits(addr);
1168 msg->data = its_get_event_id(d);
1170 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1173 static int its_irq_set_irqchip_state(struct irq_data *d,
1174 enum irqchip_irq_state which,
1177 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1178 u32 event = its_get_event_id(d);
1180 if (which != IRQCHIP_STATE_PENDING)
1184 its_send_int(its_dev, event);
1186 its_send_clear(its_dev, event);
1191 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1193 unsigned long flags;
1195 /* Not using the ITS list? Everything is always mapped. */
1199 raw_spin_lock_irqsave(&vmovp_lock, flags);
1202 * If the VM wasn't mapped yet, iterate over the vpes and get
1205 vm->vlpi_count[its->list_nr]++;
1207 if (vm->vlpi_count[its->list_nr] == 1) {
1210 for (i = 0; i < vm->nr_vpes; i++) {
1211 struct its_vpe *vpe = vm->vpes[i];
1212 struct irq_data *d = irq_get_irq_data(vpe->irq);
1214 /* Map the VPE to the first possible CPU */
1215 vpe->col_idx = cpumask_first(cpu_online_mask);
1216 its_send_vmapp(its, vpe, true);
1217 its_send_vinvall(its, vpe);
1218 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1222 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1225 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1227 unsigned long flags;
1229 /* Not using the ITS list? Everything is always mapped. */
1233 raw_spin_lock_irqsave(&vmovp_lock, flags);
1235 if (!--vm->vlpi_count[its->list_nr]) {
1238 for (i = 0; i < vm->nr_vpes; i++)
1239 its_send_vmapp(its, vm->vpes[i], false);
1242 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1245 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1247 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1248 u32 event = its_get_event_id(d);
1254 mutex_lock(&its_dev->event_map.vlpi_lock);
1256 if (!its_dev->event_map.vm) {
1257 struct its_vlpi_map *maps;
1259 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1266 its_dev->event_map.vm = info->map->vm;
1267 its_dev->event_map.vlpi_maps = maps;
1268 } else if (its_dev->event_map.vm != info->map->vm) {
1273 /* Get our private copy of the mapping information */
1274 its_dev->event_map.vlpi_maps[event] = *info->map;
1276 if (irqd_is_forwarded_to_vcpu(d)) {
1277 /* Already mapped, move it around */
1278 its_send_vmovi(its_dev, event);
1280 /* Ensure all the VPEs are mapped on this ITS */
1281 its_map_vm(its_dev->its, info->map->vm);
1284 * Flag the interrupt as forwarded so that we can
1285 * start poking the virtual property table.
1287 irqd_set_forwarded_to_vcpu(d);
1289 /* Write out the property to the prop table */
1290 lpi_write_config(d, 0xff, info->map->properties);
1292 /* Drop the physical mapping */
1293 its_send_discard(its_dev, event);
1295 /* and install the virtual one */
1296 its_send_vmapti(its_dev, event);
1298 /* Increment the number of VLPIs */
1299 its_dev->event_map.nr_vlpis++;
1303 mutex_unlock(&its_dev->event_map.vlpi_lock);
1307 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1309 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1310 u32 event = its_get_event_id(d);
1313 mutex_lock(&its_dev->event_map.vlpi_lock);
1315 if (!its_dev->event_map.vm ||
1316 !its_dev->event_map.vlpi_maps[event].vm) {
1321 /* Copy our mapping information to the incoming request */
1322 *info->map = its_dev->event_map.vlpi_maps[event];
1325 mutex_unlock(&its_dev->event_map.vlpi_lock);
1329 static int its_vlpi_unmap(struct irq_data *d)
1331 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1332 u32 event = its_get_event_id(d);
1335 mutex_lock(&its_dev->event_map.vlpi_lock);
1337 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1342 /* Drop the virtual mapping */
1343 its_send_discard(its_dev, event);
1345 /* and restore the physical one */
1346 irqd_clr_forwarded_to_vcpu(d);
1347 its_send_mapti(its_dev, d->hwirq, event);
1348 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1352 /* Potentially unmap the VM from this ITS */
1353 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1356 * Drop the refcount and make the device available again if
1357 * this was the last VLPI.
1359 if (!--its_dev->event_map.nr_vlpis) {
1360 its_dev->event_map.vm = NULL;
1361 kfree(its_dev->event_map.vlpi_maps);
1365 mutex_unlock(&its_dev->event_map.vlpi_lock);
1369 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1371 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1373 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1376 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1377 lpi_update_config(d, 0xff, info->config);
1379 lpi_write_config(d, 0xff, info->config);
1380 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1385 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1387 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1388 struct its_cmd_info *info = vcpu_info;
1391 if (!its_dev->its->is_v4)
1394 /* Unmap request? */
1396 return its_vlpi_unmap(d);
1398 switch (info->cmd_type) {
1400 return its_vlpi_map(d, info);
1403 return its_vlpi_get(d, info);
1405 case PROP_UPDATE_VLPI:
1406 case PROP_UPDATE_AND_INV_VLPI:
1407 return its_vlpi_prop_update(d, info);
1414 static struct irq_chip its_irq_chip = {
1416 .irq_mask = its_mask_irq,
1417 .irq_unmask = its_unmask_irq,
1418 .irq_eoi = irq_chip_eoi_parent,
1419 .irq_set_affinity = its_set_affinity,
1420 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1421 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1422 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1427 * How we allocate LPIs:
1429 * lpi_range_list contains ranges of LPIs that are to available to
1430 * allocate from. To allocate LPIs, just pick the first range that
1431 * fits the required allocation, and reduce it by the required
1432 * amount. Once empty, remove the range from the list.
1434 * To free a range of LPIs, add a free range to the list, sort it and
1435 * merge the result if the new range happens to be adjacent to an
1436 * already free block.
1438 * The consequence of the above is that allocation is cost is low, but
1439 * freeing is expensive. We assumes that freeing rarely occurs.
1441 #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1443 static DEFINE_MUTEX(lpi_range_lock);
1444 static LIST_HEAD(lpi_range_list);
1447 struct list_head entry;
1452 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1454 struct lpi_range *range;
1456 range = kmalloc(sizeof(*range), GFP_KERNEL);
1458 range->base_id = base;
1465 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1467 struct lpi_range *range, *tmp;
1470 mutex_lock(&lpi_range_lock);
1472 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1473 if (range->span >= nr_lpis) {
1474 *base = range->base_id;
1475 range->base_id += nr_lpis;
1476 range->span -= nr_lpis;
1478 if (range->span == 0) {
1479 list_del(&range->entry);
1488 mutex_unlock(&lpi_range_lock);
1490 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1494 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
1496 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
1498 if (a->base_id + a->span != b->base_id)
1500 b->base_id = a->base_id;
1502 list_del(&a->entry);
1506 static int free_lpi_range(u32 base, u32 nr_lpis)
1508 struct lpi_range *new, *old;
1510 new = mk_lpi_range(base, nr_lpis);
1514 mutex_lock(&lpi_range_lock);
1516 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
1517 if (old->base_id < base)
1521 * old is the last element with ->base_id smaller than base,
1522 * so new goes right after it. If there are no elements with
1523 * ->base_id smaller than base, &old->entry ends up pointing
1524 * at the head of the list, and inserting new it the start of
1525 * the list is the right thing to do in that case as well.
1527 list_add(&new->entry, &old->entry);
1529 * Now check if we can merge with the preceding and/or
1532 merge_lpi_ranges(old, new);
1533 merge_lpi_ranges(new, list_next_entry(new, entry));
1535 mutex_unlock(&lpi_range_lock);
1539 static int __init its_lpi_init(u32 id_bits)
1541 u32 lpis = (1UL << id_bits) - 8192;
1545 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1547 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1549 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1554 * Initializing the allocator is just the same as freeing the
1555 * full range of LPIs.
1557 err = free_lpi_range(8192, lpis);
1558 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1562 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1564 unsigned long *bitmap = NULL;
1568 err = alloc_lpi_range(nr_irqs, base);
1573 } while (nr_irqs > 0);
1581 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1589 *base = *nr_ids = 0;
1594 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1596 WARN_ON(free_lpi_range(base, nr_ids));
1600 static void gic_reset_prop_table(void *va)
1602 /* Priority 0xa0, Group-1, disabled */
1603 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
1605 /* Make sure the GIC will observe the written configuration */
1606 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
1609 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1611 struct page *prop_page;
1613 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1617 gic_reset_prop_table(page_address(prop_page));
1622 static void its_free_prop_table(struct page *prop_page)
1624 free_pages((unsigned long)page_address(prop_page),
1625 get_order(LPI_PROPBASE_SZ));
1628 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
1630 phys_addr_t start, end, addr_end;
1634 * We don't bother checking for a kdump kernel as by
1635 * construction, the LPI tables are out of this kernel's
1638 if (is_kdump_kernel())
1641 addr_end = addr + size - 1;
1643 for_each_reserved_mem_region(i, &start, &end) {
1644 if (addr >= start && addr_end <= end)
1648 /* Not found, not a good sign... */
1649 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
1651 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
1655 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
1657 if (efi_enabled(EFI_CONFIG_TABLES))
1658 return efi_mem_reserve_persistent(addr, size);
1663 static int __init its_setup_lpi_prop_table(void)
1665 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
1668 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
1669 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
1671 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
1672 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
1675 gic_reset_prop_table(gic_rdists->prop_table_va);
1679 lpi_id_bits = min_t(u32,
1680 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1681 ITS_MAX_LPI_NRBITS);
1682 page = its_allocate_prop_table(GFP_NOWAIT);
1684 pr_err("Failed to allocate PROPBASE\n");
1688 gic_rdists->prop_table_pa = page_to_phys(page);
1689 gic_rdists->prop_table_va = page_address(page);
1690 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
1694 pr_info("GICv3: using LPI property table @%pa\n",
1695 &gic_rdists->prop_table_pa);
1697 return its_lpi_init(lpi_id_bits);
1700 static const char *its_base_type_string[] = {
1701 [GITS_BASER_TYPE_DEVICE] = "Devices",
1702 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
1703 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
1704 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
1705 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
1706 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
1707 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
1710 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1712 u32 idx = baser - its->tables;
1714 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1717 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1720 u32 idx = baser - its->tables;
1722 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1723 baser->val = its_read_baser(its, baser);
1726 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1727 u64 cache, u64 shr, u32 psz, u32 order,
1730 u64 val = its_read_baser(its, baser);
1731 u64 esz = GITS_BASER_ENTRY_SIZE(val);
1732 u64 type = GITS_BASER_TYPE(val);
1733 u64 baser_phys, tmp;
1739 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1740 if (alloc_pages > GITS_BASER_PAGES_MAX) {
1741 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1742 &its->phys_base, its_base_type_string[type],
1743 alloc_pages, GITS_BASER_PAGES_MAX);
1744 alloc_pages = GITS_BASER_PAGES_MAX;
1745 order = get_order(GITS_BASER_PAGES_MAX * psz);
1748 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
1752 base = (void *)page_address(page);
1753 baser_phys = virt_to_phys(base);
1755 /* Check if the physical address of the memory is above 48bits */
1756 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1758 /* 52bit PA is supported only when PageSize=64K */
1759 if (psz != SZ_64K) {
1760 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1761 free_pages((unsigned long)base, order);
1765 /* Convert 52bit PA to 48bit field */
1766 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1771 (type << GITS_BASER_TYPE_SHIFT) |
1772 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
1773 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
1778 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
1782 val |= GITS_BASER_PAGE_SIZE_4K;
1785 val |= GITS_BASER_PAGE_SIZE_16K;
1788 val |= GITS_BASER_PAGE_SIZE_64K;
1792 its_write_baser(its, baser, val);
1795 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1797 * Shareability didn't stick. Just use
1798 * whatever the read reported, which is likely
1799 * to be the only thing this redistributor
1800 * supports. If that's zero, make it
1801 * non-cacheable as well.
1803 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1805 cache = GITS_BASER_nC;
1806 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1811 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1813 * Page size didn't stick. Let's try a smaller
1814 * size and retry. If we reach 4K, then
1815 * something is horribly wrong...
1817 free_pages((unsigned long)base, order);
1823 goto retry_alloc_baser;
1826 goto retry_alloc_baser;
1831 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1832 &its->phys_base, its_base_type_string[type],
1834 free_pages((unsigned long)base, order);
1838 baser->order = order;
1841 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1843 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1844 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1845 its_base_type_string[type],
1846 (unsigned long)virt_to_phys(base),
1847 indirect ? "indirect" : "flat", (int)esz,
1848 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1853 static bool its_parse_indirect_baser(struct its_node *its,
1854 struct its_baser *baser,
1855 u32 psz, u32 *order, u32 ids)
1857 u64 tmp = its_read_baser(its, baser);
1858 u64 type = GITS_BASER_TYPE(tmp);
1859 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1860 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1861 u32 new_order = *order;
1862 bool indirect = false;
1864 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1865 if ((esz << ids) > (psz * 2)) {
1867 * Find out whether hw supports a single or two-level table by
1868 * table by reading bit at offset '62' after writing '1' to it.
1870 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1871 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1875 * The size of the lvl2 table is equal to ITS page size
1876 * which is 'psz'. For computing lvl1 table size,
1877 * subtract ID bits that sparse lvl2 table from 'ids'
1878 * which is reported by ITS hardware times lvl1 table
1881 ids -= ilog2(psz / (int)esz);
1882 esz = GITS_LVL1_ENTRY_SIZE;
1887 * Allocate as many entries as required to fit the
1888 * range of device IDs that the ITS can grok... The ID
1889 * space being incredibly sparse, this results in a
1890 * massive waste of memory if two-level device table
1891 * feature is not supported by hardware.
1893 new_order = max_t(u32, get_order(esz << ids), new_order);
1894 if (new_order >= MAX_ORDER) {
1895 new_order = MAX_ORDER - 1;
1896 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1897 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1898 &its->phys_base, its_base_type_string[type],
1899 its->device_ids, ids);
1907 static void its_free_tables(struct its_node *its)
1911 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1912 if (its->tables[i].base) {
1913 free_pages((unsigned long)its->tables[i].base,
1914 its->tables[i].order);
1915 its->tables[i].base = NULL;
1920 static int its_alloc_tables(struct its_node *its)
1922 u64 shr = GITS_BASER_InnerShareable;
1923 u64 cache = GITS_BASER_RaWaWb;
1927 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1928 /* erratum 24313: ignore memory access type */
1929 cache = GITS_BASER_nCnB;
1931 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1932 struct its_baser *baser = its->tables + i;
1933 u64 val = its_read_baser(its, baser);
1934 u64 type = GITS_BASER_TYPE(val);
1935 u32 order = get_order(psz);
1936 bool indirect = false;
1939 case GITS_BASER_TYPE_NONE:
1942 case GITS_BASER_TYPE_DEVICE:
1943 indirect = its_parse_indirect_baser(its, baser,
1948 case GITS_BASER_TYPE_VCPU:
1949 indirect = its_parse_indirect_baser(its, baser,
1951 ITS_MAX_VPEID_BITS);
1955 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1957 its_free_tables(its);
1961 /* Update settings which will be used for next BASERn */
1963 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1964 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1970 static int its_alloc_collections(struct its_node *its)
1974 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
1976 if (!its->collections)
1979 for (i = 0; i < nr_cpu_ids; i++)
1980 its->collections[i].target_address = ~0ULL;
1985 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
1987 struct page *pend_page;
1989 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
1990 get_order(LPI_PENDBASE_SZ));
1994 /* Make sure the GIC will observe the zero-ed page */
1995 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2000 static void its_free_pending_table(struct page *pt)
2002 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2006 * Booting with kdump and LPIs enabled is generally fine. Any other
2007 * case is wrong in the absence of firmware/EFI support.
2009 static bool enabled_lpis_allowed(void)
2014 /* Check whether the property table is in a reserved region */
2015 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2016 addr = val & GENMASK_ULL(51, 12);
2018 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2021 static int __init allocate_lpi_tables(void)
2027 * If LPIs are enabled while we run this from the boot CPU,
2028 * flag the RD tables as pre-allocated if the stars do align.
2030 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2031 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2032 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2033 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2034 pr_info("GICv3: Using preallocated redistributor tables\n");
2037 err = its_setup_lpi_prop_table();
2042 * We allocate all the pending tables anyway, as we may have a
2043 * mix of RDs that have had LPIs enabled, and some that
2044 * don't. We'll free the unused ones as each CPU comes online.
2046 for_each_possible_cpu(cpu) {
2047 struct page *pend_page;
2049 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2051 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2055 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2061 static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
2063 u32 count = 1000000; /* 1s! */
2067 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2068 val &= ~GICR_VPENDBASER_Valid;
2069 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2072 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2073 clean = !(val & GICR_VPENDBASER_Dirty);
2079 } while (!clean && count);
2084 static void its_cpu_init_lpis(void)
2086 void __iomem *rbase = gic_data_rdist_rd_base();
2087 struct page *pend_page;
2091 if (gic_data_rdist()->lpi_enabled)
2094 val = readl_relaxed(rbase + GICR_CTLR);
2095 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
2096 (val & GICR_CTLR_ENABLE_LPIS)) {
2098 * Check that we get the same property table on all
2099 * RDs. If we don't, this is hopeless.
2101 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
2102 paddr &= GENMASK_ULL(51, 12);
2103 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
2104 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2106 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2107 paddr &= GENMASK_ULL(51, 16);
2109 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
2110 its_free_pending_table(gic_data_rdist()->pend_page);
2111 gic_data_rdist()->pend_page = NULL;
2116 pend_page = gic_data_rdist()->pend_page;
2117 paddr = page_to_phys(pend_page);
2118 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
2121 val = (gic_rdists->prop_table_pa |
2122 GICR_PROPBASER_InnerShareable |
2123 GICR_PROPBASER_RaWaWb |
2124 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2126 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2127 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2129 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2130 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2132 * The HW reports non-shareable, we must
2133 * remove the cacheability attributes as
2136 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2137 GICR_PROPBASER_CACHEABILITY_MASK);
2138 val |= GICR_PROPBASER_nC;
2139 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2141 pr_info_once("GIC: using cache flushing for LPI property table\n");
2142 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2146 val = (page_to_phys(pend_page) |
2147 GICR_PENDBASER_InnerShareable |
2148 GICR_PENDBASER_RaWaWb);
2150 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2151 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2153 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2155 * The HW reports non-shareable, we must remove the
2156 * cacheability attributes as well.
2158 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2159 GICR_PENDBASER_CACHEABILITY_MASK);
2160 val |= GICR_PENDBASER_nC;
2161 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2165 val = readl_relaxed(rbase + GICR_CTLR);
2166 val |= GICR_CTLR_ENABLE_LPIS;
2167 writel_relaxed(val, rbase + GICR_CTLR);
2169 if (gic_rdists->has_vlpis) {
2170 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2173 * It's possible for CPU to receive VLPIs before it is
2174 * sheduled as a vPE, especially for the first CPU, and the
2175 * VLPI with INTID larger than 2^(IDbits+1) will be considered
2176 * as out of range and dropped by GIC.
2177 * So we initialize IDbits to known value to avoid VLPI drop.
2179 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2180 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2181 smp_processor_id(), val);
2182 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2185 * Also clear Valid bit of GICR_VPENDBASER, in case some
2186 * ancient programming gets left in and has possibility of
2187 * corrupting memory.
2189 val = its_clear_vpend_valid(vlpi_base);
2190 WARN_ON(val & GICR_VPENDBASER_Dirty);
2193 /* Make sure the GIC has seen the above */
2196 gic_data_rdist()->lpi_enabled = true;
2197 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
2199 gic_data_rdist()->pend_page ? "allocated" : "reserved",
2203 static void its_cpu_init_collection(struct its_node *its)
2205 int cpu = smp_processor_id();
2208 /* avoid cross node collections and its mapping */
2209 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2210 struct device_node *cpu_node;
2212 cpu_node = of_get_cpu_node(cpu, NULL);
2213 if (its->numa_node != NUMA_NO_NODE &&
2214 its->numa_node != of_node_to_nid(cpu_node))
2219 * We now have to bind each collection to its target
2222 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2224 * This ITS wants the physical address of the
2227 target = gic_data_rdist()->phys_base;
2229 /* This ITS wants a linear CPU number. */
2230 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2231 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2234 /* Perform collection mapping */
2235 its->collections[cpu].target_address = target;
2236 its->collections[cpu].col_id = cpu;
2238 its_send_mapc(its, &its->collections[cpu], 1);
2239 its_send_invall(its, &its->collections[cpu]);
2242 static void its_cpu_init_collections(void)
2244 struct its_node *its;
2246 raw_spin_lock(&its_lock);
2248 list_for_each_entry(its, &its_nodes, entry)
2249 its_cpu_init_collection(its);
2251 raw_spin_unlock(&its_lock);
2254 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2256 struct its_device *its_dev = NULL, *tmp;
2257 unsigned long flags;
2259 raw_spin_lock_irqsave(&its->lock, flags);
2261 list_for_each_entry(tmp, &its->its_device_list, entry) {
2262 if (tmp->device_id == dev_id) {
2268 raw_spin_unlock_irqrestore(&its->lock, flags);
2273 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2277 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2278 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2279 return &its->tables[i];
2285 static bool its_alloc_table_entry(struct its_node *its,
2286 struct its_baser *baser, u32 id)
2292 /* Don't allow device id that exceeds single, flat table limit */
2293 esz = GITS_BASER_ENTRY_SIZE(baser->val);
2294 if (!(baser->val & GITS_BASER_INDIRECT))
2295 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2297 /* Compute 1st level table index & check if that exceeds table limit */
2298 idx = id >> ilog2(baser->psz / esz);
2299 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2302 table = baser->base;
2304 /* Allocate memory for 2nd level table */
2306 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
2307 get_order(baser->psz));
2311 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2312 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2313 gic_flush_dcache_to_poc(page_address(page), baser->psz);
2315 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2317 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2318 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2319 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2321 /* Ensure updated table contents are visible to ITS hardware */
2328 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2330 struct its_baser *baser;
2332 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2334 /* Don't allow device id that exceeds ITS hardware limit */
2336 return (ilog2(dev_id) < its->device_ids);
2338 return its_alloc_table_entry(its, baser, dev_id);
2341 static bool its_alloc_vpe_table(u32 vpe_id)
2343 struct its_node *its;
2346 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2347 * could try and only do it on ITSs corresponding to devices
2348 * that have interrupts targeted at this VPE, but the
2349 * complexity becomes crazy (and you have tons of memory
2352 list_for_each_entry(its, &its_nodes, entry) {
2353 struct its_baser *baser;
2358 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2362 if (!its_alloc_table_entry(its, baser, vpe_id))
2369 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2370 int nvecs, bool alloc_lpis)
2372 struct its_device *dev;
2373 unsigned long *lpi_map = NULL;
2374 unsigned long flags;
2375 u16 *col_map = NULL;
2382 if (!its_alloc_device_table(its, dev_id))
2385 if (WARN_ON(!is_power_of_2(nvecs)))
2386 nvecs = roundup_pow_of_two(nvecs);
2388 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2390 * Even if the device wants a single LPI, the ITT must be
2391 * sized as a power of two (and you need at least one bit...).
2393 nr_ites = max(2, nvecs);
2394 sz = nr_ites * its->ite_size;
2395 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2396 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
2398 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2400 col_map = kcalloc(nr_lpis, sizeof(*col_map),
2403 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2408 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
2416 gic_flush_dcache_to_poc(itt, sz);
2420 dev->nr_ites = nr_ites;
2421 dev->event_map.lpi_map = lpi_map;
2422 dev->event_map.col_map = col_map;
2423 dev->event_map.lpi_base = lpi_base;
2424 dev->event_map.nr_lpis = nr_lpis;
2425 mutex_init(&dev->event_map.vlpi_lock);
2426 dev->device_id = dev_id;
2427 INIT_LIST_HEAD(&dev->entry);
2429 raw_spin_lock_irqsave(&its->lock, flags);
2430 list_add(&dev->entry, &its->its_device_list);
2431 raw_spin_unlock_irqrestore(&its->lock, flags);
2433 /* Map device to its ITT */
2434 its_send_mapd(dev, 1);
2439 static void its_free_device(struct its_device *its_dev)
2441 unsigned long flags;
2443 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2444 list_del(&its_dev->entry);
2445 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2446 kfree(its_dev->itt);
2450 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
2454 idx = bitmap_find_free_region(dev->event_map.lpi_map,
2455 dev->event_map.nr_lpis,
2456 get_count_order(nvecs));
2460 *hwirq = dev->event_map.lpi_base + idx;
2461 set_bit(idx, dev->event_map.lpi_map);
2466 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2467 int nvec, msi_alloc_info_t *info)
2469 struct its_node *its;
2470 struct its_device *its_dev;
2471 struct msi_domain_info *msi_info;
2476 * We ignore "dev" entirely, and rely on the dev_id that has
2477 * been passed via the scratchpad. This limits this domain's
2478 * usefulness to upper layers that definitely know that they
2479 * are built on top of the ITS.
2481 dev_id = info->scratchpad[0].ul;
2483 msi_info = msi_get_domain_info(domain);
2484 its = msi_info->data;
2486 if (!gic_rdists->has_direct_lpi &&
2488 vpe_proxy.dev->its == its &&
2489 dev_id == vpe_proxy.dev->device_id) {
2490 /* Bad luck. Get yourself a better implementation */
2491 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2496 mutex_lock(&its->dev_alloc_lock);
2497 its_dev = its_find_device(its, dev_id);
2500 * We already have seen this ID, probably through
2501 * another alias (PCI bridge of some sort). No need to
2502 * create the device.
2504 its_dev->shared = true;
2505 pr_debug("Reusing ITT for devID %x\n", dev_id);
2509 its_dev = its_create_device(its, dev_id, nvec, true);
2515 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2517 mutex_unlock(&its->dev_alloc_lock);
2518 info->scratchpad[0].ptr = its_dev;
2522 static struct msi_domain_ops its_msi_domain_ops = {
2523 .msi_prepare = its_msi_prepare,
2526 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2528 irq_hw_number_t hwirq)
2530 struct irq_fwspec fwspec;
2532 if (irq_domain_get_of_node(domain->parent)) {
2533 fwspec.fwnode = domain->parent->fwnode;
2534 fwspec.param_count = 3;
2535 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2536 fwspec.param[1] = hwirq;
2537 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2538 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2539 fwspec.fwnode = domain->parent->fwnode;
2540 fwspec.param_count = 2;
2541 fwspec.param[0] = hwirq;
2542 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2547 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2550 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2551 unsigned int nr_irqs, void *args)
2553 msi_alloc_info_t *info = args;
2554 struct its_device *its_dev = info->scratchpad[0].ptr;
2555 struct its_node *its = its_dev->its;
2556 irq_hw_number_t hwirq;
2560 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
2564 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
2568 for (i = 0; i < nr_irqs; i++) {
2569 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
2573 irq_domain_set_hwirq_and_chip(domain, virq + i,
2574 hwirq + i, &its_irq_chip, its_dev);
2575 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2576 pr_debug("ID:%d pID:%d vID:%d\n",
2577 (int)(hwirq + i - its_dev->event_map.lpi_base),
2578 (int)(hwirq + i), virq + i);
2584 static int its_irq_domain_activate(struct irq_domain *domain,
2585 struct irq_data *d, bool reserve)
2587 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2588 u32 event = its_get_event_id(d);
2589 const struct cpumask *cpu_mask = cpu_online_mask;
2592 /* get the cpu_mask of local node */
2593 if (its_dev->its->numa_node >= 0)
2594 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2596 /* Bind the LPI to the first possible CPU */
2597 cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
2598 if (cpu >= nr_cpu_ids) {
2599 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
2602 cpu = cpumask_first(cpu_online_mask);
2605 its_dev->event_map.col_map[event] = cpu;
2606 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2608 /* Map the GIC IRQ and event to the device */
2609 its_send_mapti(its_dev, d->hwirq, event);
2613 static void its_irq_domain_deactivate(struct irq_domain *domain,
2616 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2617 u32 event = its_get_event_id(d);
2619 /* Stop the delivery of interrupts */
2620 its_send_discard(its_dev, event);
2623 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2624 unsigned int nr_irqs)
2626 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2627 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2628 struct its_node *its = its_dev->its;
2631 for (i = 0; i < nr_irqs; i++) {
2632 struct irq_data *data = irq_domain_get_irq_data(domain,
2634 u32 event = its_get_event_id(data);
2636 /* Mark interrupt index as unused */
2637 clear_bit(event, its_dev->event_map.lpi_map);
2639 /* Nuke the entry in the domain */
2640 irq_domain_reset_irq_data(data);
2643 mutex_lock(&its->dev_alloc_lock);
2646 * If all interrupts have been freed, start mopping the
2647 * floor. This is conditionned on the device not being shared.
2649 if (!its_dev->shared &&
2650 bitmap_empty(its_dev->event_map.lpi_map,
2651 its_dev->event_map.nr_lpis)) {
2652 its_lpi_free(its_dev->event_map.lpi_map,
2653 its_dev->event_map.lpi_base,
2654 its_dev->event_map.nr_lpis);
2655 kfree(its_dev->event_map.col_map);
2657 /* Unmap device/itt */
2658 its_send_mapd(its_dev, 0);
2659 its_free_device(its_dev);
2662 mutex_unlock(&its->dev_alloc_lock);
2664 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2667 static const struct irq_domain_ops its_domain_ops = {
2668 .alloc = its_irq_domain_alloc,
2669 .free = its_irq_domain_free,
2670 .activate = its_irq_domain_activate,
2671 .deactivate = its_irq_domain_deactivate,
2677 * If a GICv4 doesn't implement Direct LPIs (which is extremely
2678 * likely), the only way to perform an invalidate is to use a fake
2679 * device to issue an INV command, implying that the LPI has first
2680 * been mapped to some event on that device. Since this is not exactly
2681 * cheap, we try to keep that mapping around as long as possible, and
2682 * only issue an UNMAP if we're short on available slots.
2684 * Broken by design(tm).
2686 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2688 /* Already unmapped? */
2689 if (vpe->vpe_proxy_event == -1)
2692 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2693 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2696 * We don't track empty slots at all, so let's move the
2697 * next_victim pointer if we can quickly reuse that slot
2698 * instead of nuking an existing entry. Not clear that this is
2699 * always a win though, and this might just generate a ripple
2700 * effect... Let's just hope VPEs don't migrate too often.
2702 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2703 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2705 vpe->vpe_proxy_event = -1;
2708 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2710 if (!gic_rdists->has_direct_lpi) {
2711 unsigned long flags;
2713 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2714 its_vpe_db_proxy_unmap_locked(vpe);
2715 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2719 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2721 /* Already mapped? */
2722 if (vpe->vpe_proxy_event != -1)
2725 /* This slot was already allocated. Kick the other VPE out. */
2726 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2727 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2729 /* Map the new VPE instead */
2730 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2731 vpe->vpe_proxy_event = vpe_proxy.next_victim;
2732 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2734 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2735 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2738 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2740 unsigned long flags;
2741 struct its_collection *target_col;
2743 if (gic_rdists->has_direct_lpi) {
2744 void __iomem *rdbase;
2746 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2747 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2748 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2754 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2756 its_vpe_db_proxy_map_locked(vpe);
2758 target_col = &vpe_proxy.dev->its->collections[to];
2759 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2760 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2762 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2765 static int its_vpe_set_affinity(struct irq_data *d,
2766 const struct cpumask *mask_val,
2769 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2770 int cpu = cpumask_first(mask_val);
2773 * Changing affinity is mega expensive, so let's be as lazy as
2774 * we can and only do it if we really have to. Also, if mapped
2775 * into the proxy device, we need to move the doorbell
2776 * interrupt to its new location.
2778 if (vpe->col_idx != cpu) {
2779 int from = vpe->col_idx;
2782 its_send_vmovp(vpe);
2783 its_vpe_db_proxy_move(vpe, from, cpu);
2786 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2788 return IRQ_SET_MASK_OK_DONE;
2791 static void its_vpe_schedule(struct its_vpe *vpe)
2793 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2796 /* Schedule the VPE */
2797 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2798 GENMASK_ULL(51, 12);
2799 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2800 val |= GICR_VPROPBASER_RaWb;
2801 val |= GICR_VPROPBASER_InnerShareable;
2802 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2804 val = virt_to_phys(page_address(vpe->vpt_page)) &
2805 GENMASK_ULL(51, 16);
2806 val |= GICR_VPENDBASER_RaWaWb;
2807 val |= GICR_VPENDBASER_NonShareable;
2809 * There is no good way of finding out if the pending table is
2810 * empty as we can race against the doorbell interrupt very
2811 * easily. So in the end, vpe->pending_last is only an
2812 * indication that the vcpu has something pending, not one
2813 * that the pending table is empty. A good implementation
2814 * would be able to read its coarse map pretty quickly anyway,
2815 * making this a tolerable issue.
2817 val |= GICR_VPENDBASER_PendingLast;
2818 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2819 val |= GICR_VPENDBASER_Valid;
2820 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2823 static void its_vpe_deschedule(struct its_vpe *vpe)
2825 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2828 val = its_clear_vpend_valid(vlpi_base);
2830 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2831 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2833 vpe->pending_last = true;
2835 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2836 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2840 static void its_vpe_invall(struct its_vpe *vpe)
2842 struct its_node *its;
2844 list_for_each_entry(its, &its_nodes, entry) {
2848 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2852 * Sending a VINVALL to a single ITS is enough, as all
2853 * we need is to reach the redistributors.
2855 its_send_vinvall(its, vpe);
2860 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2862 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2863 struct its_cmd_info *info = vcpu_info;
2865 switch (info->cmd_type) {
2867 its_vpe_schedule(vpe);
2870 case DESCHEDULE_VPE:
2871 its_vpe_deschedule(vpe);
2875 its_vpe_invall(vpe);
2883 static void its_vpe_send_cmd(struct its_vpe *vpe,
2884 void (*cmd)(struct its_device *, u32))
2886 unsigned long flags;
2888 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2890 its_vpe_db_proxy_map_locked(vpe);
2891 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2893 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2896 static void its_vpe_send_inv(struct irq_data *d)
2898 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2900 if (gic_rdists->has_direct_lpi) {
2901 void __iomem *rdbase;
2903 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2904 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2905 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2908 its_vpe_send_cmd(vpe, its_send_inv);
2912 static void its_vpe_mask_irq(struct irq_data *d)
2915 * We need to unmask the LPI, which is described by the parent
2916 * irq_data. Instead of calling into the parent (which won't
2917 * exactly do the right thing, let's simply use the
2918 * parent_data pointer. Yes, I'm naughty.
2920 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2921 its_vpe_send_inv(d);
2924 static void its_vpe_unmask_irq(struct irq_data *d)
2926 /* Same hack as above... */
2927 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2928 its_vpe_send_inv(d);
2931 static int its_vpe_set_irqchip_state(struct irq_data *d,
2932 enum irqchip_irq_state which,
2935 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2937 if (which != IRQCHIP_STATE_PENDING)
2940 if (gic_rdists->has_direct_lpi) {
2941 void __iomem *rdbase;
2943 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2945 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2947 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2948 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2953 its_vpe_send_cmd(vpe, its_send_int);
2955 its_vpe_send_cmd(vpe, its_send_clear);
2961 static struct irq_chip its_vpe_irq_chip = {
2962 .name = "GICv4-vpe",
2963 .irq_mask = its_vpe_mask_irq,
2964 .irq_unmask = its_vpe_unmask_irq,
2965 .irq_eoi = irq_chip_eoi_parent,
2966 .irq_set_affinity = its_vpe_set_affinity,
2967 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
2968 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
2971 static int its_vpe_id_alloc(void)
2973 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2976 static void its_vpe_id_free(u16 id)
2978 ida_simple_remove(&its_vpeid_ida, id);
2981 static int its_vpe_init(struct its_vpe *vpe)
2983 struct page *vpt_page;
2986 /* Allocate vpe_id */
2987 vpe_id = its_vpe_id_alloc();
2992 vpt_page = its_allocate_pending_table(GFP_KERNEL);
2994 its_vpe_id_free(vpe_id);
2998 if (!its_alloc_vpe_table(vpe_id)) {
2999 its_vpe_id_free(vpe_id);
3000 its_free_pending_table(vpe->vpt_page);
3004 vpe->vpe_id = vpe_id;
3005 vpe->vpt_page = vpt_page;
3006 vpe->vpe_proxy_event = -1;
3011 static void its_vpe_teardown(struct its_vpe *vpe)
3013 its_vpe_db_proxy_unmap(vpe);
3014 its_vpe_id_free(vpe->vpe_id);
3015 its_free_pending_table(vpe->vpt_page);
3018 static void its_vpe_irq_domain_free(struct irq_domain *domain,
3020 unsigned int nr_irqs)
3022 struct its_vm *vm = domain->host_data;
3025 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3027 for (i = 0; i < nr_irqs; i++) {
3028 struct irq_data *data = irq_domain_get_irq_data(domain,
3030 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
3032 BUG_ON(vm != vpe->its_vm);
3034 clear_bit(data->hwirq, vm->db_bitmap);
3035 its_vpe_teardown(vpe);
3036 irq_domain_reset_irq_data(data);
3039 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
3040 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
3041 its_free_prop_table(vm->vprop_page);
3045 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3046 unsigned int nr_irqs, void *args)
3048 struct its_vm *vm = args;
3049 unsigned long *bitmap;
3050 struct page *vprop_page;
3051 int base, nr_ids, i, err = 0;
3055 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
3059 if (nr_ids < nr_irqs) {
3060 its_lpi_free(bitmap, base, nr_ids);
3064 vprop_page = its_allocate_prop_table(GFP_KERNEL);
3066 its_lpi_free(bitmap, base, nr_ids);
3070 vm->db_bitmap = bitmap;
3071 vm->db_lpi_base = base;
3072 vm->nr_db_lpis = nr_ids;
3073 vm->vprop_page = vprop_page;
3075 for (i = 0; i < nr_irqs; i++) {
3076 vm->vpes[i]->vpe_db_lpi = base + i;
3077 err = its_vpe_init(vm->vpes[i]);
3080 err = its_irq_gic_domain_alloc(domain, virq + i,
3081 vm->vpes[i]->vpe_db_lpi);
3084 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
3085 &its_vpe_irq_chip, vm->vpes[i]);
3091 its_vpe_irq_domain_free(domain, virq, i - 1);
3093 its_lpi_free(bitmap, base, nr_ids);
3094 its_free_prop_table(vprop_page);
3100 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3101 struct irq_data *d, bool reserve)
3103 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3104 struct its_node *its;
3106 /* If we use the list map, we issue VMAPP on demand... */
3110 /* Map the VPE to the first possible CPU */
3111 vpe->col_idx = cpumask_first(cpu_online_mask);
3113 list_for_each_entry(its, &its_nodes, entry) {
3117 its_send_vmapp(its, vpe, true);
3118 its_send_vinvall(its, vpe);
3121 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3126 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3129 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3130 struct its_node *its;
3133 * If we use the list map, we unmap the VPE once no VLPIs are
3134 * associated with the VM.
3139 list_for_each_entry(its, &its_nodes, entry) {
3143 its_send_vmapp(its, vpe, false);
3147 static const struct irq_domain_ops its_vpe_domain_ops = {
3148 .alloc = its_vpe_irq_domain_alloc,
3149 .free = its_vpe_irq_domain_free,
3150 .activate = its_vpe_irq_domain_activate,
3151 .deactivate = its_vpe_irq_domain_deactivate,
3154 static int its_force_quiescent(void __iomem *base)
3156 u32 count = 1000000; /* 1s */
3159 val = readl_relaxed(base + GITS_CTLR);
3161 * GIC architecture specification requires the ITS to be both
3162 * disabled and quiescent for writes to GITS_BASER<n> or
3163 * GITS_CBASER to not have UNPREDICTABLE results.
3165 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3168 /* Disable the generation of all interrupts to this ITS */
3169 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3170 writel_relaxed(val, base + GITS_CTLR);
3172 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
3174 val = readl_relaxed(base + GITS_CTLR);
3175 if (val & GITS_CTLR_QUIESCENT)
3187 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3189 struct its_node *its = data;
3191 /* erratum 22375: only alloc 8MB table size */
3192 its->device_ids = 0x14; /* 20 bits, 8MB */
3193 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3198 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3200 struct its_node *its = data;
3202 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3207 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3209 struct its_node *its = data;
3211 /* On QDF2400, the size of the ITE is 16Bytes */
3217 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3219 struct its_node *its = its_dev->its;
3222 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
3223 * which maps 32-bit writes targeted at a separate window of
3224 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
3225 * with device ID taken from bits [device_id_bits + 1:2] of
3226 * the window offset.
3228 return its->pre_its_base + (its_dev->device_id << 2);
3231 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
3233 struct its_node *its = data;
3234 u32 pre_its_window[2];
3237 if (!fwnode_property_read_u32_array(its->fwnode_handle,
3238 "socionext,synquacer-pre-its",
3240 ARRAY_SIZE(pre_its_window))) {
3242 its->pre_its_base = pre_its_window[0];
3243 its->get_msi_base = its_irq_get_msi_base_pre_its;
3245 ids = ilog2(pre_its_window[1]) - 2;
3246 if (its->device_ids > ids)
3247 its->device_ids = ids;
3249 /* the pre-ITS breaks isolation, so disable MSI remapping */
3250 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
3256 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
3258 struct its_node *its = data;
3261 * Hip07 insists on using the wrong address for the VLPI
3262 * page. Trick it into doing the right thing...
3264 its->vlpi_redist_offset = SZ_128K;
3268 static const struct gic_quirk its_quirks[] = {
3269 #ifdef CONFIG_CAVIUM_ERRATUM_22375
3271 .desc = "ITS: Cavium errata 22375, 24313",
3272 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3274 .init = its_enable_quirk_cavium_22375,
3277 #ifdef CONFIG_CAVIUM_ERRATUM_23144
3279 .desc = "ITS: Cavium erratum 23144",
3280 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3282 .init = its_enable_quirk_cavium_23144,
3285 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3287 .desc = "ITS: QDF2400 erratum 0065",
3288 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
3290 .init = its_enable_quirk_qdf2400_e0065,
3293 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3296 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3297 * implementation, but with a 'pre-ITS' added that requires
3298 * special handling in software.
3300 .desc = "ITS: Socionext Synquacer pre-ITS",
3303 .init = its_enable_quirk_socionext_synquacer,
3306 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3308 .desc = "ITS: Hip07 erratum 161600802",
3311 .init = its_enable_quirk_hip07_161600802,
3318 static void its_enable_quirks(struct its_node *its)
3320 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3322 gic_enable_quirks(iidr, its_quirks, its);
3325 static int its_save_disable(void)
3327 struct its_node *its;
3330 raw_spin_lock(&its_lock);
3331 list_for_each_entry(its, &its_nodes, entry) {
3334 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3338 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3339 err = its_force_quiescent(base);
3341 pr_err("ITS@%pa: failed to quiesce: %d\n",
3342 &its->phys_base, err);
3343 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3347 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3352 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3355 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3359 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3362 raw_spin_unlock(&its_lock);
3367 static void its_restore_enable(void)
3369 struct its_node *its;
3372 raw_spin_lock(&its_lock);
3373 list_for_each_entry(its, &its_nodes, entry) {
3377 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3383 * Make sure that the ITS is disabled. If it fails to quiesce,
3384 * don't restore it since writing to CBASER or BASER<n>
3385 * registers is undefined according to the GIC v3 ITS
3388 ret = its_force_quiescent(base);
3390 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3391 &its->phys_base, ret);
3395 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3398 * Writing CBASER resets CREADR to 0, so make CWRITER and
3399 * cmd_write line up with it.
3401 its->cmd_write = its->cmd_base;
3402 gits_write_cwriter(0, base + GITS_CWRITER);
3404 /* Restore GITS_BASER from the value cache. */
3405 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3406 struct its_baser *baser = &its->tables[i];
3408 if (!(baser->val & GITS_BASER_VALID))
3411 its_write_baser(its, baser, baser->val);
3413 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3416 * Reinit the collection if it's stored in the ITS. This is
3417 * indicated by the col_id being less than the HCC field.
3418 * CID < HCC as specified in the GIC v3 Documentation.
3420 if (its->collections[smp_processor_id()].col_id <
3421 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3422 its_cpu_init_collection(its);
3424 raw_spin_unlock(&its_lock);
3427 static struct syscore_ops its_syscore_ops = {
3428 .suspend = its_save_disable,
3429 .resume = its_restore_enable,
3432 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3434 struct irq_domain *inner_domain;
3435 struct msi_domain_info *info;
3437 info = kzalloc(sizeof(*info), GFP_KERNEL);
3441 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3442 if (!inner_domain) {
3447 inner_domain->parent = its_parent;
3448 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3449 inner_domain->flags |= its->msi_domain_flags;
3450 info->ops = &its_msi_domain_ops;
3452 inner_domain->host_data = info;
3457 static int its_init_vpe_domain(void)
3459 struct its_node *its;
3463 if (gic_rdists->has_direct_lpi) {
3464 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3468 /* Any ITS will do, even if not v4 */
3469 its = list_first_entry(&its_nodes, struct its_node, entry);
3471 entries = roundup_pow_of_two(nr_cpu_ids);
3472 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3474 if (!vpe_proxy.vpes) {
3475 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3479 /* Use the last possible DevID */
3480 devid = GENMASK(its->device_ids - 1, 0);
3481 vpe_proxy.dev = its_create_device(its, devid, entries, false);
3482 if (!vpe_proxy.dev) {
3483 kfree(vpe_proxy.vpes);
3484 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3488 BUG_ON(entries > vpe_proxy.dev->nr_ites);
3490 raw_spin_lock_init(&vpe_proxy.lock);
3491 vpe_proxy.next_victim = 0;
3492 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3493 devid, vpe_proxy.dev->nr_ites);
3498 static int __init its_compute_its_list_map(struct resource *res,
3499 void __iomem *its_base)
3505 * This is assumed to be done early enough that we're
3506 * guaranteed to be single-threaded, hence no
3507 * locking. Should this change, we should address
3510 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3511 if (its_number >= GICv4_ITS_LIST_MAX) {
3512 pr_err("ITS@%pa: No ITSList entry available!\n",
3517 ctlr = readl_relaxed(its_base + GITS_CTLR);
3518 ctlr &= ~GITS_CTLR_ITS_NUMBER;
3519 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3520 writel_relaxed(ctlr, its_base + GITS_CTLR);
3521 ctlr = readl_relaxed(its_base + GITS_CTLR);
3522 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3523 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3524 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3527 if (test_and_set_bit(its_number, &its_list_map)) {
3528 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3529 &res->start, its_number);
3536 static int __init its_probe_one(struct resource *res,
3537 struct fwnode_handle *handle, int numa_node)
3539 struct its_node *its;
3540 void __iomem *its_base;
3542 u64 baser, tmp, typer;
3546 its_base = ioremap(res->start, resource_size(res));
3548 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3552 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3553 if (val != 0x30 && val != 0x40) {
3554 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3559 err = its_force_quiescent(its_base);
3561 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3565 pr_info("ITS %pR\n", res);
3567 its = kzalloc(sizeof(*its), GFP_KERNEL);
3573 raw_spin_lock_init(&its->lock);
3574 mutex_init(&its->dev_alloc_lock);
3575 INIT_LIST_HEAD(&its->entry);
3576 INIT_LIST_HEAD(&its->its_device_list);
3577 typer = gic_read_typer(its_base + GITS_TYPER);
3578 its->base = its_base;
3579 its->phys_base = res->start;
3580 its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3581 its->device_ids = GITS_TYPER_DEVBITS(typer);
3582 its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3584 if (!(typer & GITS_TYPER_VMOVP)) {
3585 err = its_compute_its_list_map(res, its_base);
3591 pr_info("ITS@%pa: Using ITS number %d\n",
3594 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3598 its->numa_node = numa_node;
3600 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3601 get_order(ITS_CMD_QUEUE_SZ));
3606 its->cmd_base = (void *)page_address(page);
3607 its->cmd_write = its->cmd_base;
3608 its->fwnode_handle = handle;
3609 its->get_msi_base = its_irq_get_msi_base;
3610 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3612 its_enable_quirks(its);
3614 err = its_alloc_tables(its);
3618 err = its_alloc_collections(its);
3620 goto out_free_tables;
3622 baser = (virt_to_phys(its->cmd_base) |
3623 GITS_CBASER_RaWaWb |
3624 GITS_CBASER_InnerShareable |
3625 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3628 gits_write_cbaser(baser, its->base + GITS_CBASER);
3629 tmp = gits_read_cbaser(its->base + GITS_CBASER);
3631 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3632 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3634 * The HW reports non-shareable, we must
3635 * remove the cacheability attributes as
3638 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3639 GITS_CBASER_CACHEABILITY_MASK);
3640 baser |= GITS_CBASER_nC;
3641 gits_write_cbaser(baser, its->base + GITS_CBASER);
3643 pr_info("ITS: using cache flushing for cmd queue\n");
3644 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3647 gits_write_cwriter(0, its->base + GITS_CWRITER);
3648 ctlr = readl_relaxed(its->base + GITS_CTLR);
3649 ctlr |= GITS_CTLR_ENABLE;
3651 ctlr |= GITS_CTLR_ImDe;
3652 writel_relaxed(ctlr, its->base + GITS_CTLR);
3654 if (GITS_TYPER_HCC(typer))
3655 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
3657 err = its_init_domain(handle, its);
3659 goto out_free_tables;
3661 raw_spin_lock(&its_lock);
3662 list_add(&its->entry, &its_nodes);
3663 raw_spin_unlock(&its_lock);
3668 its_free_tables(its);
3670 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3675 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3679 static bool gic_rdists_supports_plpis(void)
3681 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3684 static int redist_disable_lpis(void)
3686 void __iomem *rbase = gic_data_rdist_rd_base();
3687 u64 timeout = USEC_PER_SEC;
3690 if (!gic_rdists_supports_plpis()) {
3691 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3695 val = readl_relaxed(rbase + GICR_CTLR);
3696 if (!(val & GICR_CTLR_ENABLE_LPIS))
3700 * If coming via a CPU hotplug event, we don't need to disable
3701 * LPIs before trying to re-enable them. They are already
3702 * configured and all is well in the world.
3704 * If running with preallocated tables, there is nothing to do.
3706 if (gic_data_rdist()->lpi_enabled ||
3707 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
3711 * From that point on, we only try to do some damage control.
3713 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3714 smp_processor_id());
3715 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3718 val &= ~GICR_CTLR_ENABLE_LPIS;
3719 writel_relaxed(val, rbase + GICR_CTLR);
3721 /* Make sure any change to GICR_CTLR is observable by the GIC */
3725 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3726 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3727 * Error out if we time out waiting for RWP to clear.
3729 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3731 pr_err("CPU%d: Timeout while disabling LPIs\n",
3732 smp_processor_id());
3740 * After it has been written to 1, it is IMPLEMENTATION
3741 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3742 * cleared to 0. Error out if clearing the bit failed.
3744 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3745 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3752 int its_cpu_init(void)
3754 if (!list_empty(&its_nodes)) {
3757 ret = redist_disable_lpis();
3761 its_cpu_init_lpis();
3762 its_cpu_init_collections();
3768 static const struct of_device_id its_device_id[] = {
3769 { .compatible = "arm,gic-v3-its", },
3773 static int __init its_of_probe(struct device_node *node)
3775 struct device_node *np;
3776 struct resource res;
3778 for (np = of_find_matching_node(node, its_device_id); np;
3779 np = of_find_matching_node(np, its_device_id)) {
3780 if (!of_device_is_available(np))
3782 if (!of_property_read_bool(np, "msi-controller")) {
3783 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3788 if (of_address_to_resource(np, 0, &res)) {
3789 pr_warn("%pOF: no regs?\n", np);
3793 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3800 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3802 #ifdef CONFIG_ACPI_NUMA
3803 struct its_srat_map {
3810 static struct its_srat_map *its_srat_maps __initdata;
3811 static int its_in_srat __initdata;
3813 static int __init acpi_get_its_numa_node(u32 its_id)
3817 for (i = 0; i < its_in_srat; i++) {
3818 if (its_id == its_srat_maps[i].its_id)
3819 return its_srat_maps[i].numa_node;
3821 return NUMA_NO_NODE;
3824 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
3825 const unsigned long end)
3830 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
3831 const unsigned long end)
3834 struct acpi_srat_gic_its_affinity *its_affinity;
3836 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3840 if (its_affinity->header.length < sizeof(*its_affinity)) {
3841 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3842 its_affinity->header.length);
3846 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3848 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3849 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3853 its_srat_maps[its_in_srat].numa_node = node;
3854 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3856 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3857 its_affinity->proximity_domain, its_affinity->its_id, node);
3862 static void __init acpi_table_parse_srat_its(void)
3866 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3867 sizeof(struct acpi_table_srat),
3868 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3869 gic_acpi_match_srat_its, 0);
3873 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3875 if (!its_srat_maps) {
3876 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3880 acpi_table_parse_entries(ACPI_SIG_SRAT,
3881 sizeof(struct acpi_table_srat),
3882 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3883 gic_acpi_parse_srat_its, 0);
3886 /* free the its_srat_maps after ITS probing */
3887 static void __init acpi_its_srat_maps_free(void)
3889 kfree(its_srat_maps);
3892 static void __init acpi_table_parse_srat_its(void) { }
3893 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3894 static void __init acpi_its_srat_maps_free(void) { }
3897 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
3898 const unsigned long end)
3900 struct acpi_madt_generic_translator *its_entry;
3901 struct fwnode_handle *dom_handle;
3902 struct resource res;
3905 its_entry = (struct acpi_madt_generic_translator *)header;
3906 memset(&res, 0, sizeof(res));
3907 res.start = its_entry->base_address;
3908 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3909 res.flags = IORESOURCE_MEM;
3911 dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
3913 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3918 err = iort_register_domain_token(its_entry->translation_id, res.start,
3921 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3922 &res.start, its_entry->translation_id);
3926 err = its_probe_one(&res, dom_handle,
3927 acpi_get_its_numa_node(its_entry->translation_id));
3931 iort_deregister_domain_token(its_entry->translation_id);
3933 irq_domain_free_fwnode(dom_handle);
3937 static void __init its_acpi_probe(void)
3939 acpi_table_parse_srat_its();
3940 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3941 gic_acpi_parse_madt_its, 0);
3942 acpi_its_srat_maps_free();
3945 static void __init its_acpi_probe(void) { }
3948 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3949 struct irq_domain *parent_domain)
3951 struct device_node *of_node;
3952 struct its_node *its;
3953 bool has_v4 = false;
3956 its_parent = parent_domain;
3957 of_node = to_of_node(handle);
3959 its_of_probe(of_node);
3963 if (list_empty(&its_nodes)) {
3964 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3968 gic_rdists = rdists;
3970 err = allocate_lpi_tables();
3974 list_for_each_entry(its, &its_nodes, entry)
3975 has_v4 |= its->is_v4;
3977 if (has_v4 & rdists->has_vlpis) {
3978 if (its_init_vpe_domain() ||
3979 its_init_v4(parent_domain, &its_vpe_domain_ops)) {
3980 rdists->has_vlpis = false;
3981 pr_err("ITS: Disabling GICv4 support\n");
3985 register_syscore_ops(&its_syscore_ops);