1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #include <linux/acpi.h>
8 #include <linux/acpi_iort.h>
9 #include <linux/bitmap.h>
10 #include <linux/cpu.h>
11 #include <linux/crash_dump.h>
12 #include <linux/delay.h>
13 #include <linux/dma-iommu.h>
14 #include <linux/efi.h>
15 #include <linux/interrupt.h>
16 #include <linux/irqdomain.h>
17 #include <linux/list.h>
18 #include <linux/log2.h>
19 #include <linux/memblock.h>
21 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/percpu.h>
28 #include <linux/slab.h>
29 #include <linux/syscore_ops.h>
31 #include <linux/irqchip.h>
32 #include <linux/irqchip/arm-gic-v3.h>
33 #include <linux/irqchip/arm-gic-v4.h>
35 #include <asm/cputype.h>
36 #include <asm/exception.h>
38 #include "irq-gic-common.h"
40 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
41 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
42 #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
43 #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3)
45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
46 #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
48 static u32 lpi_id_bits;
51 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
52 * deal with (one configuration byte per interrupt). PENDBASE has to
53 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
55 #define LPI_NRBITS lpi_id_bits
56 #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
57 #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
59 #define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
62 * Collection structure - just an ID, and a redistributor address to
63 * ping. We use one per CPU as a bag of interrupts assigned to this
66 struct its_collection {
72 * The ITS_BASER structure - contains memory information, cached
73 * value of BASER register configuration and ITS page size.
85 * The ITS structure - contains most of the infrastructure, with the
86 * top-level MSI domain, the command queue, the collections, and the
87 * list of devices writing to it.
89 * dev_alloc_lock has to be taken for device allocations, while the
90 * spinlock must be taken to parse data structures such as the device
95 struct mutex dev_alloc_lock;
96 struct list_head entry;
98 phys_addr_t phys_base;
99 struct its_cmd_block *cmd_base;
100 struct its_cmd_block *cmd_write;
101 struct its_baser tables[GITS_BASER_NR_REGS];
102 struct its_collection *collections;
103 struct fwnode_handle *fwnode_handle;
104 u64 (*get_msi_base)(struct its_device *its_dev);
107 struct list_head its_device_list;
109 unsigned long list_nr;
113 unsigned int msi_domain_flags;
114 u32 pre_its_base; /* for Socionext Synquacer */
116 int vlpi_redist_offset;
119 #define ITS_ITT_ALIGN SZ_256
121 /* The maximum number of VPEID bits supported by VLPI commands */
122 #define ITS_MAX_VPEID_BITS (16)
123 #define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
125 /* Convert page order to size in bytes */
126 #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
128 struct event_lpi_map {
129 unsigned long *lpi_map;
131 irq_hw_number_t lpi_base;
133 struct mutex vlpi_lock;
135 struct its_vlpi_map *vlpi_maps;
140 * The ITS view of a device - belongs to an ITS, owns an interrupt
141 * translation table, and a list of interrupts. If it some of its
142 * LPIs are injected into a guest (GICv4), the event_map.vm field
143 * indicates which one.
146 struct list_head entry;
147 struct its_node *its;
148 struct event_lpi_map event_map;
157 struct its_device *dev;
158 struct its_vpe **vpes;
162 static LIST_HEAD(its_nodes);
163 static DEFINE_RAW_SPINLOCK(its_lock);
164 static struct rdists *gic_rdists;
165 static struct irq_domain *its_parent;
167 static unsigned long its_list_map;
168 static u16 vmovp_seq_num;
169 static DEFINE_RAW_SPINLOCK(vmovp_lock);
171 static DEFINE_IDA(its_vpeid_ida);
173 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
174 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
175 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
176 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
178 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
181 struct its_node *its = its_dev->its;
183 return its->collections + its_dev->event_map.col_map[event];
186 static struct its_collection *valid_col(struct its_collection *col)
188 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
194 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
196 if (valid_col(its->collections + vpe->col_idx))
203 * ITS command descriptors - parameters to be encoded in a command
206 struct its_cmd_desc {
209 struct its_device *dev;
214 struct its_device *dev;
219 struct its_device *dev;
224 struct its_device *dev;
229 struct its_collection *col;
234 struct its_device *dev;
240 struct its_device *dev;
241 struct its_collection *col;
246 struct its_device *dev;
251 struct its_collection *col;
260 struct its_collection *col;
266 struct its_device *dev;
274 struct its_device *dev;
281 struct its_collection *col;
289 * The ITS command block, which is what the ITS actually parses.
291 struct its_cmd_block {
295 #define ITS_CMD_QUEUE_SZ SZ_64K
296 #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
298 typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
299 struct its_cmd_block *,
300 struct its_cmd_desc *);
302 typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
303 struct its_cmd_block *,
304 struct its_cmd_desc *);
306 static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
308 u64 mask = GENMASK_ULL(h, l);
310 *raw_cmd |= (val << l) & mask;
313 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
315 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
318 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
320 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
323 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
325 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
328 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
330 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
333 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
335 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
338 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
340 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
343 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
345 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
348 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
350 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
353 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
355 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
358 static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
360 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
363 static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
365 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
368 static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
370 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
373 static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
375 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
378 static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
380 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
383 static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
385 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
388 static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
390 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
393 static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
395 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
398 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
400 /* Let's fixup BE commands */
401 cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
402 cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
403 cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
404 cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
407 static struct its_collection *its_build_mapd_cmd(struct its_node *its,
408 struct its_cmd_block *cmd,
409 struct its_cmd_desc *desc)
411 unsigned long itt_addr;
412 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
414 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
415 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
417 its_encode_cmd(cmd, GITS_CMD_MAPD);
418 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
419 its_encode_size(cmd, size - 1);
420 its_encode_itt(cmd, itt_addr);
421 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
428 static struct its_collection *its_build_mapc_cmd(struct its_node *its,
429 struct its_cmd_block *cmd,
430 struct its_cmd_desc *desc)
432 its_encode_cmd(cmd, GITS_CMD_MAPC);
433 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
434 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
435 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
439 return desc->its_mapc_cmd.col;
442 static struct its_collection *its_build_mapti_cmd(struct its_node *its,
443 struct its_cmd_block *cmd,
444 struct its_cmd_desc *desc)
446 struct its_collection *col;
448 col = dev_event_to_col(desc->its_mapti_cmd.dev,
449 desc->its_mapti_cmd.event_id);
451 its_encode_cmd(cmd, GITS_CMD_MAPTI);
452 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
453 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
454 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
455 its_encode_collection(cmd, col->col_id);
459 return valid_col(col);
462 static struct its_collection *its_build_movi_cmd(struct its_node *its,
463 struct its_cmd_block *cmd,
464 struct its_cmd_desc *desc)
466 struct its_collection *col;
468 col = dev_event_to_col(desc->its_movi_cmd.dev,
469 desc->its_movi_cmd.event_id);
471 its_encode_cmd(cmd, GITS_CMD_MOVI);
472 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
473 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
474 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
478 return valid_col(col);
481 static struct its_collection *its_build_discard_cmd(struct its_node *its,
482 struct its_cmd_block *cmd,
483 struct its_cmd_desc *desc)
485 struct its_collection *col;
487 col = dev_event_to_col(desc->its_discard_cmd.dev,
488 desc->its_discard_cmd.event_id);
490 its_encode_cmd(cmd, GITS_CMD_DISCARD);
491 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
492 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
496 return valid_col(col);
499 static struct its_collection *its_build_inv_cmd(struct its_node *its,
500 struct its_cmd_block *cmd,
501 struct its_cmd_desc *desc)
503 struct its_collection *col;
505 col = dev_event_to_col(desc->its_inv_cmd.dev,
506 desc->its_inv_cmd.event_id);
508 its_encode_cmd(cmd, GITS_CMD_INV);
509 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
510 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
514 return valid_col(col);
517 static struct its_collection *its_build_int_cmd(struct its_node *its,
518 struct its_cmd_block *cmd,
519 struct its_cmd_desc *desc)
521 struct its_collection *col;
523 col = dev_event_to_col(desc->its_int_cmd.dev,
524 desc->its_int_cmd.event_id);
526 its_encode_cmd(cmd, GITS_CMD_INT);
527 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
528 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
532 return valid_col(col);
535 static struct its_collection *its_build_clear_cmd(struct its_node *its,
536 struct its_cmd_block *cmd,
537 struct its_cmd_desc *desc)
539 struct its_collection *col;
541 col = dev_event_to_col(desc->its_clear_cmd.dev,
542 desc->its_clear_cmd.event_id);
544 its_encode_cmd(cmd, GITS_CMD_CLEAR);
545 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
546 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
550 return valid_col(col);
553 static struct its_collection *its_build_invall_cmd(struct its_node *its,
554 struct its_cmd_block *cmd,
555 struct its_cmd_desc *desc)
557 its_encode_cmd(cmd, GITS_CMD_INVALL);
558 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
565 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
566 struct its_cmd_block *cmd,
567 struct its_cmd_desc *desc)
569 its_encode_cmd(cmd, GITS_CMD_VINVALL);
570 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
574 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
577 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
578 struct its_cmd_block *cmd,
579 struct its_cmd_desc *desc)
581 unsigned long vpt_addr;
584 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
585 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
587 its_encode_cmd(cmd, GITS_CMD_VMAPP);
588 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
589 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
590 its_encode_target(cmd, target);
591 its_encode_vpt_addr(cmd, vpt_addr);
592 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
596 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
599 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
600 struct its_cmd_block *cmd,
601 struct its_cmd_desc *desc)
605 if (desc->its_vmapti_cmd.db_enabled)
606 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
610 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
611 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
612 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
613 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
614 its_encode_db_phys_id(cmd, db);
615 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
619 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
622 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
623 struct its_cmd_block *cmd,
624 struct its_cmd_desc *desc)
628 if (desc->its_vmovi_cmd.db_enabled)
629 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
633 its_encode_cmd(cmd, GITS_CMD_VMOVI);
634 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
635 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
636 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
637 its_encode_db_phys_id(cmd, db);
638 its_encode_db_valid(cmd, true);
642 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
645 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
646 struct its_cmd_block *cmd,
647 struct its_cmd_desc *desc)
651 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
652 its_encode_cmd(cmd, GITS_CMD_VMOVP);
653 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
654 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
655 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
656 its_encode_target(cmd, target);
660 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
663 static u64 its_cmd_ptr_to_offset(struct its_node *its,
664 struct its_cmd_block *ptr)
666 return (ptr - its->cmd_base) * sizeof(*ptr);
669 static int its_queue_full(struct its_node *its)
674 widx = its->cmd_write - its->cmd_base;
675 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
677 /* This is incredibly unlikely to happen, unless the ITS locks up. */
678 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
684 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
686 struct its_cmd_block *cmd;
687 u32 count = 1000000; /* 1s! */
689 while (its_queue_full(its)) {
692 pr_err_ratelimited("ITS queue not draining\n");
699 cmd = its->cmd_write++;
701 /* Handle queue wrapping */
702 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
703 its->cmd_write = its->cmd_base;
714 static struct its_cmd_block *its_post_commands(struct its_node *its)
716 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
718 writel_relaxed(wr, its->base + GITS_CWRITER);
720 return its->cmd_write;
723 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
726 * Make sure the commands written to memory are observable by
729 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
730 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
735 static int its_wait_for_range_completion(struct its_node *its,
737 struct its_cmd_block *to)
739 u64 rd_idx, to_idx, linear_idx;
740 u32 count = 1000000; /* 1s! */
742 /* Linearize to_idx if the command set has wrapped around */
743 to_idx = its_cmd_ptr_to_offset(its, to);
744 if (to_idx < prev_idx)
745 to_idx += ITS_CMD_QUEUE_SZ;
747 linear_idx = prev_idx;
752 rd_idx = readl_relaxed(its->base + GITS_CREADR);
755 * Compute the read pointer progress, taking the
756 * potential wrap-around into account.
758 delta = rd_idx - prev_idx;
759 if (rd_idx < prev_idx)
760 delta += ITS_CMD_QUEUE_SZ;
763 if (linear_idx >= to_idx)
768 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
780 /* Warning, macro hell follows */
781 #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
782 void name(struct its_node *its, \
784 struct its_cmd_desc *desc) \
786 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
787 synctype *sync_obj; \
788 unsigned long flags; \
791 raw_spin_lock_irqsave(&its->lock, flags); \
793 cmd = its_allocate_entry(its); \
794 if (!cmd) { /* We're soooooo screewed... */ \
795 raw_spin_unlock_irqrestore(&its->lock, flags); \
798 sync_obj = builder(its, cmd, desc); \
799 its_flush_cmd(its, cmd); \
802 sync_cmd = its_allocate_entry(its); \
806 buildfn(its, sync_cmd, sync_obj); \
807 its_flush_cmd(its, sync_cmd); \
811 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
812 next_cmd = its_post_commands(its); \
813 raw_spin_unlock_irqrestore(&its->lock, flags); \
815 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
816 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
819 static void its_build_sync_cmd(struct its_node *its,
820 struct its_cmd_block *sync_cmd,
821 struct its_collection *sync_col)
823 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
824 its_encode_target(sync_cmd, sync_col->target_address);
826 its_fixup_cmd(sync_cmd);
829 static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
830 struct its_collection, its_build_sync_cmd)
832 static void its_build_vsync_cmd(struct its_node *its,
833 struct its_cmd_block *sync_cmd,
834 struct its_vpe *sync_vpe)
836 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
837 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
839 its_fixup_cmd(sync_cmd);
842 static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
843 struct its_vpe, its_build_vsync_cmd)
845 static void its_send_int(struct its_device *dev, u32 event_id)
847 struct its_cmd_desc desc;
849 desc.its_int_cmd.dev = dev;
850 desc.its_int_cmd.event_id = event_id;
852 its_send_single_command(dev->its, its_build_int_cmd, &desc);
855 static void its_send_clear(struct its_device *dev, u32 event_id)
857 struct its_cmd_desc desc;
859 desc.its_clear_cmd.dev = dev;
860 desc.its_clear_cmd.event_id = event_id;
862 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
865 static void its_send_inv(struct its_device *dev, u32 event_id)
867 struct its_cmd_desc desc;
869 desc.its_inv_cmd.dev = dev;
870 desc.its_inv_cmd.event_id = event_id;
872 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
875 static void its_send_mapd(struct its_device *dev, int valid)
877 struct its_cmd_desc desc;
879 desc.its_mapd_cmd.dev = dev;
880 desc.its_mapd_cmd.valid = !!valid;
882 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
885 static void its_send_mapc(struct its_node *its, struct its_collection *col,
888 struct its_cmd_desc desc;
890 desc.its_mapc_cmd.col = col;
891 desc.its_mapc_cmd.valid = !!valid;
893 its_send_single_command(its, its_build_mapc_cmd, &desc);
896 static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
898 struct its_cmd_desc desc;
900 desc.its_mapti_cmd.dev = dev;
901 desc.its_mapti_cmd.phys_id = irq_id;
902 desc.its_mapti_cmd.event_id = id;
904 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
907 static void its_send_movi(struct its_device *dev,
908 struct its_collection *col, u32 id)
910 struct its_cmd_desc desc;
912 desc.its_movi_cmd.dev = dev;
913 desc.its_movi_cmd.col = col;
914 desc.its_movi_cmd.event_id = id;
916 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
919 static void its_send_discard(struct its_device *dev, u32 id)
921 struct its_cmd_desc desc;
923 desc.its_discard_cmd.dev = dev;
924 desc.its_discard_cmd.event_id = id;
926 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
929 static void its_send_invall(struct its_node *its, struct its_collection *col)
931 struct its_cmd_desc desc;
933 desc.its_invall_cmd.col = col;
935 its_send_single_command(its, its_build_invall_cmd, &desc);
938 static void its_send_vmapti(struct its_device *dev, u32 id)
940 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
941 struct its_cmd_desc desc;
943 desc.its_vmapti_cmd.vpe = map->vpe;
944 desc.its_vmapti_cmd.dev = dev;
945 desc.its_vmapti_cmd.virt_id = map->vintid;
946 desc.its_vmapti_cmd.event_id = id;
947 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
949 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
952 static void its_send_vmovi(struct its_device *dev, u32 id)
954 struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
955 struct its_cmd_desc desc;
957 desc.its_vmovi_cmd.vpe = map->vpe;
958 desc.its_vmovi_cmd.dev = dev;
959 desc.its_vmovi_cmd.event_id = id;
960 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
962 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
965 static void its_send_vmapp(struct its_node *its,
966 struct its_vpe *vpe, bool valid)
968 struct its_cmd_desc desc;
970 desc.its_vmapp_cmd.vpe = vpe;
971 desc.its_vmapp_cmd.valid = valid;
972 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
974 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
977 static void its_send_vmovp(struct its_vpe *vpe)
979 struct its_cmd_desc desc;
980 struct its_node *its;
982 int col_id = vpe->col_idx;
984 desc.its_vmovp_cmd.vpe = vpe;
985 desc.its_vmovp_cmd.its_list = (u16)its_list_map;
988 its = list_first_entry(&its_nodes, struct its_node, entry);
989 desc.its_vmovp_cmd.seq_num = 0;
990 desc.its_vmovp_cmd.col = &its->collections[col_id];
991 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
996 * Yet another marvel of the architecture. If using the
997 * its_list "feature", we need to make sure that all ITSs
998 * receive all VMOVP commands in the same order. The only way
999 * to guarantee this is to make vmovp a serialization point.
1003 raw_spin_lock_irqsave(&vmovp_lock, flags);
1005 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
1008 list_for_each_entry(its, &its_nodes, entry) {
1012 if (!vpe->its_vm->vlpi_count[its->list_nr])
1015 desc.its_vmovp_cmd.col = &its->collections[col_id];
1016 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1019 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1022 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1024 struct its_cmd_desc desc;
1026 desc.its_vinvall_cmd.vpe = vpe;
1027 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1031 * irqchip functions - assumes MSI, mostly.
1034 static inline u32 its_get_event_id(struct irq_data *d)
1036 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1037 return d->hwirq - its_dev->event_map.lpi_base;
1040 static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1042 irq_hw_number_t hwirq;
1046 if (irqd_is_forwarded_to_vcpu(d)) {
1047 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1048 u32 event = its_get_event_id(d);
1049 struct its_vlpi_map *map;
1051 va = page_address(its_dev->event_map.vm->vprop_page);
1052 map = &its_dev->event_map.vlpi_maps[event];
1053 hwirq = map->vintid;
1055 /* Remember the updated property */
1056 map->properties &= ~clr;
1057 map->properties |= set | LPI_PROP_GROUP1;
1059 va = gic_rdists->prop_table_va;
1063 cfg = va + hwirq - 8192;
1065 *cfg |= set | LPI_PROP_GROUP1;
1068 * Make the above write visible to the redistributors.
1069 * And yes, we're flushing exactly: One. Single. Byte.
1072 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1073 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1078 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1080 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1082 lpi_write_config(d, clr, set);
1083 its_send_inv(its_dev, its_get_event_id(d));
1086 static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1088 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1089 u32 event = its_get_event_id(d);
1091 if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
1094 its_dev->event_map.vlpi_maps[event].db_enabled = enable;
1097 * More fun with the architecture:
1099 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1100 * value or to 1023, depending on the enable bit. But that
1101 * would be issueing a mapping for an /existing/ DevID+EventID
1102 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1103 * to the /same/ vPE, using this opportunity to adjust the
1104 * doorbell. Mouahahahaha. We loves it, Precious.
1106 its_send_vmovi(its_dev, event);
1109 static void its_mask_irq(struct irq_data *d)
1111 if (irqd_is_forwarded_to_vcpu(d))
1112 its_vlpi_set_doorbell(d, false);
1114 lpi_update_config(d, LPI_PROP_ENABLED, 0);
1117 static void its_unmask_irq(struct irq_data *d)
1119 if (irqd_is_forwarded_to_vcpu(d))
1120 its_vlpi_set_doorbell(d, true);
1122 lpi_update_config(d, 0, LPI_PROP_ENABLED);
1125 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1129 const struct cpumask *cpu_mask = cpu_online_mask;
1130 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1131 struct its_collection *target_col;
1132 u32 id = its_get_event_id(d);
1134 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1135 if (irqd_is_forwarded_to_vcpu(d))
1138 /* lpi cannot be routed to a redistributor that is on a foreign node */
1139 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
1140 if (its_dev->its->numa_node >= 0) {
1141 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
1142 if (!cpumask_intersects(mask_val, cpu_mask))
1147 cpu = cpumask_any_and(mask_val, cpu_mask);
1149 if (cpu >= nr_cpu_ids)
1152 /* don't set the affinity when the target cpu is same as current one */
1153 if (cpu != its_dev->event_map.col_map[id]) {
1154 target_col = &its_dev->its->collections[cpu];
1155 its_send_movi(its_dev, target_col, id);
1156 its_dev->event_map.col_map[id] = cpu;
1157 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1160 return IRQ_SET_MASK_OK_DONE;
1163 static u64 its_irq_get_msi_base(struct its_device *its_dev)
1165 struct its_node *its = its_dev->its;
1167 return its->phys_base + GITS_TRANSLATER;
1170 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1172 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1173 struct its_node *its;
1177 addr = its->get_msi_base(its_dev);
1179 msg->address_lo = lower_32_bits(addr);
1180 msg->address_hi = upper_32_bits(addr);
1181 msg->data = its_get_event_id(d);
1183 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
1186 static int its_irq_set_irqchip_state(struct irq_data *d,
1187 enum irqchip_irq_state which,
1190 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1191 u32 event = its_get_event_id(d);
1193 if (which != IRQCHIP_STATE_PENDING)
1197 its_send_int(its_dev, event);
1199 its_send_clear(its_dev, event);
1204 static void its_map_vm(struct its_node *its, struct its_vm *vm)
1206 unsigned long flags;
1208 /* Not using the ITS list? Everything is always mapped. */
1212 raw_spin_lock_irqsave(&vmovp_lock, flags);
1215 * If the VM wasn't mapped yet, iterate over the vpes and get
1218 vm->vlpi_count[its->list_nr]++;
1220 if (vm->vlpi_count[its->list_nr] == 1) {
1223 for (i = 0; i < vm->nr_vpes; i++) {
1224 struct its_vpe *vpe = vm->vpes[i];
1225 struct irq_data *d = irq_get_irq_data(vpe->irq);
1227 /* Map the VPE to the first possible CPU */
1228 vpe->col_idx = cpumask_first(cpu_online_mask);
1229 its_send_vmapp(its, vpe, true);
1230 its_send_vinvall(its, vpe);
1231 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1235 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1238 static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1240 unsigned long flags;
1242 /* Not using the ITS list? Everything is always mapped. */
1246 raw_spin_lock_irqsave(&vmovp_lock, flags);
1248 if (!--vm->vlpi_count[its->list_nr]) {
1251 for (i = 0; i < vm->nr_vpes; i++)
1252 its_send_vmapp(its, vm->vpes[i], false);
1255 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1258 static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1260 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1261 u32 event = its_get_event_id(d);
1267 mutex_lock(&its_dev->event_map.vlpi_lock);
1269 if (!its_dev->event_map.vm) {
1270 struct its_vlpi_map *maps;
1272 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1279 its_dev->event_map.vm = info->map->vm;
1280 its_dev->event_map.vlpi_maps = maps;
1281 } else if (its_dev->event_map.vm != info->map->vm) {
1286 /* Get our private copy of the mapping information */
1287 its_dev->event_map.vlpi_maps[event] = *info->map;
1289 if (irqd_is_forwarded_to_vcpu(d)) {
1290 /* Already mapped, move it around */
1291 its_send_vmovi(its_dev, event);
1293 /* Ensure all the VPEs are mapped on this ITS */
1294 its_map_vm(its_dev->its, info->map->vm);
1297 * Flag the interrupt as forwarded so that we can
1298 * start poking the virtual property table.
1300 irqd_set_forwarded_to_vcpu(d);
1302 /* Write out the property to the prop table */
1303 lpi_write_config(d, 0xff, info->map->properties);
1305 /* Drop the physical mapping */
1306 its_send_discard(its_dev, event);
1308 /* and install the virtual one */
1309 its_send_vmapti(its_dev, event);
1311 /* Increment the number of VLPIs */
1312 its_dev->event_map.nr_vlpis++;
1316 mutex_unlock(&its_dev->event_map.vlpi_lock);
1320 static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1322 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1323 u32 event = its_get_event_id(d);
1326 mutex_lock(&its_dev->event_map.vlpi_lock);
1328 if (!its_dev->event_map.vm ||
1329 !its_dev->event_map.vlpi_maps[event].vm) {
1334 /* Copy our mapping information to the incoming request */
1335 *info->map = its_dev->event_map.vlpi_maps[event];
1338 mutex_unlock(&its_dev->event_map.vlpi_lock);
1342 static int its_vlpi_unmap(struct irq_data *d)
1344 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1345 u32 event = its_get_event_id(d);
1348 mutex_lock(&its_dev->event_map.vlpi_lock);
1350 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1355 /* Drop the virtual mapping */
1356 its_send_discard(its_dev, event);
1358 /* and restore the physical one */
1359 irqd_clr_forwarded_to_vcpu(d);
1360 its_send_mapti(its_dev, d->hwirq, event);
1361 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1365 /* Potentially unmap the VM from this ITS */
1366 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1369 * Drop the refcount and make the device available again if
1370 * this was the last VLPI.
1372 if (!--its_dev->event_map.nr_vlpis) {
1373 its_dev->event_map.vm = NULL;
1374 kfree(its_dev->event_map.vlpi_maps);
1378 mutex_unlock(&its_dev->event_map.vlpi_lock);
1382 static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1384 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1386 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1389 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1390 lpi_update_config(d, 0xff, info->config);
1392 lpi_write_config(d, 0xff, info->config);
1393 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1398 static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1400 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1401 struct its_cmd_info *info = vcpu_info;
1404 if (!its_dev->its->is_v4)
1407 /* Unmap request? */
1409 return its_vlpi_unmap(d);
1411 switch (info->cmd_type) {
1413 return its_vlpi_map(d, info);
1416 return its_vlpi_get(d, info);
1418 case PROP_UPDATE_VLPI:
1419 case PROP_UPDATE_AND_INV_VLPI:
1420 return its_vlpi_prop_update(d, info);
1427 static struct irq_chip its_irq_chip = {
1429 .irq_mask = its_mask_irq,
1430 .irq_unmask = its_unmask_irq,
1431 .irq_eoi = irq_chip_eoi_parent,
1432 .irq_set_affinity = its_set_affinity,
1433 .irq_compose_msi_msg = its_irq_compose_msi_msg,
1434 .irq_set_irqchip_state = its_irq_set_irqchip_state,
1435 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
1440 * How we allocate LPIs:
1442 * lpi_range_list contains ranges of LPIs that are to available to
1443 * allocate from. To allocate LPIs, just pick the first range that
1444 * fits the required allocation, and reduce it by the required
1445 * amount. Once empty, remove the range from the list.
1447 * To free a range of LPIs, add a free range to the list, sort it and
1448 * merge the result if the new range happens to be adjacent to an
1449 * already free block.
1451 * The consequence of the above is that allocation is cost is low, but
1452 * freeing is expensive. We assumes that freeing rarely occurs.
1454 #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
1456 static DEFINE_MUTEX(lpi_range_lock);
1457 static LIST_HEAD(lpi_range_list);
1460 struct list_head entry;
1465 static struct lpi_range *mk_lpi_range(u32 base, u32 span)
1467 struct lpi_range *range;
1469 range = kmalloc(sizeof(*range), GFP_KERNEL);
1471 range->base_id = base;
1478 static int alloc_lpi_range(u32 nr_lpis, u32 *base)
1480 struct lpi_range *range, *tmp;
1483 mutex_lock(&lpi_range_lock);
1485 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
1486 if (range->span >= nr_lpis) {
1487 *base = range->base_id;
1488 range->base_id += nr_lpis;
1489 range->span -= nr_lpis;
1491 if (range->span == 0) {
1492 list_del(&range->entry);
1501 mutex_unlock(&lpi_range_lock);
1503 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
1507 static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
1509 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
1511 if (a->base_id + a->span != b->base_id)
1513 b->base_id = a->base_id;
1515 list_del(&a->entry);
1519 static int free_lpi_range(u32 base, u32 nr_lpis)
1521 struct lpi_range *new, *old;
1523 new = mk_lpi_range(base, nr_lpis);
1527 mutex_lock(&lpi_range_lock);
1529 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
1530 if (old->base_id < base)
1534 * old is the last element with ->base_id smaller than base,
1535 * so new goes right after it. If there are no elements with
1536 * ->base_id smaller than base, &old->entry ends up pointing
1537 * at the head of the list, and inserting new it the start of
1538 * the list is the right thing to do in that case as well.
1540 list_add(&new->entry, &old->entry);
1542 * Now check if we can merge with the preceding and/or
1545 merge_lpi_ranges(old, new);
1546 merge_lpi_ranges(new, list_next_entry(new, entry));
1548 mutex_unlock(&lpi_range_lock);
1552 static int __init its_lpi_init(u32 id_bits)
1554 u32 lpis = (1UL << id_bits) - 8192;
1558 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
1560 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
1562 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
1567 * Initializing the allocator is just the same as freeing the
1568 * full range of LPIs.
1570 err = free_lpi_range(8192, lpis);
1571 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
1575 static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1577 unsigned long *bitmap = NULL;
1581 err = alloc_lpi_range(nr_irqs, base);
1586 } while (nr_irqs > 0);
1594 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
1602 *base = *nr_ids = 0;
1607 static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
1609 WARN_ON(free_lpi_range(base, nr_ids));
1613 static void gic_reset_prop_table(void *va)
1615 /* Priority 0xa0, Group-1, disabled */
1616 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
1618 /* Make sure the GIC will observe the written configuration */
1619 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
1622 static struct page *its_allocate_prop_table(gfp_t gfp_flags)
1624 struct page *prop_page;
1626 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
1630 gic_reset_prop_table(page_address(prop_page));
1635 static void its_free_prop_table(struct page *prop_page)
1637 free_pages((unsigned long)page_address(prop_page),
1638 get_order(LPI_PROPBASE_SZ));
1641 static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
1643 phys_addr_t start, end, addr_end;
1647 * We don't bother checking for a kdump kernel as by
1648 * construction, the LPI tables are out of this kernel's
1651 if (is_kdump_kernel())
1654 addr_end = addr + size - 1;
1656 for_each_reserved_mem_region(i, &start, &end) {
1657 if (addr >= start && addr_end <= end)
1661 /* Not found, not a good sign... */
1662 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
1664 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
1668 static int gic_reserve_range(phys_addr_t addr, unsigned long size)
1670 if (efi_enabled(EFI_CONFIG_TABLES))
1671 return efi_mem_reserve_persistent(addr, size);
1676 static int __init its_setup_lpi_prop_table(void)
1678 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
1681 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
1682 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
1684 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
1685 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
1688 gic_reset_prop_table(gic_rdists->prop_table_va);
1692 lpi_id_bits = min_t(u32,
1693 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
1694 ITS_MAX_LPI_NRBITS);
1695 page = its_allocate_prop_table(GFP_NOWAIT);
1697 pr_err("Failed to allocate PROPBASE\n");
1701 gic_rdists->prop_table_pa = page_to_phys(page);
1702 gic_rdists->prop_table_va = page_address(page);
1703 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
1707 pr_info("GICv3: using LPI property table @%pa\n",
1708 &gic_rdists->prop_table_pa);
1710 return its_lpi_init(lpi_id_bits);
1713 static const char *its_base_type_string[] = {
1714 [GITS_BASER_TYPE_DEVICE] = "Devices",
1715 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
1716 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
1717 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
1718 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
1719 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
1720 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
1723 static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
1725 u32 idx = baser - its->tables;
1727 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1730 static void its_write_baser(struct its_node *its, struct its_baser *baser,
1733 u32 idx = baser - its->tables;
1735 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1736 baser->val = its_read_baser(its, baser);
1739 static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1740 u64 cache, u64 shr, u32 psz, u32 order,
1743 u64 val = its_read_baser(its, baser);
1744 u64 esz = GITS_BASER_ENTRY_SIZE(val);
1745 u64 type = GITS_BASER_TYPE(val);
1746 u64 baser_phys, tmp;
1752 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
1753 if (alloc_pages > GITS_BASER_PAGES_MAX) {
1754 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
1755 &its->phys_base, its_base_type_string[type],
1756 alloc_pages, GITS_BASER_PAGES_MAX);
1757 alloc_pages = GITS_BASER_PAGES_MAX;
1758 order = get_order(GITS_BASER_PAGES_MAX * psz);
1761 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
1765 base = (void *)page_address(page);
1766 baser_phys = virt_to_phys(base);
1768 /* Check if the physical address of the memory is above 48bits */
1769 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
1771 /* 52bit PA is supported only when PageSize=64K */
1772 if (psz != SZ_64K) {
1773 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
1774 free_pages((unsigned long)base, order);
1778 /* Convert 52bit PA to 48bit field */
1779 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
1784 (type << GITS_BASER_TYPE_SHIFT) |
1785 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
1786 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
1791 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
1795 val |= GITS_BASER_PAGE_SIZE_4K;
1798 val |= GITS_BASER_PAGE_SIZE_16K;
1801 val |= GITS_BASER_PAGE_SIZE_64K;
1805 its_write_baser(its, baser, val);
1808 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
1810 * Shareability didn't stick. Just use
1811 * whatever the read reported, which is likely
1812 * to be the only thing this redistributor
1813 * supports. If that's zero, make it
1814 * non-cacheable as well.
1816 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
1818 cache = GITS_BASER_nC;
1819 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1824 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
1826 * Page size didn't stick. Let's try a smaller
1827 * size and retry. If we reach 4K, then
1828 * something is horribly wrong...
1830 free_pages((unsigned long)base, order);
1836 goto retry_alloc_baser;
1839 goto retry_alloc_baser;
1844 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1845 &its->phys_base, its_base_type_string[type],
1847 free_pages((unsigned long)base, order);
1851 baser->order = order;
1854 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1856 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1857 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1858 its_base_type_string[type],
1859 (unsigned long)virt_to_phys(base),
1860 indirect ? "indirect" : "flat", (int)esz,
1861 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
1866 static bool its_parse_indirect_baser(struct its_node *its,
1867 struct its_baser *baser,
1868 u32 psz, u32 *order, u32 ids)
1870 u64 tmp = its_read_baser(its, baser);
1871 u64 type = GITS_BASER_TYPE(tmp);
1872 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1873 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1874 u32 new_order = *order;
1875 bool indirect = false;
1877 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
1878 if ((esz << ids) > (psz * 2)) {
1880 * Find out whether hw supports a single or two-level table by
1881 * table by reading bit at offset '62' after writing '1' to it.
1883 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
1884 indirect = !!(baser->val & GITS_BASER_INDIRECT);
1888 * The size of the lvl2 table is equal to ITS page size
1889 * which is 'psz'. For computing lvl1 table size,
1890 * subtract ID bits that sparse lvl2 table from 'ids'
1891 * which is reported by ITS hardware times lvl1 table
1894 ids -= ilog2(psz / (int)esz);
1895 esz = GITS_LVL1_ENTRY_SIZE;
1900 * Allocate as many entries as required to fit the
1901 * range of device IDs that the ITS can grok... The ID
1902 * space being incredibly sparse, this results in a
1903 * massive waste of memory if two-level device table
1904 * feature is not supported by hardware.
1906 new_order = max_t(u32, get_order(esz << ids), new_order);
1907 if (new_order >= MAX_ORDER) {
1908 new_order = MAX_ORDER - 1;
1909 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1910 pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
1911 &its->phys_base, its_base_type_string[type],
1912 its->device_ids, ids);
1920 static void its_free_tables(struct its_node *its)
1924 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1925 if (its->tables[i].base) {
1926 free_pages((unsigned long)its->tables[i].base,
1927 its->tables[i].order);
1928 its->tables[i].base = NULL;
1933 static int its_alloc_tables(struct its_node *its)
1935 u64 shr = GITS_BASER_InnerShareable;
1936 u64 cache = GITS_BASER_RaWaWb;
1940 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
1941 /* erratum 24313: ignore memory access type */
1942 cache = GITS_BASER_nCnB;
1944 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1945 struct its_baser *baser = its->tables + i;
1946 u64 val = its_read_baser(its, baser);
1947 u64 type = GITS_BASER_TYPE(val);
1948 u32 order = get_order(psz);
1949 bool indirect = false;
1952 case GITS_BASER_TYPE_NONE:
1955 case GITS_BASER_TYPE_DEVICE:
1956 indirect = its_parse_indirect_baser(its, baser,
1961 case GITS_BASER_TYPE_VCPU:
1962 indirect = its_parse_indirect_baser(its, baser,
1964 ITS_MAX_VPEID_BITS);
1968 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1970 its_free_tables(its);
1974 /* Update settings which will be used for next BASERn */
1976 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1977 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1983 static int its_alloc_collections(struct its_node *its)
1987 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
1989 if (!its->collections)
1992 for (i = 0; i < nr_cpu_ids; i++)
1993 its->collections[i].target_address = ~0ULL;
1998 static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2000 struct page *pend_page;
2002 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
2003 get_order(LPI_PENDBASE_SZ));
2007 /* Make sure the GIC will observe the zero-ed page */
2008 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2013 static void its_free_pending_table(struct page *pt)
2015 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
2019 * Booting with kdump and LPIs enabled is generally fine. Any other
2020 * case is wrong in the absence of firmware/EFI support.
2022 static bool enabled_lpis_allowed(void)
2027 /* Check whether the property table is in a reserved region */
2028 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2029 addr = val & GENMASK_ULL(51, 12);
2031 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
2034 static int __init allocate_lpi_tables(void)
2040 * If LPIs are enabled while we run this from the boot CPU,
2041 * flag the RD tables as pre-allocated if the stars do align.
2043 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2044 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2045 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2046 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2047 pr_info("GICv3: Using preallocated redistributor tables\n");
2050 err = its_setup_lpi_prop_table();
2055 * We allocate all the pending tables anyway, as we may have a
2056 * mix of RDs that have had LPIs enabled, and some that
2057 * don't. We'll free the unused ones as each CPU comes online.
2059 for_each_possible_cpu(cpu) {
2060 struct page *pend_page;
2062 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2064 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2068 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2074 static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
2076 u32 count = 1000000; /* 1s! */
2080 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2081 val &= ~GICR_VPENDBASER_Valid;
2082 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2085 val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
2086 clean = !(val & GICR_VPENDBASER_Dirty);
2092 } while (!clean && count);
2097 static void its_cpu_init_lpis(void)
2099 void __iomem *rbase = gic_data_rdist_rd_base();
2100 struct page *pend_page;
2104 if (gic_data_rdist()->lpi_enabled)
2107 val = readl_relaxed(rbase + GICR_CTLR);
2108 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
2109 (val & GICR_CTLR_ENABLE_LPIS)) {
2111 * Check that we get the same property table on all
2112 * RDs. If we don't, this is hopeless.
2114 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
2115 paddr &= GENMASK_ULL(51, 12);
2116 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
2117 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2119 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2120 paddr &= GENMASK_ULL(51, 16);
2122 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
2123 its_free_pending_table(gic_data_rdist()->pend_page);
2124 gic_data_rdist()->pend_page = NULL;
2129 pend_page = gic_data_rdist()->pend_page;
2130 paddr = page_to_phys(pend_page);
2131 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
2134 val = (gic_rdists->prop_table_pa |
2135 GICR_PROPBASER_InnerShareable |
2136 GICR_PROPBASER_RaWaWb |
2137 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
2139 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2140 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2142 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2143 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
2145 * The HW reports non-shareable, we must
2146 * remove the cacheability attributes as
2149 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
2150 GICR_PROPBASER_CACHEABILITY_MASK);
2151 val |= GICR_PROPBASER_nC;
2152 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2154 pr_info_once("GIC: using cache flushing for LPI property table\n");
2155 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
2159 val = (page_to_phys(pend_page) |
2160 GICR_PENDBASER_InnerShareable |
2161 GICR_PENDBASER_RaWaWb);
2163 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2164 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2166 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
2168 * The HW reports non-shareable, we must remove the
2169 * cacheability attributes as well.
2171 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
2172 GICR_PENDBASER_CACHEABILITY_MASK);
2173 val |= GICR_PENDBASER_nC;
2174 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2178 val = readl_relaxed(rbase + GICR_CTLR);
2179 val |= GICR_CTLR_ENABLE_LPIS;
2180 writel_relaxed(val, rbase + GICR_CTLR);
2182 if (gic_rdists->has_vlpis) {
2183 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2186 * It's possible for CPU to receive VLPIs before it is
2187 * sheduled as a vPE, especially for the first CPU, and the
2188 * VLPI with INTID larger than 2^(IDbits+1) will be considered
2189 * as out of range and dropped by GIC.
2190 * So we initialize IDbits to known value to avoid VLPI drop.
2192 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2193 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
2194 smp_processor_id(), val);
2195 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2198 * Also clear Valid bit of GICR_VPENDBASER, in case some
2199 * ancient programming gets left in and has possibility of
2200 * corrupting memory.
2202 val = its_clear_vpend_valid(vlpi_base);
2203 WARN_ON(val & GICR_VPENDBASER_Dirty);
2206 /* Make sure the GIC has seen the above */
2209 gic_data_rdist()->lpi_enabled = true;
2210 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
2212 gic_data_rdist()->pend_page ? "allocated" : "reserved",
2216 static void its_cpu_init_collection(struct its_node *its)
2218 int cpu = smp_processor_id();
2221 /* avoid cross node collections and its mapping */
2222 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
2223 struct device_node *cpu_node;
2225 cpu_node = of_get_cpu_node(cpu, NULL);
2226 if (its->numa_node != NUMA_NO_NODE &&
2227 its->numa_node != of_node_to_nid(cpu_node))
2232 * We now have to bind each collection to its target
2235 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2237 * This ITS wants the physical address of the
2240 target = gic_data_rdist()->phys_base;
2242 /* This ITS wants a linear CPU number. */
2243 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2244 target = GICR_TYPER_CPU_NUMBER(target) << 16;
2247 /* Perform collection mapping */
2248 its->collections[cpu].target_address = target;
2249 its->collections[cpu].col_id = cpu;
2251 its_send_mapc(its, &its->collections[cpu], 1);
2252 its_send_invall(its, &its->collections[cpu]);
2255 static void its_cpu_init_collections(void)
2257 struct its_node *its;
2259 raw_spin_lock(&its_lock);
2261 list_for_each_entry(its, &its_nodes, entry)
2262 its_cpu_init_collection(its);
2264 raw_spin_unlock(&its_lock);
2267 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
2269 struct its_device *its_dev = NULL, *tmp;
2270 unsigned long flags;
2272 raw_spin_lock_irqsave(&its->lock, flags);
2274 list_for_each_entry(tmp, &its->its_device_list, entry) {
2275 if (tmp->device_id == dev_id) {
2281 raw_spin_unlock_irqrestore(&its->lock, flags);
2286 static struct its_baser *its_get_baser(struct its_node *its, u32 type)
2290 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
2291 if (GITS_BASER_TYPE(its->tables[i].val) == type)
2292 return &its->tables[i];
2298 static bool its_alloc_table_entry(struct its_node *its,
2299 struct its_baser *baser, u32 id)
2305 /* Don't allow device id that exceeds single, flat table limit */
2306 esz = GITS_BASER_ENTRY_SIZE(baser->val);
2307 if (!(baser->val & GITS_BASER_INDIRECT))
2308 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2310 /* Compute 1st level table index & check if that exceeds table limit */
2311 idx = id >> ilog2(baser->psz / esz);
2312 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
2315 table = baser->base;
2317 /* Allocate memory for 2nd level table */
2319 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
2320 get_order(baser->psz));
2324 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2325 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2326 gic_flush_dcache_to_poc(page_address(page), baser->psz);
2328 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2330 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2331 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2332 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2334 /* Ensure updated table contents are visible to ITS hardware */
2341 static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
2343 struct its_baser *baser;
2345 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
2347 /* Don't allow device id that exceeds ITS hardware limit */
2349 return (ilog2(dev_id) < its->device_ids);
2351 return its_alloc_table_entry(its, baser, dev_id);
2354 static bool its_alloc_vpe_table(u32 vpe_id)
2356 struct its_node *its;
2359 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
2360 * could try and only do it on ITSs corresponding to devices
2361 * that have interrupts targeted at this VPE, but the
2362 * complexity becomes crazy (and you have tons of memory
2365 list_for_each_entry(its, &its_nodes, entry) {
2366 struct its_baser *baser;
2371 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
2375 if (!its_alloc_table_entry(its, baser, vpe_id))
2382 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2383 int nvecs, bool alloc_lpis)
2385 struct its_device *dev;
2386 unsigned long *lpi_map = NULL;
2387 unsigned long flags;
2388 u16 *col_map = NULL;
2395 if (!its_alloc_device_table(its, dev_id))
2398 if (WARN_ON(!is_power_of_2(nvecs)))
2399 nvecs = roundup_pow_of_two(nvecs);
2401 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2403 * Even if the device wants a single LPI, the ITT must be
2404 * sized as a power of two (and you need at least one bit...).
2406 nr_ites = max(2, nvecs);
2407 sz = nr_ites * its->ite_size;
2408 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2409 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
2411 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2413 col_map = kcalloc(nr_lpis, sizeof(*col_map),
2416 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2421 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
2429 gic_flush_dcache_to_poc(itt, sz);
2433 dev->nr_ites = nr_ites;
2434 dev->event_map.lpi_map = lpi_map;
2435 dev->event_map.col_map = col_map;
2436 dev->event_map.lpi_base = lpi_base;
2437 dev->event_map.nr_lpis = nr_lpis;
2438 mutex_init(&dev->event_map.vlpi_lock);
2439 dev->device_id = dev_id;
2440 INIT_LIST_HEAD(&dev->entry);
2442 raw_spin_lock_irqsave(&its->lock, flags);
2443 list_add(&dev->entry, &its->its_device_list);
2444 raw_spin_unlock_irqrestore(&its->lock, flags);
2446 /* Map device to its ITT */
2447 its_send_mapd(dev, 1);
2452 static void its_free_device(struct its_device *its_dev)
2454 unsigned long flags;
2456 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2457 list_del(&its_dev->entry);
2458 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2459 kfree(its_dev->itt);
2463 static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
2467 /* Find a free LPI region in lpi_map and allocate them. */
2468 idx = bitmap_find_free_region(dev->event_map.lpi_map,
2469 dev->event_map.nr_lpis,
2470 get_count_order(nvecs));
2474 *hwirq = dev->event_map.lpi_base + idx;
2479 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
2480 int nvec, msi_alloc_info_t *info)
2482 struct its_node *its;
2483 struct its_device *its_dev;
2484 struct msi_domain_info *msi_info;
2489 * We ignore "dev" entirely, and rely on the dev_id that has
2490 * been passed via the scratchpad. This limits this domain's
2491 * usefulness to upper layers that definitely know that they
2492 * are built on top of the ITS.
2494 dev_id = info->scratchpad[0].ul;
2496 msi_info = msi_get_domain_info(domain);
2497 its = msi_info->data;
2499 if (!gic_rdists->has_direct_lpi &&
2501 vpe_proxy.dev->its == its &&
2502 dev_id == vpe_proxy.dev->device_id) {
2503 /* Bad luck. Get yourself a better implementation */
2504 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
2509 mutex_lock(&its->dev_alloc_lock);
2510 its_dev = its_find_device(its, dev_id);
2513 * We already have seen this ID, probably through
2514 * another alias (PCI bridge of some sort). No need to
2515 * create the device.
2517 its_dev->shared = true;
2518 pr_debug("Reusing ITT for devID %x\n", dev_id);
2522 its_dev = its_create_device(its, dev_id, nvec, true);
2528 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2530 mutex_unlock(&its->dev_alloc_lock);
2531 info->scratchpad[0].ptr = its_dev;
2535 static struct msi_domain_ops its_msi_domain_ops = {
2536 .msi_prepare = its_msi_prepare,
2539 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
2541 irq_hw_number_t hwirq)
2543 struct irq_fwspec fwspec;
2545 if (irq_domain_get_of_node(domain->parent)) {
2546 fwspec.fwnode = domain->parent->fwnode;
2547 fwspec.param_count = 3;
2548 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
2549 fwspec.param[1] = hwirq;
2550 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2551 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
2552 fwspec.fwnode = domain->parent->fwnode;
2553 fwspec.param_count = 2;
2554 fwspec.param[0] = hwirq;
2555 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2560 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
2563 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2564 unsigned int nr_irqs, void *args)
2566 msi_alloc_info_t *info = args;
2567 struct its_device *its_dev = info->scratchpad[0].ptr;
2568 struct its_node *its = its_dev->its;
2569 irq_hw_number_t hwirq;
2573 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
2577 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
2581 for (i = 0; i < nr_irqs; i++) {
2582 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
2586 irq_domain_set_hwirq_and_chip(domain, virq + i,
2587 hwirq + i, &its_irq_chip, its_dev);
2588 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2589 pr_debug("ID:%d pID:%d vID:%d\n",
2590 (int)(hwirq + i - its_dev->event_map.lpi_base),
2591 (int)(hwirq + i), virq + i);
2597 static int its_irq_domain_activate(struct irq_domain *domain,
2598 struct irq_data *d, bool reserve)
2600 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2601 u32 event = its_get_event_id(d);
2602 const struct cpumask *cpu_mask = cpu_online_mask;
2605 /* get the cpu_mask of local node */
2606 if (its_dev->its->numa_node >= 0)
2607 cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2609 /* Bind the LPI to the first possible CPU */
2610 cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
2611 if (cpu >= nr_cpu_ids) {
2612 if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
2615 cpu = cpumask_first(cpu_online_mask);
2618 its_dev->event_map.col_map[event] = cpu;
2619 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2621 /* Map the GIC IRQ and event to the device */
2622 its_send_mapti(its_dev, d->hwirq, event);
2626 static void its_irq_domain_deactivate(struct irq_domain *domain,
2629 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2630 u32 event = its_get_event_id(d);
2632 /* Stop the delivery of interrupts */
2633 its_send_discard(its_dev, event);
2636 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2637 unsigned int nr_irqs)
2639 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2640 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2641 struct its_node *its = its_dev->its;
2644 bitmap_release_region(its_dev->event_map.lpi_map,
2645 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
2646 get_count_order(nr_irqs));
2648 for (i = 0; i < nr_irqs; i++) {
2649 struct irq_data *data = irq_domain_get_irq_data(domain,
2651 /* Nuke the entry in the domain */
2652 irq_domain_reset_irq_data(data);
2655 mutex_lock(&its->dev_alloc_lock);
2658 * If all interrupts have been freed, start mopping the
2659 * floor. This is conditionned on the device not being shared.
2661 if (!its_dev->shared &&
2662 bitmap_empty(its_dev->event_map.lpi_map,
2663 its_dev->event_map.nr_lpis)) {
2664 its_lpi_free(its_dev->event_map.lpi_map,
2665 its_dev->event_map.lpi_base,
2666 its_dev->event_map.nr_lpis);
2667 kfree(its_dev->event_map.col_map);
2669 /* Unmap device/itt */
2670 its_send_mapd(its_dev, 0);
2671 its_free_device(its_dev);
2674 mutex_unlock(&its->dev_alloc_lock);
2676 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2679 static const struct irq_domain_ops its_domain_ops = {
2680 .alloc = its_irq_domain_alloc,
2681 .free = its_irq_domain_free,
2682 .activate = its_irq_domain_activate,
2683 .deactivate = its_irq_domain_deactivate,
2689 * If a GICv4 doesn't implement Direct LPIs (which is extremely
2690 * likely), the only way to perform an invalidate is to use a fake
2691 * device to issue an INV command, implying that the LPI has first
2692 * been mapped to some event on that device. Since this is not exactly
2693 * cheap, we try to keep that mapping around as long as possible, and
2694 * only issue an UNMAP if we're short on available slots.
2696 * Broken by design(tm).
2698 static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
2700 /* Already unmapped? */
2701 if (vpe->vpe_proxy_event == -1)
2704 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
2705 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
2708 * We don't track empty slots at all, so let's move the
2709 * next_victim pointer if we can quickly reuse that slot
2710 * instead of nuking an existing entry. Not clear that this is
2711 * always a win though, and this might just generate a ripple
2712 * effect... Let's just hope VPEs don't migrate too often.
2714 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2715 vpe_proxy.next_victim = vpe->vpe_proxy_event;
2717 vpe->vpe_proxy_event = -1;
2720 static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
2722 if (!gic_rdists->has_direct_lpi) {
2723 unsigned long flags;
2725 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2726 its_vpe_db_proxy_unmap_locked(vpe);
2727 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2731 static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
2733 /* Already mapped? */
2734 if (vpe->vpe_proxy_event != -1)
2737 /* This slot was already allocated. Kick the other VPE out. */
2738 if (vpe_proxy.vpes[vpe_proxy.next_victim])
2739 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
2741 /* Map the new VPE instead */
2742 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
2743 vpe->vpe_proxy_event = vpe_proxy.next_victim;
2744 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
2746 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
2747 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
2750 static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
2752 unsigned long flags;
2753 struct its_collection *target_col;
2755 if (gic_rdists->has_direct_lpi) {
2756 void __iomem *rdbase;
2758 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
2759 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2760 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2766 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2768 its_vpe_db_proxy_map_locked(vpe);
2770 target_col = &vpe_proxy.dev->its->collections[to];
2771 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
2772 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
2774 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2777 static int its_vpe_set_affinity(struct irq_data *d,
2778 const struct cpumask *mask_val,
2781 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2782 int cpu = cpumask_first(mask_val);
2785 * Changing affinity is mega expensive, so let's be as lazy as
2786 * we can and only do it if we really have to. Also, if mapped
2787 * into the proxy device, we need to move the doorbell
2788 * interrupt to its new location.
2790 if (vpe->col_idx != cpu) {
2791 int from = vpe->col_idx;
2794 its_send_vmovp(vpe);
2795 its_vpe_db_proxy_move(vpe, from, cpu);
2798 irq_data_update_effective_affinity(d, cpumask_of(cpu));
2800 return IRQ_SET_MASK_OK_DONE;
2803 static void its_vpe_schedule(struct its_vpe *vpe)
2805 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2808 /* Schedule the VPE */
2809 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
2810 GENMASK_ULL(51, 12);
2811 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
2812 val |= GICR_VPROPBASER_RaWb;
2813 val |= GICR_VPROPBASER_InnerShareable;
2814 gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2816 val = virt_to_phys(page_address(vpe->vpt_page)) &
2817 GENMASK_ULL(51, 16);
2818 val |= GICR_VPENDBASER_RaWaWb;
2819 val |= GICR_VPENDBASER_NonShareable;
2821 * There is no good way of finding out if the pending table is
2822 * empty as we can race against the doorbell interrupt very
2823 * easily. So in the end, vpe->pending_last is only an
2824 * indication that the vcpu has something pending, not one
2825 * that the pending table is empty. A good implementation
2826 * would be able to read its coarse map pretty quickly anyway,
2827 * making this a tolerable issue.
2829 val |= GICR_VPENDBASER_PendingLast;
2830 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
2831 val |= GICR_VPENDBASER_Valid;
2832 gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
2835 static void its_vpe_deschedule(struct its_vpe *vpe)
2837 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2840 val = its_clear_vpend_valid(vlpi_base);
2842 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2843 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
2845 vpe->pending_last = true;
2847 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
2848 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
2852 static void its_vpe_invall(struct its_vpe *vpe)
2854 struct its_node *its;
2856 list_for_each_entry(its, &its_nodes, entry) {
2860 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
2864 * Sending a VINVALL to a single ITS is enough, as all
2865 * we need is to reach the redistributors.
2867 its_send_vinvall(its, vpe);
2872 static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
2874 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2875 struct its_cmd_info *info = vcpu_info;
2877 switch (info->cmd_type) {
2879 its_vpe_schedule(vpe);
2882 case DESCHEDULE_VPE:
2883 its_vpe_deschedule(vpe);
2887 its_vpe_invall(vpe);
2895 static void its_vpe_send_cmd(struct its_vpe *vpe,
2896 void (*cmd)(struct its_device *, u32))
2898 unsigned long flags;
2900 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
2902 its_vpe_db_proxy_map_locked(vpe);
2903 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
2905 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
2908 static void its_vpe_send_inv(struct irq_data *d)
2910 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2912 if (gic_rdists->has_direct_lpi) {
2913 void __iomem *rdbase;
2915 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2916 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
2917 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2920 its_vpe_send_cmd(vpe, its_send_inv);
2924 static void its_vpe_mask_irq(struct irq_data *d)
2927 * We need to unmask the LPI, which is described by the parent
2928 * irq_data. Instead of calling into the parent (which won't
2929 * exactly do the right thing, let's simply use the
2930 * parent_data pointer. Yes, I'm naughty.
2932 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
2933 its_vpe_send_inv(d);
2936 static void its_vpe_unmask_irq(struct irq_data *d)
2938 /* Same hack as above... */
2939 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
2940 its_vpe_send_inv(d);
2943 static int its_vpe_set_irqchip_state(struct irq_data *d,
2944 enum irqchip_irq_state which,
2947 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
2949 if (which != IRQCHIP_STATE_PENDING)
2952 if (gic_rdists->has_direct_lpi) {
2953 void __iomem *rdbase;
2955 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
2957 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
2959 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
2960 while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
2965 its_vpe_send_cmd(vpe, its_send_int);
2967 its_vpe_send_cmd(vpe, its_send_clear);
2973 static struct irq_chip its_vpe_irq_chip = {
2974 .name = "GICv4-vpe",
2975 .irq_mask = its_vpe_mask_irq,
2976 .irq_unmask = its_vpe_unmask_irq,
2977 .irq_eoi = irq_chip_eoi_parent,
2978 .irq_set_affinity = its_vpe_set_affinity,
2979 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
2980 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
2983 static int its_vpe_id_alloc(void)
2985 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2988 static void its_vpe_id_free(u16 id)
2990 ida_simple_remove(&its_vpeid_ida, id);
2993 static int its_vpe_init(struct its_vpe *vpe)
2995 struct page *vpt_page;
2998 /* Allocate vpe_id */
2999 vpe_id = its_vpe_id_alloc();
3004 vpt_page = its_allocate_pending_table(GFP_KERNEL);
3006 its_vpe_id_free(vpe_id);
3010 if (!its_alloc_vpe_table(vpe_id)) {
3011 its_vpe_id_free(vpe_id);
3012 its_free_pending_table(vpt_page);
3016 vpe->vpe_id = vpe_id;
3017 vpe->vpt_page = vpt_page;
3018 vpe->vpe_proxy_event = -1;
3023 static void its_vpe_teardown(struct its_vpe *vpe)
3025 its_vpe_db_proxy_unmap(vpe);
3026 its_vpe_id_free(vpe->vpe_id);
3027 its_free_pending_table(vpe->vpt_page);
3030 static void its_vpe_irq_domain_free(struct irq_domain *domain,
3032 unsigned int nr_irqs)
3034 struct its_vm *vm = domain->host_data;
3037 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3039 for (i = 0; i < nr_irqs; i++) {
3040 struct irq_data *data = irq_domain_get_irq_data(domain,
3042 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
3044 BUG_ON(vm != vpe->its_vm);
3046 clear_bit(data->hwirq, vm->db_bitmap);
3047 its_vpe_teardown(vpe);
3048 irq_domain_reset_irq_data(data);
3051 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
3052 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
3053 its_free_prop_table(vm->vprop_page);
3057 static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3058 unsigned int nr_irqs, void *args)
3060 struct its_vm *vm = args;
3061 unsigned long *bitmap;
3062 struct page *vprop_page;
3063 int base, nr_ids, i, err = 0;
3067 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
3071 if (nr_ids < nr_irqs) {
3072 its_lpi_free(bitmap, base, nr_ids);
3076 vprop_page = its_allocate_prop_table(GFP_KERNEL);
3078 its_lpi_free(bitmap, base, nr_ids);
3082 vm->db_bitmap = bitmap;
3083 vm->db_lpi_base = base;
3084 vm->nr_db_lpis = nr_ids;
3085 vm->vprop_page = vprop_page;
3087 for (i = 0; i < nr_irqs; i++) {
3088 vm->vpes[i]->vpe_db_lpi = base + i;
3089 err = its_vpe_init(vm->vpes[i]);
3092 err = its_irq_gic_domain_alloc(domain, virq + i,
3093 vm->vpes[i]->vpe_db_lpi);
3096 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
3097 &its_vpe_irq_chip, vm->vpes[i]);
3103 its_vpe_irq_domain_free(domain, virq, i - 1);
3105 its_lpi_free(bitmap, base, nr_ids);
3106 its_free_prop_table(vprop_page);
3112 static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3113 struct irq_data *d, bool reserve)
3115 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3116 struct its_node *its;
3118 /* If we use the list map, we issue VMAPP on demand... */
3122 /* Map the VPE to the first possible CPU */
3123 vpe->col_idx = cpumask_first(cpu_online_mask);
3125 list_for_each_entry(its, &its_nodes, entry) {
3129 its_send_vmapp(its, vpe, true);
3130 its_send_vinvall(its, vpe);
3133 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
3138 static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
3141 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3142 struct its_node *its;
3145 * If we use the list map, we unmap the VPE once no VLPIs are
3146 * associated with the VM.
3151 list_for_each_entry(its, &its_nodes, entry) {
3155 its_send_vmapp(its, vpe, false);
3159 static const struct irq_domain_ops its_vpe_domain_ops = {
3160 .alloc = its_vpe_irq_domain_alloc,
3161 .free = its_vpe_irq_domain_free,
3162 .activate = its_vpe_irq_domain_activate,
3163 .deactivate = its_vpe_irq_domain_deactivate,
3166 static int its_force_quiescent(void __iomem *base)
3168 u32 count = 1000000; /* 1s */
3171 val = readl_relaxed(base + GITS_CTLR);
3173 * GIC architecture specification requires the ITS to be both
3174 * disabled and quiescent for writes to GITS_BASER<n> or
3175 * GITS_CBASER to not have UNPREDICTABLE results.
3177 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3180 /* Disable the generation of all interrupts to this ITS */
3181 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3182 writel_relaxed(val, base + GITS_CTLR);
3184 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
3186 val = readl_relaxed(base + GITS_CTLR);
3187 if (val & GITS_CTLR_QUIESCENT)
3199 static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3201 struct its_node *its = data;
3203 /* erratum 22375: only alloc 8MB table size */
3204 its->device_ids = 0x14; /* 20 bits, 8MB */
3205 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3210 static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3212 struct its_node *its = data;
3214 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3219 static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3221 struct its_node *its = data;
3223 /* On QDF2400, the size of the ITE is 16Bytes */
3229 static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
3231 struct its_node *its = its_dev->its;
3234 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
3235 * which maps 32-bit writes targeted at a separate window of
3236 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
3237 * with device ID taken from bits [device_id_bits + 1:2] of
3238 * the window offset.
3240 return its->pre_its_base + (its_dev->device_id << 2);
3243 static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
3245 struct its_node *its = data;
3246 u32 pre_its_window[2];
3249 if (!fwnode_property_read_u32_array(its->fwnode_handle,
3250 "socionext,synquacer-pre-its",
3252 ARRAY_SIZE(pre_its_window))) {
3254 its->pre_its_base = pre_its_window[0];
3255 its->get_msi_base = its_irq_get_msi_base_pre_its;
3257 ids = ilog2(pre_its_window[1]) - 2;
3258 if (its->device_ids > ids)
3259 its->device_ids = ids;
3261 /* the pre-ITS breaks isolation, so disable MSI remapping */
3262 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
3268 static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
3270 struct its_node *its = data;
3273 * Hip07 insists on using the wrong address for the VLPI
3274 * page. Trick it into doing the right thing...
3276 its->vlpi_redist_offset = SZ_128K;
3280 static const struct gic_quirk its_quirks[] = {
3281 #ifdef CONFIG_CAVIUM_ERRATUM_22375
3283 .desc = "ITS: Cavium errata 22375, 24313",
3284 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3286 .init = its_enable_quirk_cavium_22375,
3289 #ifdef CONFIG_CAVIUM_ERRATUM_23144
3291 .desc = "ITS: Cavium erratum 23144",
3292 .iidr = 0xa100034c, /* ThunderX pass 1.x */
3294 .init = its_enable_quirk_cavium_23144,
3297 #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
3299 .desc = "ITS: QDF2400 erratum 0065",
3300 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
3302 .init = its_enable_quirk_qdf2400_e0065,
3305 #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
3308 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
3309 * implementation, but with a 'pre-ITS' added that requires
3310 * special handling in software.
3312 .desc = "ITS: Socionext Synquacer pre-ITS",
3315 .init = its_enable_quirk_socionext_synquacer,
3318 #ifdef CONFIG_HISILICON_ERRATUM_161600802
3320 .desc = "ITS: Hip07 erratum 161600802",
3323 .init = its_enable_quirk_hip07_161600802,
3330 static void its_enable_quirks(struct its_node *its)
3332 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
3334 gic_enable_quirks(iidr, its_quirks, its);
3337 static int its_save_disable(void)
3339 struct its_node *its;
3342 raw_spin_lock(&its_lock);
3343 list_for_each_entry(its, &its_nodes, entry) {
3346 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3350 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
3351 err = its_force_quiescent(base);
3353 pr_err("ITS@%pa: failed to quiesce: %d\n",
3354 &its->phys_base, err);
3355 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3359 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
3364 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
3367 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3371 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3374 raw_spin_unlock(&its_lock);
3379 static void its_restore_enable(void)
3381 struct its_node *its;
3384 raw_spin_lock(&its_lock);
3385 list_for_each_entry(its, &its_nodes, entry) {
3389 if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
3395 * Make sure that the ITS is disabled. If it fails to quiesce,
3396 * don't restore it since writing to CBASER or BASER<n>
3397 * registers is undefined according to the GIC v3 ITS
3400 ret = its_force_quiescent(base);
3402 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
3403 &its->phys_base, ret);
3407 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
3410 * Writing CBASER resets CREADR to 0, so make CWRITER and
3411 * cmd_write line up with it.
3413 its->cmd_write = its->cmd_base;
3414 gits_write_cwriter(0, base + GITS_CWRITER);
3416 /* Restore GITS_BASER from the value cache. */
3417 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3418 struct its_baser *baser = &its->tables[i];
3420 if (!(baser->val & GITS_BASER_VALID))
3423 its_write_baser(its, baser, baser->val);
3425 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3428 * Reinit the collection if it's stored in the ITS. This is
3429 * indicated by the col_id being less than the HCC field.
3430 * CID < HCC as specified in the GIC v3 Documentation.
3432 if (its->collections[smp_processor_id()].col_id <
3433 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
3434 its_cpu_init_collection(its);
3436 raw_spin_unlock(&its_lock);
3439 static struct syscore_ops its_syscore_ops = {
3440 .suspend = its_save_disable,
3441 .resume = its_restore_enable,
3444 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3446 struct irq_domain *inner_domain;
3447 struct msi_domain_info *info;
3449 info = kzalloc(sizeof(*info), GFP_KERNEL);
3453 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3454 if (!inner_domain) {
3459 inner_domain->parent = its_parent;
3460 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3461 inner_domain->flags |= its->msi_domain_flags;
3462 info->ops = &its_msi_domain_ops;
3464 inner_domain->host_data = info;
3469 static int its_init_vpe_domain(void)
3471 struct its_node *its;
3475 if (gic_rdists->has_direct_lpi) {
3476 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
3480 /* Any ITS will do, even if not v4 */
3481 its = list_first_entry(&its_nodes, struct its_node, entry);
3483 entries = roundup_pow_of_two(nr_cpu_ids);
3484 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3486 if (!vpe_proxy.vpes) {
3487 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
3491 /* Use the last possible DevID */
3492 devid = GENMASK(its->device_ids - 1, 0);
3493 vpe_proxy.dev = its_create_device(its, devid, entries, false);
3494 if (!vpe_proxy.dev) {
3495 kfree(vpe_proxy.vpes);
3496 pr_err("ITS: Can't allocate GICv4 proxy device\n");
3500 BUG_ON(entries > vpe_proxy.dev->nr_ites);
3502 raw_spin_lock_init(&vpe_proxy.lock);
3503 vpe_proxy.next_victim = 0;
3504 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
3505 devid, vpe_proxy.dev->nr_ites);
3510 static int __init its_compute_its_list_map(struct resource *res,
3511 void __iomem *its_base)
3517 * This is assumed to be done early enough that we're
3518 * guaranteed to be single-threaded, hence no
3519 * locking. Should this change, we should address
3522 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
3523 if (its_number >= GICv4_ITS_LIST_MAX) {
3524 pr_err("ITS@%pa: No ITSList entry available!\n",
3529 ctlr = readl_relaxed(its_base + GITS_CTLR);
3530 ctlr &= ~GITS_CTLR_ITS_NUMBER;
3531 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
3532 writel_relaxed(ctlr, its_base + GITS_CTLR);
3533 ctlr = readl_relaxed(its_base + GITS_CTLR);
3534 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
3535 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
3536 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
3539 if (test_and_set_bit(its_number, &its_list_map)) {
3540 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
3541 &res->start, its_number);
3548 static int __init its_probe_one(struct resource *res,
3549 struct fwnode_handle *handle, int numa_node)
3551 struct its_node *its;
3552 void __iomem *its_base;
3554 u64 baser, tmp, typer;
3558 its_base = ioremap(res->start, resource_size(res));
3560 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3564 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
3565 if (val != 0x30 && val != 0x40) {
3566 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3571 err = its_force_quiescent(its_base);
3573 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3577 pr_info("ITS %pR\n", res);
3579 its = kzalloc(sizeof(*its), GFP_KERNEL);
3585 raw_spin_lock_init(&its->lock);
3586 mutex_init(&its->dev_alloc_lock);
3587 INIT_LIST_HEAD(&its->entry);
3588 INIT_LIST_HEAD(&its->its_device_list);
3589 typer = gic_read_typer(its_base + GITS_TYPER);
3590 its->base = its_base;
3591 its->phys_base = res->start;
3592 its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3593 its->device_ids = GITS_TYPER_DEVBITS(typer);
3594 its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
3596 if (!(typer & GITS_TYPER_VMOVP)) {
3597 err = its_compute_its_list_map(res, its_base);
3603 pr_info("ITS@%pa: Using ITS number %d\n",
3606 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
3610 its->numa_node = numa_node;
3612 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3613 get_order(ITS_CMD_QUEUE_SZ));
3618 its->cmd_base = (void *)page_address(page);
3619 its->cmd_write = its->cmd_base;
3620 its->fwnode_handle = handle;
3621 its->get_msi_base = its_irq_get_msi_base;
3622 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3624 its_enable_quirks(its);
3626 err = its_alloc_tables(its);
3630 err = its_alloc_collections(its);
3632 goto out_free_tables;
3634 baser = (virt_to_phys(its->cmd_base) |
3635 GITS_CBASER_RaWaWb |
3636 GITS_CBASER_InnerShareable |
3637 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
3640 gits_write_cbaser(baser, its->base + GITS_CBASER);
3641 tmp = gits_read_cbaser(its->base + GITS_CBASER);
3643 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3644 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
3646 * The HW reports non-shareable, we must
3647 * remove the cacheability attributes as
3650 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
3651 GITS_CBASER_CACHEABILITY_MASK);
3652 baser |= GITS_CBASER_nC;
3653 gits_write_cbaser(baser, its->base + GITS_CBASER);
3655 pr_info("ITS: using cache flushing for cmd queue\n");
3656 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
3659 gits_write_cwriter(0, its->base + GITS_CWRITER);
3660 ctlr = readl_relaxed(its->base + GITS_CTLR);
3661 ctlr |= GITS_CTLR_ENABLE;
3663 ctlr |= GITS_CTLR_ImDe;
3664 writel_relaxed(ctlr, its->base + GITS_CTLR);
3666 if (GITS_TYPER_HCC(typer))
3667 its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;
3669 err = its_init_domain(handle, its);
3671 goto out_free_tables;
3673 raw_spin_lock(&its_lock);
3674 list_add(&its->entry, &its_nodes);
3675 raw_spin_unlock(&its_lock);
3680 its_free_tables(its);
3682 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3687 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3691 static bool gic_rdists_supports_plpis(void)
3693 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3696 static int redist_disable_lpis(void)
3698 void __iomem *rbase = gic_data_rdist_rd_base();
3699 u64 timeout = USEC_PER_SEC;
3702 if (!gic_rdists_supports_plpis()) {
3703 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
3707 val = readl_relaxed(rbase + GICR_CTLR);
3708 if (!(val & GICR_CTLR_ENABLE_LPIS))
3712 * If coming via a CPU hotplug event, we don't need to disable
3713 * LPIs before trying to re-enable them. They are already
3714 * configured and all is well in the world.
3716 * If running with preallocated tables, there is nothing to do.
3718 if (gic_data_rdist()->lpi_enabled ||
3719 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
3723 * From that point on, we only try to do some damage control.
3725 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3726 smp_processor_id());
3727 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3730 val &= ~GICR_CTLR_ENABLE_LPIS;
3731 writel_relaxed(val, rbase + GICR_CTLR);
3733 /* Make sure any change to GICR_CTLR is observable by the GIC */
3737 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
3738 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
3739 * Error out if we time out waiting for RWP to clear.
3741 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
3743 pr_err("CPU%d: Timeout while disabling LPIs\n",
3744 smp_processor_id());
3752 * After it has been written to 1, it is IMPLEMENTATION
3753 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
3754 * cleared to 0. Error out if clearing the bit failed.
3756 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
3757 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
3764 int its_cpu_init(void)
3766 if (!list_empty(&its_nodes)) {
3769 ret = redist_disable_lpis();
3773 its_cpu_init_lpis();
3774 its_cpu_init_collections();
3780 static const struct of_device_id its_device_id[] = {
3781 { .compatible = "arm,gic-v3-its", },
3785 static int __init its_of_probe(struct device_node *node)
3787 struct device_node *np;
3788 struct resource res;
3790 for (np = of_find_matching_node(node, its_device_id); np;
3791 np = of_find_matching_node(np, its_device_id)) {
3792 if (!of_device_is_available(np))
3794 if (!of_property_read_bool(np, "msi-controller")) {
3795 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
3800 if (of_address_to_resource(np, 0, &res)) {
3801 pr_warn("%pOF: no regs?\n", np);
3805 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3812 #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
3814 #ifdef CONFIG_ACPI_NUMA
3815 struct its_srat_map {
3822 static struct its_srat_map *its_srat_maps __initdata;
3823 static int its_in_srat __initdata;
3825 static int __init acpi_get_its_numa_node(u32 its_id)
3829 for (i = 0; i < its_in_srat; i++) {
3830 if (its_id == its_srat_maps[i].its_id)
3831 return its_srat_maps[i].numa_node;
3833 return NUMA_NO_NODE;
3836 static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
3837 const unsigned long end)
3842 static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
3843 const unsigned long end)
3846 struct acpi_srat_gic_its_affinity *its_affinity;
3848 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
3852 if (its_affinity->header.length < sizeof(*its_affinity)) {
3853 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
3854 its_affinity->header.length);
3858 node = acpi_map_pxm_to_node(its_affinity->proximity_domain);
3860 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
3861 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
3865 its_srat_maps[its_in_srat].numa_node = node;
3866 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
3868 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
3869 its_affinity->proximity_domain, its_affinity->its_id, node);
3874 static void __init acpi_table_parse_srat_its(void)
3878 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
3879 sizeof(struct acpi_table_srat),
3880 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3881 gic_acpi_match_srat_its, 0);
3885 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
3887 if (!its_srat_maps) {
3888 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
3892 acpi_table_parse_entries(ACPI_SIG_SRAT,
3893 sizeof(struct acpi_table_srat),
3894 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
3895 gic_acpi_parse_srat_its, 0);
3898 /* free the its_srat_maps after ITS probing */
3899 static void __init acpi_its_srat_maps_free(void)
3901 kfree(its_srat_maps);
3904 static void __init acpi_table_parse_srat_its(void) { }
3905 static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3906 static void __init acpi_its_srat_maps_free(void) { }
3909 static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
3910 const unsigned long end)
3912 struct acpi_madt_generic_translator *its_entry;
3913 struct fwnode_handle *dom_handle;
3914 struct resource res;
3917 its_entry = (struct acpi_madt_generic_translator *)header;
3918 memset(&res, 0, sizeof(res));
3919 res.start = its_entry->base_address;
3920 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
3921 res.flags = IORESOURCE_MEM;
3923 dom_handle = irq_domain_alloc_fwnode(&res.start);
3925 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
3930 err = iort_register_domain_token(its_entry->translation_id, res.start,
3933 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
3934 &res.start, its_entry->translation_id);
3938 err = its_probe_one(&res, dom_handle,
3939 acpi_get_its_numa_node(its_entry->translation_id));
3943 iort_deregister_domain_token(its_entry->translation_id);
3945 irq_domain_free_fwnode(dom_handle);
3949 static void __init its_acpi_probe(void)
3951 acpi_table_parse_srat_its();
3952 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
3953 gic_acpi_parse_madt_its, 0);
3954 acpi_its_srat_maps_free();
3957 static void __init its_acpi_probe(void) { }
3960 int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
3961 struct irq_domain *parent_domain)
3963 struct device_node *of_node;
3964 struct its_node *its;
3965 bool has_v4 = false;
3968 its_parent = parent_domain;
3969 of_node = to_of_node(handle);
3971 its_of_probe(of_node);
3975 if (list_empty(&its_nodes)) {
3976 pr_warn("ITS: No ITS available, not enabling LPIs\n");
3980 gic_rdists = rdists;
3982 err = allocate_lpi_tables();
3986 list_for_each_entry(its, &its_nodes, entry)
3987 has_v4 |= its->is_v4;
3989 if (has_v4 & rdists->has_vlpis) {
3990 if (its_init_vpe_domain() ||
3991 its_init_v4(parent_domain, &its_vpe_domain_ops)) {
3992 rdists->has_vlpis = false;
3993 pr_err("ITS: Disabling GICv4 support\n");
3997 register_syscore_ops(&its_syscore_ops);