drivers/irqchip/irq-gic-v3.c

   1 /*
   2  * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #define pr_fmt(fmt)     "GICv3: " fmt
  19
  20 #include <linux/acpi.h>
  21 #include <linux/cpu.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/percpu.h>
  30 #include <linux/slab.h>
  31
  32 #include <linux/irqchip.h>
  33 #include <linux/irqchip/arm-gic-common.h>
  34 #include <linux/irqchip/arm-gic-v3.h>
  35 #include <linux/irqchip/irq-partition-percpu.h>
  36
  37 #include <asm/cputype.h>
  38 #include <asm/exception.h>
  39 #include <asm/smp_plat.h>
  40 #include <asm/virt.h>
  41
  42 #include "irq-gic-common.h"
  43
  44 struct redist_region {
  45         void __iomem            *redist_base;
  46         phys_addr_t             phys_base;
  47         bool                    single_redist;
  48 };
  49
  50 struct gic_chip_data {
  51         struct fwnode_handle    *fwnode;
  52         void __iomem            *dist_base;
  53         struct redist_region    *redist_regions;
  54         struct rdists           rdists;
  55         struct irq_domain       *domain;
  56         u64                     redist_stride;
  57         u32                     nr_redist_regions;
  58         bool                    has_rss;
  59         unsigned int            irq_nr;
  60         struct partition_desc   *ppi_descs[16];
  61 };
  62
  63 static struct gic_chip_data gic_data __read_mostly;
  64 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
  65
  66 static struct gic_kvm_info gic_v3_kvm_info;
  67 static DEFINE_PER_CPU(bool, has_rss);
  68
  69 #define MPIDR_RS(mpidr)                 (((mpidr) & 0xF0UL) >> 4)
  70 #define gic_data_rdist()                (this_cpu_ptr(gic_data.rdists.rdist))
  71 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
  72 #define gic_data_rdist_sgi_base()       (gic_data_rdist_rd_base() + SZ_64K)
  73
  74 /* Our default, arbitrary priority value. Linux only uses one anyway. */
  75 #define DEFAULT_PMR_VALUE       0xf0
  76
  77 static inline unsigned int gic_irq(struct irq_data *d)
  78 {
  79         return d->hwirq;
  80 }
  81
  82 static inline int gic_irq_in_rdist(struct irq_data *d)
  83 {
  84         return gic_irq(d) < 32;
  85 }
  86
  87 static inline void __iomem *gic_dist_base(struct irq_data *d)
  88 {
  89         if (gic_irq_in_rdist(d))        /* SGI+PPI -> SGI_base for this CPU */
  90                 return gic_data_rdist_sgi_base();
  91
  92         if (d->hwirq <= 1023)           /* SPI -> dist_base */
  93                 return gic_data.dist_base;
  94
  95         return NULL;
  96 }
  97
  98 static void gic_do_wait_for_rwp(void __iomem *base)
  99 {
 100         u32 count = 1000000;    /* 1s! */
 101
 102         while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
 103                 count--;
 104                 if (!count) {
 105                         pr_err_ratelimited("RWP timeout, gone fishing\n");
 106                         return;
 107                 }
 108                 cpu_relax();
 109                 udelay(1);
 110         };
 111 }
 112
 113 /* Wait for completion of a distributor change */
 114 static void gic_dist_wait_for_rwp(void)
 115 {
 116         gic_do_wait_for_rwp(gic_data.dist_base);
 117 }
 118
 119 /* Wait for completion of a redistributor change */
 120 static void gic_redist_wait_for_rwp(void)
 121 {
 122         gic_do_wait_for_rwp(gic_data_rdist_rd_base());
 123 }
 124
 125 #ifdef CONFIG_ARM64
 126
 127 static u64 __maybe_unused gic_read_iar(void)
 128 {
 129         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
 130                 return gic_read_iar_cavium_thunderx();
 131         else
 132                 return gic_read_iar_common();
 133 }
 134 #endif
 135
 136 static void gic_enable_redist(bool enable)
 137 {
 138         void __iomem *rbase;
 139         u32 count = 1000000;    /* 1s! */
 140         u32 val;
 141
 142         rbase = gic_data_rdist_rd_base();
 143
 144         val = readl_relaxed(rbase + GICR_WAKER);
 145         if (enable)
 146                 /* Wake up this CPU redistributor */
 147                 val &= ~GICR_WAKER_ProcessorSleep;
 148         else
 149                 val |= GICR_WAKER_ProcessorSleep;
 150         writel_relaxed(val, rbase + GICR_WAKER);
 151
 152         if (!enable) {          /* Check that GICR_WAKER is writeable */
 153                 val = readl_relaxed(rbase + GICR_WAKER);
 154                 if (!(val & GICR_WAKER_ProcessorSleep))
 155                         return; /* No PM support in this redistributor */
 156         }
 157
 158         while (--count) {
 159                 val = readl_relaxed(rbase + GICR_WAKER);
 160                 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
 161                         break;
 162                 cpu_relax();
 163                 udelay(1);
 164         };
 165         if (!count)
 166                 pr_err_ratelimited("redistributor failed to %s...\n",
 167                                    enable ? "wakeup" : "sleep");
 168 }
 169
 170 /*
 171  * Routines to disable, enable, EOI and route interrupts
 172  */
 173 static int gic_peek_irq(struct irq_data *d, u32 offset)
 174 {
 175         u32 mask = 1 << (gic_irq(d) % 32);
 176         void __iomem *base;
 177
 178         if (gic_irq_in_rdist(d))
 179                 base = gic_data_rdist_sgi_base();
 180         else
 181                 base = gic_data.dist_base;
 182
 183         return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
 184 }
 185
 186 static void gic_poke_irq(struct irq_data *d, u32 offset)
 187 {
 188         u32 mask = 1 << (gic_irq(d) % 32);
 189         void (*rwp_wait)(void);
 190         void __iomem *base;
 191
 192         if (gic_irq_in_rdist(d)) {
 193                 base = gic_data_rdist_sgi_base();
 194                 rwp_wait = gic_redist_wait_for_rwp;
 195         } else {
 196                 base = gic_data.dist_base;
 197                 rwp_wait = gic_dist_wait_for_rwp;
 198         }
 199
 200         writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
 201         rwp_wait();
 202 }
 203
 204 static void gic_mask_irq(struct irq_data *d)
 205 {
 206         gic_poke_irq(d, GICD_ICENABLER);
 207 }
 208
 209 static void gic_eoimode1_mask_irq(struct irq_data *d)
 210 {
 211         gic_mask_irq(d);
 212         /*
 213          * When masking a forwarded interrupt, make sure it is
 214          * deactivated as well.
 215          *
 216          * This ensures that an interrupt that is getting
 217          * disabled/masked will not get "stuck", because there is
 218          * noone to deactivate it (guest is being terminated).
 219          */
 220         if (irqd_is_forwarded_to_vcpu(d))
 221                 gic_poke_irq(d, GICD_ICACTIVER);
 222 }
 223
 224 static void gic_unmask_irq(struct irq_data *d)
 225 {
 226         gic_poke_irq(d, GICD_ISENABLER);
 227 }
 228
 229 static int gic_irq_set_irqchip_state(struct irq_data *d,
 230                                      enum irqchip_irq_state which, bool val)
 231 {
 232         u32 reg;
 233
 234         if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
 235                 return -EINVAL;
 236
 237         switch (which) {
 238         case IRQCHIP_STATE_PENDING:
 239                 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
 240                 break;
 241
 242         case IRQCHIP_STATE_ACTIVE:
 243                 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
 244                 break;
 245
 246         case IRQCHIP_STATE_MASKED:
 247                 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
 248                 break;
 249
 250         default:
 251                 return -EINVAL;
 252         }
 253
 254         gic_poke_irq(d, reg);
 255         return 0;
 256 }
 257
 258 static int gic_irq_get_irqchip_state(struct irq_data *d,
 259                                      enum irqchip_irq_state which, bool *val)
 260 {
 261         if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
 262                 return -EINVAL;
 263
 264         switch (which) {
 265         case IRQCHIP_STATE_PENDING:
 266                 *val = gic_peek_irq(d, GICD_ISPENDR);
 267                 break;
 268
 269         case IRQCHIP_STATE_ACTIVE:
 270                 *val = gic_peek_irq(d, GICD_ISACTIVER);
 271                 break;
 272
 273         case IRQCHIP_STATE_MASKED:
 274                 *val = !gic_peek_irq(d, GICD_ISENABLER);
 275                 break;
 276
 277         default:
 278                 return -EINVAL;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static void gic_eoi_irq(struct irq_data *d)
 285 {
 286         gic_write_eoir(gic_irq(d));
 287 }
 288
 289 static void gic_eoimode1_eoi_irq(struct irq_data *d)
 290 {
 291         /*
 292          * No need to deactivate an LPI, or an interrupt that
 293          * is is getting forwarded to a vcpu.
 294          */
 295         if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
 296                 return;
 297         gic_write_dir(gic_irq(d));
 298 }
 299
 300 static int gic_set_type(struct irq_data *d, unsigned int type)
 301 {
 302         unsigned int irq = gic_irq(d);
 303         void (*rwp_wait)(void);
 304         void __iomem *base;
 305
 306         /* Interrupt configuration for SGIs can't be changed */
 307         if (irq < 16)
 308                 return -EINVAL;
 309
 310         /* SPIs have restrictions on the supported types */
 311         if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
 312                          type != IRQ_TYPE_EDGE_RISING)
 313                 return -EINVAL;
 314
 315         if (gic_irq_in_rdist(d)) {
 316                 base = gic_data_rdist_sgi_base();
 317                 rwp_wait = gic_redist_wait_for_rwp;
 318         } else {
 319                 base = gic_data.dist_base;
 320                 rwp_wait = gic_dist_wait_for_rwp;
 321         }
 322
 323         return gic_configure_irq(irq, type, base, rwp_wait);
 324 }
 325
 326 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
 327 {
 328         if (vcpu)
 329                 irqd_set_forwarded_to_vcpu(d);
 330         else
 331                 irqd_clr_forwarded_to_vcpu(d);
 332         return 0;
 333 }
 334
 335 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
 336 {
 337         u64 aff;
 338
 339         aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
 340                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 341                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8  |
 342                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 343
 344         return aff;
 345 }
 346
 347 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 348 {
 349         u32 irqnr;
 350
 351         irqnr = gic_read_iar();
 352
 353         if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
 354                 int err;
 355
 356                 if (static_branch_likely(&supports_deactivate_key))
 357                         gic_write_eoir(irqnr);
 358                 else
 359                         isb();
 360
 361                 err = handle_domain_irq(gic_data.domain, irqnr, regs);
 362                 if (err) {
 363                         WARN_ONCE(true, "Unexpected interrupt received!\n");
 364                         if (static_branch_likely(&supports_deactivate_key)) {
 365                                 if (irqnr < 8192)
 366                                         gic_write_dir(irqnr);
 367                         } else {
 368                                 gic_write_eoir(irqnr);
 369                         }
 370                 }
 371                 return;
 372         }
 373         if (irqnr < 16) {
 374                 gic_write_eoir(irqnr);
 375                 if (static_branch_likely(&supports_deactivate_key))
 376                         gic_write_dir(irqnr);
 377 #ifdef CONFIG_SMP
 378                 /*
 379                  * Unlike GICv2, we don't need an smp_rmb() here.
 380                  * The control dependency from gic_read_iar to
 381                  * the ISB in gic_write_eoir is enough to ensure
 382                  * that any shared data read by handle_IPI will
 383                  * be read after the ACK.
 384                  */
 385                 handle_IPI(irqnr, regs);
 386 #else
 387                 WARN_ONCE(true, "Unexpected SGI received!\n");
 388 #endif
 389         }
 390 }
 391
 392 static void __init gic_dist_init(void)
 393 {
 394         unsigned int i;
 395         u64 affinity;
 396         void __iomem *base = gic_data.dist_base;
 397
 398         /* Disable the distributor */
 399         writel_relaxed(0, base + GICD_CTLR);
 400         gic_dist_wait_for_rwp();
 401
 402         /*
 403          * Configure SPIs as non-secure Group-1. This will only matter
 404          * if the GIC only has a single security state. This will not
 405          * do the right thing if the kernel is running in secure mode,
 406          * but that's not the intended use case anyway.
 407          */
 408         for (i = 32; i < gic_data.irq_nr; i += 32)
 409                 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
 410
 411         gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
 412
 413         /* Enable distributor with ARE, Group1 */
 414         writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
 415                        base + GICD_CTLR);
 416
 417         /*
 418          * Set all global interrupts to the boot CPU only. ARE must be
 419          * enabled.
 420          */
 421         affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
 422         for (i = 32; i < gic_data.irq_nr; i++)
 423                 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
 424 }
 425
 426 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
 427 {
 428         int ret = -ENODEV;
 429         int i;
 430
 431         for (i = 0; i < gic_data.nr_redist_regions; i++) {
 432                 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
 433                 u64 typer;
 434                 u32 reg;
 435
 436                 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
 437                 if (reg != GIC_PIDR2_ARCH_GICv3 &&
 438                     reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
 439                         pr_warn("No redistributor present @%p\n", ptr);
 440                         break;
 441                 }
 442
 443                 do {
 444                         typer = gic_read_typer(ptr + GICR_TYPER);
 445                         ret = fn(gic_data.redist_regions + i, ptr);
 446                         if (!ret)
 447                                 return 0;
 448
 449                         if (gic_data.redist_regions[i].single_redist)
 450                                 break;
 451
 452                         if (gic_data.redist_stride) {
 453                                 ptr += gic_data.redist_stride;
 454                         } else {
 455                                 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
 456                                 if (typer & GICR_TYPER_VLPIS)
 457                                         ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
 458                         }
 459                 } while (!(typer & GICR_TYPER_LAST));
 460         }
 461
 462         return ret ? -ENODEV : 0;
 463 }
 464
 465 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
 466 {
 467         unsigned long mpidr = cpu_logical_map(smp_processor_id());
 468         u64 typer;
 469         u32 aff;
 470
 471         /*
 472          * Convert affinity to a 32bit value that can be matched to
 473          * GICR_TYPER bits [63:32].
 474          */
 475         aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
 476                MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
 477                MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
 478                MPIDR_AFFINITY_LEVEL(mpidr, 0));
 479
 480         typer = gic_read_typer(ptr + GICR_TYPER);
 481         if ((typer >> 32) == aff) {
 482                 u64 offset = ptr - region->redist_base;
 483                 gic_data_rdist_rd_base() = ptr;
 484                 gic_data_rdist()->phys_base = region->phys_base + offset;
 485
 486                 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
 487                         smp_processor_id(), mpidr,
 488                         (int)(region - gic_data.redist_regions),
 489                         &gic_data_rdist()->phys_base);
 490                 return 0;
 491         }
 492
 493         /* Try next one */
 494         return 1;
 495 }
 496
 497 static int gic_populate_rdist(void)
 498 {
 499         if (gic_iterate_rdists(__gic_populate_rdist) == 0)
 500                 return 0;
 501
 502         /* We couldn't even deal with ourselves... */
 503         WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
 504              smp_processor_id(),
 505              (unsigned long)cpu_logical_map(smp_processor_id()));
 506         return -ENODEV;
 507 }
 508
 509 static int __gic_update_vlpi_properties(struct redist_region *region,
 510                                         void __iomem *ptr)
 511 {
 512         u64 typer = gic_read_typer(ptr + GICR_TYPER);
 513         gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
 514         gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS);
 515
 516         return 1;
 517 }
 518
 519 static void gic_update_vlpi_properties(void)
 520 {
 521         gic_iterate_rdists(__gic_update_vlpi_properties);
 522         pr_info("%sVLPI support, %sdirect LPI support\n",
 523                 !gic_data.rdists.has_vlpis ? "no " : "",
 524                 !gic_data.rdists.has_direct_lpi ? "no " : "");
 525 }
 526
 527 static void gic_cpu_sys_reg_init(void)
 528 {
 529         int i, cpu = smp_processor_id();
 530         u64 mpidr = cpu_logical_map(cpu);
 531         u64 need_rss = MPIDR_RS(mpidr);
 532         bool group0;
 533         u32 val, pribits;
 534
 535         /*
 536          * Need to check that the SRE bit has actually been set. If
 537          * not, it means that SRE is disabled at EL2. We're going to
 538          * die painfully, and there is nothing we can do about it.
 539          *
 540          * Kindly inform the luser.
 541          */
 542         if (!gic_enable_sre())
 543                 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
 544
 545         pribits = gic_read_ctlr();
 546         pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
 547         pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
 548         pribits++;
 549
 550         /*
 551          * Let's find out if Group0 is under control of EL3 or not by
 552          * setting the highest possible, non-zero priority in PMR.
 553          *
 554          * If SCR_EL3.FIQ is set, the priority gets shifted down in
 555          * order for the CPU interface to set bit 7, and keep the
 556          * actual priority in the non-secure range. In the process, it
 557          * looses the least significant bit and the actual priority
 558          * becomes 0x80. Reading it back returns 0, indicating that
 559          * we're don't have access to Group0.
 560          */
 561         write_gicreg(BIT(8 - pribits), ICC_PMR_EL1);
 562         val = read_gicreg(ICC_PMR_EL1);
 563         group0 = val != 0;
 564
 565         /* Set priority mask register */
 566         write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
 567
 568         /*
 569          * Some firmwares hand over to the kernel with the BPR changed from
 570          * its reset value (and with a value large enough to prevent
 571          * any pre-emptive interrupts from working at all). Writing a zero
 572          * to BPR restores is reset value.
 573          */
 574         gic_write_bpr1(0);
 575
 576         if (static_branch_likely(&supports_deactivate_key)) {
 577                 /* EOI drops priority only (mode 1) */
 578                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
 579         } else {
 580                 /* EOI deactivates interrupt too (mode 0) */
 581                 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
 582         }
 583
 584         /* Always whack Group0 before Group1 */
 585         if (group0) {
 586                 switch(pribits) {
 587                 case 8:
 588                 case 7:
 589                         write_gicreg(0, ICC_AP0R3_EL1);
 590                         write_gicreg(0, ICC_AP0R2_EL1);
 591                 case 6:
 592                         write_gicreg(0, ICC_AP0R1_EL1);
 593                 case 5:
 594                 case 4:
 595                         write_gicreg(0, ICC_AP0R0_EL1);
 596                 }
 597
 598                 isb();
 599         }
 600
 601         switch(pribits) {
 602         case 8:
 603         case 7:
 604                 write_gicreg(0, ICC_AP1R3_EL1);
 605                 write_gicreg(0, ICC_AP1R2_EL1);
 606         case 6:
 607                 write_gicreg(0, ICC_AP1R1_EL1);
 608         case 5:
 609         case 4:
 610                 write_gicreg(0, ICC_AP1R0_EL1);
 611         }
 612
 613         isb();
 614
 615         /* ... and let's hit the road... */
 616         gic_write_grpen1(1);
 617
 618         /* Keep the RSS capability status in per_cpu variable */
 619         per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
 620
 621         /* Check all the CPUs have capable of sending SGIs to other CPUs */
 622         for_each_online_cpu(i) {
 623                 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
 624
 625                 need_rss |= MPIDR_RS(cpu_logical_map(i));
 626                 if (need_rss && (!have_rss))
 627                         pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
 628                                 cpu, (unsigned long)mpidr,
 629                                 i, (unsigned long)cpu_logical_map(i));
 630         }
 631
 632         /**
 633          * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
 634          * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
 635          * UNPREDICTABLE choice of :
 636          *   - The write is ignored.
 637          *   - The RS field is treated as 0.
 638          */
 639         if (need_rss && (!gic_data.has_rss))
 640                 pr_crit_once("RSS is required but GICD doesn't support it\n");
 641 }
 642
 643 static bool gicv3_nolpi;
 644
 645 static int __init gicv3_nolpi_cfg(char *buf)
 646 {
 647         return strtobool(buf, &gicv3_nolpi);
 648 }
 649 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
 650
 651 static int gic_dist_supports_lpis(void)
 652 {
 653         return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
 654                 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
 655                 !gicv3_nolpi);
 656 }
 657
 658 static void gic_cpu_init(void)
 659 {
 660         void __iomem *rbase;
 661
 662         /* Register ourselves with the rest of the world */
 663         if (gic_populate_rdist())
 664                 return;
 665
 666         gic_enable_redist(true);
 667
 668         rbase = gic_data_rdist_sgi_base();
 669
 670         /* Configure SGIs/PPIs as non-secure Group-1 */
 671         writel_relaxed(~0, rbase + GICR_IGROUPR0);
 672
 673         gic_cpu_config(rbase, gic_redist_wait_for_rwp);
 674
 675         /* initialise system registers */
 676         gic_cpu_sys_reg_init();
 677 }
 678
 679 #ifdef CONFIG_SMP
 680
 681 #define MPIDR_TO_SGI_RS(mpidr)  (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
 682 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr)  ((mpidr) & ~0xFUL)
 683
 684 static int gic_starting_cpu(unsigned int cpu)
 685 {
 686         gic_cpu_init();
 687
 688         if (gic_dist_supports_lpis())
 689                 its_cpu_init();
 690
 691         return 0;
 692 }
 693
 694 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
 695                                    unsigned long cluster_id)
 696 {
 697         int next_cpu, cpu = *base_cpu;
 698         unsigned long mpidr = cpu_logical_map(cpu);
 699         u16 tlist = 0;
 700
 701         while (cpu < nr_cpu_ids) {
 702                 tlist |= 1 << (mpidr & 0xf);
 703
 704                 next_cpu = cpumask_next(cpu, mask);
 705                 if (next_cpu >= nr_cpu_ids)
 706                         goto out;
 707                 cpu = next_cpu;
 708
 709                 mpidr = cpu_logical_map(cpu);
 710
 711                 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
 712                         cpu--;
 713                         goto out;
 714                 }
 715         }
 716 out:
 717         *base_cpu = cpu;
 718         return tlist;
 719 }
 720
 721 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
 722         (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
 723                 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
 724
 725 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
 726 {
 727         u64 val;
 728
 729         val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3)     |
 730                MPIDR_TO_SGI_AFFINITY(cluster_id, 2)     |
 731                irq << ICC_SGI1R_SGI_ID_SHIFT            |
 732                MPIDR_TO_SGI_AFFINITY(cluster_id, 1)     |
 733                MPIDR_TO_SGI_RS(cluster_id)              |
 734                tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
 735
 736         pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
 737         gic_write_sgi1r(val);
 738 }
 739
 740 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 741 {
 742         int cpu;
 743
 744         if (WARN_ON(irq >= 16))
 745                 return;
 746
 747         /*
 748          * Ensure that stores to Normal memory are visible to the
 749          * other CPUs before issuing the IPI.
 750          */
 751         wmb();
 752
 753         for_each_cpu(cpu, mask) {
 754                 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
 755                 u16 tlist;
 756
 757                 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
 758                 gic_send_sgi(cluster_id, tlist, irq);
 759         }
 760
 761         /* Force the above writes to ICC_SGI1R_EL1 to be executed */
 762         isb();
 763 }
 764
 765 static void gic_smp_init(void)
 766 {
 767         set_smp_cross_call(gic_raise_softirq);
 768         cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
 769                                   "irqchip/arm/gicv3:starting",
 770                                   gic_starting_cpu, NULL);
 771 }
 772
 773 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 774                             bool force)
 775 {
 776         unsigned int cpu;
 777         void __iomem *reg;
 778         int enabled;
 779         u64 val;
 780
 781         if (force)
 782                 cpu = cpumask_first(mask_val);
 783         else
 784                 cpu = cpumask_any_and(mask_val, cpu_online_mask);
 785
 786         if (cpu >= nr_cpu_ids)
 787                 return -EINVAL;
 788
 789         if (gic_irq_in_rdist(d))
 790                 return -EINVAL;
 791
 792         /* If interrupt was enabled, disable it first */
 793         enabled = gic_peek_irq(d, GICD_ISENABLER);
 794         if (enabled)
 795                 gic_mask_irq(d);
 796
 797         reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
 798         val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
 799
 800         gic_write_irouter(val, reg);
 801
 802         /*
 803          * If the interrupt was enabled, enabled it again. Otherwise,
 804          * just wait for the distributor to have digested our changes.
 805          */
 806         if (enabled)
 807                 gic_unmask_irq(d);
 808         else
 809                 gic_dist_wait_for_rwp();
 810
 811         irq_data_update_effective_affinity(d, cpumask_of(cpu));
 812
 813         return IRQ_SET_MASK_OK_DONE;
 814 }
 815 #else
 816 #define gic_set_affinity        NULL
 817 #define gic_smp_init()          do { } while(0)
 818 #endif
 819
 820 #ifdef CONFIG_CPU_PM
 821 /* Check whether it's single security state view */
 822 static bool gic_dist_security_disabled(void)
 823 {
 824         return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
 825 }
 826
 827 static int gic_cpu_pm_notifier(struct notifier_block *self,
 828                                unsigned long cmd, void *v)
 829 {
 830         if (cmd == CPU_PM_EXIT) {
 831                 if (gic_dist_security_disabled())
 832                         gic_enable_redist(true);
 833                 gic_cpu_sys_reg_init();
 834         } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
 835                 gic_write_grpen1(0);
 836                 gic_enable_redist(false);
 837         }
 838         return NOTIFY_OK;
 839 }
 840
 841 static struct notifier_block gic_cpu_pm_notifier_block = {
 842         .notifier_call = gic_cpu_pm_notifier,
 843 };
 844
 845 static void gic_cpu_pm_init(void)
 846 {
 847         cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
 848 }
 849
 850 #else
 851 static inline void gic_cpu_pm_init(void) { }
 852 #endif /* CONFIG_CPU_PM */
 853
 854 static struct irq_chip gic_chip = {
 855         .name                   = "GICv3",
 856         .irq_mask               = gic_mask_irq,
 857         .irq_unmask             = gic_unmask_irq,
 858         .irq_eoi                = gic_eoi_irq,
 859         .irq_set_type           = gic_set_type,
 860         .irq_set_affinity       = gic_set_affinity,
 861         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 862         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 863         .flags                  = IRQCHIP_SET_TYPE_MASKED |
 864                                   IRQCHIP_SKIP_SET_WAKE |
 865                                   IRQCHIP_MASK_ON_SUSPEND,
 866 };
 867
 868 static struct irq_chip gic_eoimode1_chip = {
 869         .name                   = "GICv3",
 870         .irq_mask               = gic_eoimode1_mask_irq,
 871         .irq_unmask             = gic_unmask_irq,
 872         .irq_eoi                = gic_eoimode1_eoi_irq,
 873         .irq_set_type           = gic_set_type,
 874         .irq_set_affinity       = gic_set_affinity,
 875         .irq_get_irqchip_state  = gic_irq_get_irqchip_state,
 876         .irq_set_irqchip_state  = gic_irq_set_irqchip_state,
 877         .irq_set_vcpu_affinity  = gic_irq_set_vcpu_affinity,
 878         .flags                  = IRQCHIP_SET_TYPE_MASKED |
 879                                   IRQCHIP_SKIP_SET_WAKE |
 880                                   IRQCHIP_MASK_ON_SUSPEND,
 881 };
 882
 883 #define GIC_ID_NR       (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
 884
 885 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 886                               irq_hw_number_t hw)
 887 {
 888         struct irq_chip *chip = &gic_chip;
 889
 890         if (static_branch_likely(&supports_deactivate_key))
 891                 chip = &gic_eoimode1_chip;
 892
 893         /* SGIs are private to the core kernel */
 894         if (hw < 16)
 895                 return -EPERM;
 896         /* Nothing here */
 897         if (hw >= gic_data.irq_nr && hw < 8192)
 898                 return -EPERM;
 899         /* Off limits */
 900         if (hw >= GIC_ID_NR)
 901                 return -EPERM;
 902
 903         /* PPIs */
 904         if (hw < 32) {
 905                 irq_set_percpu_devid(irq);
 906                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
 907                                     handle_percpu_devid_irq, NULL, NULL);
 908                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 909         }
 910         /* SPIs */
 911         if (hw >= 32 && hw < gic_data.irq_nr) {
 912                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
 913                                     handle_fasteoi_irq, NULL, NULL);
 914                 irq_set_probe(irq);
 915                 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
 916         }
 917         /* LPIs */
 918         if (hw >= 8192 && hw < GIC_ID_NR) {
 919                 if (!gic_dist_supports_lpis())
 920                         return -EPERM;
 921                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
 922                                     handle_fasteoi_irq, NULL, NULL);
 923         }
 924
 925         return 0;
 926 }
 927
 928 #define GIC_IRQ_TYPE_PARTITION  (GIC_IRQ_TYPE_LPI + 1)
 929
 930 static int gic_irq_domain_translate(struct irq_domain *d,
 931                                     struct irq_fwspec *fwspec,
 932                                     unsigned long *hwirq,
 933                                     unsigned int *type)
 934 {
 935         if (is_of_node(fwspec->fwnode)) {
 936                 if (fwspec->param_count < 3)
 937                         return -EINVAL;
 938
 939                 switch (fwspec->param[0]) {
 940                 case 0:                 /* SPI */
 941                         *hwirq = fwspec->param[1] + 32;
 942                         break;
 943                 case 1:                 /* PPI */
 944                 case GIC_IRQ_TYPE_PARTITION:
 945                         *hwirq = fwspec->param[1] + 16;
 946                         break;
 947                 case GIC_IRQ_TYPE_LPI:  /* LPI */
 948                         *hwirq = fwspec->param[1];
 949                         break;
 950                 default:
 951                         return -EINVAL;
 952                 }
 953
 954                 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
 955
 956                 /*
 957                  * Make it clear that broken DTs are... broken.
 958                  * Partitionned PPIs are an unfortunate exception.
 959                  */
 960                 WARN_ON(*type == IRQ_TYPE_NONE &&
 961                         fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
 962                 return 0;
 963         }
 964
 965         if (is_fwnode_irqchip(fwspec->fwnode)) {
 966                 if(fwspec->param_count != 2)
 967                         return -EINVAL;
 968
 969                 *hwirq = fwspec->param[0];
 970                 *type = fwspec->param[1];
 971
 972                 WARN_ON(*type == IRQ_TYPE_NONE);
 973                 return 0;
 974         }
 975
 976         return -EINVAL;
 977 }
 978
 979 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 980                                 unsigned int nr_irqs, void *arg)
 981 {
 982         int i, ret;
 983         irq_hw_number_t hwirq;
 984         unsigned int type = IRQ_TYPE_NONE;
 985         struct irq_fwspec *fwspec = arg;
 986
 987         ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
 988         if (ret)
 989                 return ret;
 990
 991         for (i = 0; i < nr_irqs; i++) {
 992                 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
 993                 if (ret)
 994                         return ret;
 995         }
 996
 997         return 0;
 998 }
 999
1000 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1001                                 unsigned int nr_irqs)
1002 {
1003         int i;
1004
1005         for (i = 0; i < nr_irqs; i++) {
1006                 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1007                 irq_set_handler(virq + i, NULL);
1008                 irq_domain_reset_irq_data(d);
1009         }
1010 }
1011
1012 static int gic_irq_domain_select(struct irq_domain *d,
1013                                  struct irq_fwspec *fwspec,
1014                                  enum irq_domain_bus_token bus_token)
1015 {
1016         /* Not for us */
1017         if (fwspec->fwnode != d->fwnode)
1018                 return 0;
1019
1020         /* If this is not DT, then we have a single domain */
1021         if (!is_of_node(fwspec->fwnode))
1022                 return 1;
1023
1024         /*
1025          * If this is a PPI and we have a 4th (non-null) parameter,
1026          * then we need to match the partition domain.
1027          */
1028         if (fwspec->param_count >= 4 &&
1029             fwspec->param[0] == 1 && fwspec->param[3] != 0)
1030                 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1031
1032         return d == gic_data.domain;
1033 }
1034
1035 static const struct irq_domain_ops gic_irq_domain_ops = {
1036         .translate = gic_irq_domain_translate,
1037         .alloc = gic_irq_domain_alloc,
1038         .free = gic_irq_domain_free,
1039         .select = gic_irq_domain_select,
1040 };
1041
1042 static int partition_domain_translate(struct irq_domain *d,
1043                                       struct irq_fwspec *fwspec,
1044                                       unsigned long *hwirq,
1045                                       unsigned int *type)
1046 {
1047         struct device_node *np;
1048         int ret;
1049
1050         np = of_find_node_by_phandle(fwspec->param[3]);
1051         if (WARN_ON(!np))
1052                 return -EINVAL;
1053
1054         ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1055                                      of_node_to_fwnode(np));
1056         if (ret < 0)
1057                 return ret;
1058
1059         *hwirq = ret;
1060         *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1061
1062         return 0;
1063 }
1064
1065 static const struct irq_domain_ops partition_domain_ops = {
1066         .translate = partition_domain_translate,
1067         .select = gic_irq_domain_select,
1068 };
1069
1070 static int __init gic_init_bases(void __iomem *dist_base,
1071                                  struct redist_region *rdist_regs,
1072                                  u32 nr_redist_regions,
1073                                  u64 redist_stride,
1074                                  struct fwnode_handle *handle)
1075 {
1076         u32 typer;
1077         int gic_irqs;
1078         int err;
1079
1080         if (!is_hyp_mode_available())
1081                 static_branch_disable(&supports_deactivate_key);
1082
1083         if (static_branch_likely(&supports_deactivate_key))
1084                 pr_info("GIC: Using split EOI/Deactivate mode\n");
1085
1086         gic_data.fwnode = handle;
1087         gic_data.dist_base = dist_base;
1088         gic_data.redist_regions = rdist_regs;
1089         gic_data.nr_redist_regions = nr_redist_regions;
1090         gic_data.redist_stride = redist_stride;
1091
1092         /*
1093          * Find out how many interrupts are supported.
1094          * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
1095          */
1096         typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1097         gic_data.rdists.gicd_typer = typer;
1098         gic_irqs = GICD_TYPER_IRQS(typer);
1099         if (gic_irqs > 1020)
1100                 gic_irqs = 1020;
1101         gic_data.irq_nr = gic_irqs;
1102
1103         gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1104                                                  &gic_data);
1105         irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1106         gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1107         gic_data.rdists.has_vlpis = true;
1108         gic_data.rdists.has_direct_lpi = true;
1109
1110         if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1111                 err = -ENOMEM;
1112                 goto out_free;
1113         }
1114
1115         gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1116         pr_info("Distributor has %sRange Selector support\n",
1117                 gic_data.has_rss ? "" : "no ");
1118
1119         if (typer & GICD_TYPER_MBIS) {
1120                 err = mbi_init(handle, gic_data.domain);
1121                 if (err)
1122                         pr_err("Failed to initialize MBIs\n");
1123         }
1124
1125         set_handle_irq(gic_handle_irq);
1126
1127         gic_update_vlpi_properties();
1128
1129         gic_smp_init();
1130         gic_dist_init();
1131         gic_cpu_init();
1132         gic_cpu_pm_init();
1133
1134         if (gic_dist_supports_lpis()) {
1135                 its_init(handle, &gic_data.rdists, gic_data.domain);
1136                 its_cpu_init();
1137         }
1138
1139         return 0;
1140
1141 out_free:
1142         if (gic_data.domain)
1143                 irq_domain_remove(gic_data.domain);
1144         free_percpu(gic_data.rdists.rdist);
1145         return err;
1146 }
1147
1148 static int __init gic_validate_dist_version(void __iomem *dist_base)
1149 {
1150         u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1151
1152         if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1153                 return -ENODEV;
1154
1155         return 0;
1156 }
1157
1158 /* Create all possible partitions at boot time */
1159 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1160 {
1161         struct device_node *parts_node, *child_part;
1162         int part_idx = 0, i;
1163         int nr_parts;
1164         struct partition_affinity *parts;
1165
1166         parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1167         if (!parts_node)
1168                 return;
1169
1170         nr_parts = of_get_child_count(parts_node);
1171
1172         if (!nr_parts)
1173                 goto out_put_node;
1174
1175         parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1176         if (WARN_ON(!parts))
1177                 goto out_put_node;
1178
1179         for_each_child_of_node(parts_node, child_part) {
1180                 struct partition_affinity *part;
1181                 int n;
1182
1183                 part = &parts[part_idx];
1184
1185                 part->partition_id = of_node_to_fwnode(child_part);
1186
1187                 pr_info("GIC: PPI partition %s[%d] { ",
1188                         child_part->name, part_idx);
1189
1190                 n = of_property_count_elems_of_size(child_part, "affinity",
1191                                                     sizeof(u32));
1192                 WARN_ON(n <= 0);
1193
1194                 for (i = 0; i < n; i++) {
1195                         int err, cpu;
1196                         u32 cpu_phandle;
1197                         struct device_node *cpu_node;
1198
1199                         err = of_property_read_u32_index(child_part, "affinity",
1200                                                          i, &cpu_phandle);
1201                         if (WARN_ON(err))
1202                                 continue;
1203
1204                         cpu_node = of_find_node_by_phandle(cpu_phandle);
1205                         if (WARN_ON(!cpu_node))
1206                                 continue;
1207
1208                         cpu = of_cpu_node_to_id(cpu_node);
1209                         if (WARN_ON(cpu < 0))
1210                                 continue;
1211
1212                         pr_cont("%pOF[%d] ", cpu_node, cpu);
1213
1214                         cpumask_set_cpu(cpu, &part->mask);
1215                 }
1216
1217                 pr_cont("}\n");
1218                 part_idx++;
1219         }
1220
1221         for (i = 0; i < 16; i++) {
1222                 unsigned int irq;
1223                 struct partition_desc *desc;
1224                 struct irq_fwspec ppi_fwspec = {
1225                         .fwnode         = gic_data.fwnode,
1226                         .param_count    = 3,
1227                         .param          = {
1228                                 [0]     = GIC_IRQ_TYPE_PARTITION,
1229                                 [1]     = i,
1230                                 [2]     = IRQ_TYPE_NONE,
1231                         },
1232                 };
1233
1234                 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1235                 if (WARN_ON(!irq))
1236                         continue;
1237                 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1238                                              irq, &partition_domain_ops);
1239                 if (WARN_ON(!desc))
1240                         continue;
1241
1242                 gic_data.ppi_descs[i] = desc;
1243         }
1244
1245 out_put_node:
1246         of_node_put(parts_node);
1247 }
1248
1249 static void __init gic_of_setup_kvm_info(struct device_node *node)
1250 {
1251         int ret;
1252         struct resource r;
1253         u32 gicv_idx;
1254
1255         gic_v3_kvm_info.type = GIC_V3;
1256
1257         gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1258         if (!gic_v3_kvm_info.maint_irq)
1259                 return;
1260
1261         if (of_property_read_u32(node, "#redistributor-regions",
1262                                  &gicv_idx))
1263                 gicv_idx = 1;
1264
1265         gicv_idx += 3;  /* Also skip GICD, GICC, GICH */
1266         ret = of_address_to_resource(node, gicv_idx, &r);
1267         if (!ret)
1268                 gic_v3_kvm_info.vcpu = r;
1269
1270         gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1271         gic_set_kvm_info(&gic_v3_kvm_info);
1272 }
1273
1274 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1275 {
1276         void __iomem *dist_base;
1277         struct redist_region *rdist_regs;
1278         u64 redist_stride;
1279         u32 nr_redist_regions;
1280         int err, i;
1281
1282         dist_base = of_iomap(node, 0);
1283         if (!dist_base) {
1284                 pr_err("%pOF: unable to map gic dist registers\n", node);
1285                 return -ENXIO;
1286         }
1287
1288         err = gic_validate_dist_version(dist_base);
1289         if (err) {
1290                 pr_err("%pOF: no distributor detected, giving up\n", node);
1291                 goto out_unmap_dist;
1292         }
1293
1294         if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1295                 nr_redist_regions = 1;
1296
1297         rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1298                              GFP_KERNEL);
1299         if (!rdist_regs) {
1300                 err = -ENOMEM;
1301                 goto out_unmap_dist;
1302         }
1303
1304         for (i = 0; i < nr_redist_regions; i++) {
1305                 struct resource res;
1306                 int ret;
1307
1308                 ret = of_address_to_resource(node, 1 + i, &res);
1309                 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1310                 if (ret || !rdist_regs[i].redist_base) {
1311                         pr_err("%pOF: couldn't map region %d\n", node, i);
1312                         err = -ENODEV;
1313                         goto out_unmap_rdist;
1314                 }
1315                 rdist_regs[i].phys_base = res.start;
1316         }
1317
1318         if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1319                 redist_stride = 0;
1320
1321         err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1322                              redist_stride, &node->fwnode);
1323         if (err)
1324                 goto out_unmap_rdist;
1325
1326         gic_populate_ppi_partitions(node);
1327
1328         if (static_branch_likely(&supports_deactivate_key))
1329                 gic_of_setup_kvm_info(node);
1330         return 0;
1331
1332 out_unmap_rdist:
1333         for (i = 0; i < nr_redist_regions; i++)
1334                 if (rdist_regs[i].redist_base)
1335                         iounmap(rdist_regs[i].redist_base);
1336         kfree(rdist_regs);
1337 out_unmap_dist:
1338         iounmap(dist_base);
1339         return err;
1340 }
1341
1342 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1343
1344 #ifdef CONFIG_ACPI
1345 static struct
1346 {
1347         void __iomem *dist_base;
1348         struct redist_region *redist_regs;
1349         u32 nr_redist_regions;
1350         bool single_redist;
1351         u32 maint_irq;
1352         int maint_irq_mode;
1353         phys_addr_t vcpu_base;
1354 } acpi_data __initdata;
1355
1356 static void __init
1357 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
1358 {
1359         static int count = 0;
1360
1361         acpi_data.redist_regs[count].phys_base = phys_base;
1362         acpi_data.redist_regs[count].redist_base = redist_base;
1363         acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
1364         count++;
1365 }
1366
1367 static int __init
1368 gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
1369                            const unsigned long end)
1370 {
1371         struct acpi_madt_generic_redistributor *redist =
1372                         (struct acpi_madt_generic_redistributor *)header;
1373         void __iomem *redist_base;
1374
1375         redist_base = ioremap(redist->base_address, redist->length);
1376         if (!redist_base) {
1377                 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
1378                 return -ENOMEM;
1379         }
1380
1381         gic_acpi_register_redist(redist->base_address, redist_base);
1382         return 0;
1383 }
1384
1385 static int __init
1386 gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header,
1387                          const unsigned long end)
1388 {
1389         struct acpi_madt_generic_interrupt *gicc =
1390                                 (struct acpi_madt_generic_interrupt *)header;
1391         u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1392         u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1393         void __iomem *redist_base;
1394
1395         /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
1396         if (!(gicc->flags & ACPI_MADT_ENABLED))
1397                 return 0;
1398
1399         redist_base = ioremap(gicc->gicr_base_address, size);
1400         if (!redist_base)
1401                 return -ENOMEM;
1402
1403         gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1404         return 0;
1405 }
1406
1407 static int __init gic_acpi_collect_gicr_base(void)
1408 {
1409         acpi_tbl_entry_handler redist_parser;
1410         enum acpi_madt_type type;
1411
1412         if (acpi_data.single_redist) {
1413                 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1414                 redist_parser = gic_acpi_parse_madt_gicc;
1415         } else {
1416                 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1417                 redist_parser = gic_acpi_parse_madt_redist;
1418         }
1419
1420         /* Collect redistributor base addresses in GICR entries */
1421         if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1422                 return 0;
1423
1424         pr_info("No valid GICR entries exist\n");
1425         return -ENODEV;
1426 }
1427
1428 static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header,
1429                                   const unsigned long end)
1430 {
1431         /* Subtable presence means that redist exists, that's it */
1432         return 0;
1433 }
1434
1435 static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
1436                                       const unsigned long end)
1437 {
1438         struct acpi_madt_generic_interrupt *gicc =
1439                                 (struct acpi_madt_generic_interrupt *)header;
1440
1441         /*
1442          * If GICC is enabled and has valid gicr base address, then it means
1443          * GICR base is presented via GICC
1444          */
1445         if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
1446                 return 0;
1447
1448         /*
1449          * It's perfectly valid firmware can pass disabled GICC entry, driver
1450          * should not treat as errors, skip the entry instead of probe fail.
1451          */
1452         if (!(gicc->flags & ACPI_MADT_ENABLED))
1453                 return 0;
1454
1455         return -ENODEV;
1456 }
1457
1458 static int __init gic_acpi_count_gicr_regions(void)
1459 {
1460         int count;
1461
1462         /*
1463          * Count how many redistributor regions we have. It is not allowed
1464          * to mix redistributor description, GICR and GICC subtables have to be
1465          * mutually exclusive.
1466          */
1467         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1468                                       gic_acpi_match_gicr, 0);
1469         if (count > 0) {
1470                 acpi_data.single_redist = false;
1471                 return count;
1472         }
1473
1474         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1475                                       gic_acpi_match_gicc, 0);
1476         if (count > 0)
1477                 acpi_data.single_redist = true;
1478
1479         return count;
1480 }
1481
1482 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
1483                                            struct acpi_probe_entry *ape)
1484 {
1485         struct acpi_madt_generic_distributor *dist;
1486         int count;
1487
1488         dist = (struct acpi_madt_generic_distributor *)header;
1489         if (dist->version != ape->driver_data)
1490                 return false;
1491
1492         /* We need to do that exercise anyway, the sooner the better */
1493         count = gic_acpi_count_gicr_regions();
1494         if (count <= 0)
1495                 return false;
1496
1497         acpi_data.nr_redist_regions = count;
1498         return true;
1499 }
1500
1501 static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header,
1502                                                 const unsigned long end)
1503 {
1504         struct acpi_madt_generic_interrupt *gicc =
1505                 (struct acpi_madt_generic_interrupt *)header;
1506         int maint_irq_mode;
1507         static int first_madt = true;
1508
1509         /* Skip unusable CPUs */
1510         if (!(gicc->flags & ACPI_MADT_ENABLED))
1511                 return 0;
1512
1513         maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1514                 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1515
1516         if (first_madt) {
1517                 first_madt = false;
1518
1519                 acpi_data.maint_irq = gicc->vgic_interrupt;
1520                 acpi_data.maint_irq_mode = maint_irq_mode;
1521                 acpi_data.vcpu_base = gicc->gicv_base_address;
1522
1523                 return 0;
1524         }
1525
1526         /*
1527          * The maintenance interrupt and GICV should be the same for every CPU
1528          */
1529         if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
1530             (acpi_data.maint_irq_mode != maint_irq_mode) ||
1531             (acpi_data.vcpu_base != gicc->gicv_base_address))
1532                 return -EINVAL;
1533
1534         return 0;
1535 }
1536
1537 static bool __init gic_acpi_collect_virt_info(void)
1538 {
1539         int count;
1540
1541         count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1542                                       gic_acpi_parse_virt_madt_gicc, 0);
1543
1544         return (count > 0);
1545 }
1546
1547 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
1548 #define ACPI_GICV2_VCTRL_MEM_SIZE       (SZ_4K)
1549 #define ACPI_GICV2_VCPU_MEM_SIZE        (SZ_8K)
1550
1551 static void __init gic_acpi_setup_kvm_info(void)
1552 {
1553         int irq;
1554
1555         if (!gic_acpi_collect_virt_info()) {
1556                 pr_warn("Unable to get hardware information used for virtualization\n");
1557                 return;
1558         }
1559
1560         gic_v3_kvm_info.type = GIC_V3;
1561
1562         irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1563                                 acpi_data.maint_irq_mode,
1564                                 ACPI_ACTIVE_HIGH);
1565         if (irq <= 0)
1566                 return;
1567
1568         gic_v3_kvm_info.maint_irq = irq;
1569
1570         if (acpi_data.vcpu_base) {
1571                 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
1572
1573                 vcpu->flags = IORESOURCE_MEM;
1574                 vcpu->start = acpi_data.vcpu_base;
1575                 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1576         }
1577
1578         gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1579         gic_set_kvm_info(&gic_v3_kvm_info);
1580 }
1581
1582 static int __init
1583 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
1584 {
1585         struct acpi_madt_generic_distributor *dist;
1586         struct fwnode_handle *domain_handle;
1587         size_t size;
1588         int i, err;
1589
1590         /* Get distributor base address */
1591         dist = (struct acpi_madt_generic_distributor *)header;
1592         acpi_data.dist_base = ioremap(dist->base_address,
1593                                       ACPI_GICV3_DIST_MEM_SIZE);
1594         if (!acpi_data.dist_base) {
1595                 pr_err("Unable to map GICD registers\n");
1596                 return -ENOMEM;
1597         }
1598
1599         err = gic_validate_dist_version(acpi_data.dist_base);
1600         if (err) {
1601                 pr_err("No distributor detected at @%p, giving up\n",
1602                        acpi_data.dist_base);
1603                 goto out_dist_unmap;
1604         }
1605
1606         size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
1607         acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
1608         if (!acpi_data.redist_regs) {
1609                 err = -ENOMEM;
1610                 goto out_dist_unmap;
1611         }
1612
1613         err = gic_acpi_collect_gicr_base();
1614         if (err)
1615                 goto out_redist_unmap;
1616
1617         domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base);
1618         if (!domain_handle) {
1619                 err = -ENOMEM;
1620                 goto out_redist_unmap;
1621         }
1622
1623         err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
1624                              acpi_data.nr_redist_regions, 0, domain_handle);
1625         if (err)
1626                 goto out_fwhandle_free;
1627
1628         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1629
1630         if (static_branch_likely(&supports_deactivate_key))
1631                 gic_acpi_setup_kvm_info();
1632
1633         return 0;
1634
1635 out_fwhandle_free:
1636         irq_domain_free_fwnode(domain_handle);
1637 out_redist_unmap:
1638         for (i = 0; i < acpi_data.nr_redist_regions; i++)
1639                 if (acpi_data.redist_regs[i].redist_base)
1640                         iounmap(acpi_data.redist_regs[i].redist_base);
1641         kfree(acpi_data.redist_regs);
1642 out_dist_unmap:
1643         iounmap(acpi_data.dist_base);
1644         return err;
1645 }
1646 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1647                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
1648                      gic_acpi_init);
1649 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1650                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
1651                      gic_acpi_init);
1652 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1653                      acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
1654                      gic_acpi_init);
1655 #endif