1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #define pr_fmt(fmt) "GICv3: " fmt
9 #include <linux/acpi.h>
10 #include <linux/cpu.h>
11 #include <linux/cpu_pm.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/percpu.h>
19 #include <linux/refcount.h>
20 #include <linux/slab.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
27 #include <asm/cputype.h>
28 #include <asm/exception.h>
29 #include <asm/smp_plat.h>
32 #include "irq-gic-common.h"
34 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
36 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
38 struct redist_region {
39 void __iomem *redist_base;
40 phys_addr_t phys_base;
44 struct gic_chip_data {
45 struct fwnode_handle *fwnode;
46 void __iomem *dist_base;
47 struct redist_region *redist_regions;
49 struct irq_domain *domain;
51 u32 nr_redist_regions;
55 struct partition_desc *ppi_descs[16];
58 static struct gic_chip_data gic_data __read_mostly;
59 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
62 * The behaviours of RPR and PMR registers differ depending on the value of
63 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
64 * distributor and redistributors depends on whether security is enabled in the
67 * When security is enabled, non-secure priority values from the (re)distributor
68 * are presented to the GIC CPUIF as follow:
69 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
71 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
72 * EL1 are subject to a similar operation thus matching the priorities presented
73 * from the (re)distributor when security is enabled.
75 * see GICv3/GICv4 Architecture Specification (IHI0069D):
76 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
78 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
81 * For now, we only support pseudo-NMIs if we have non-secure view of
84 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
86 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
87 static refcount_t ppi_nmi_refs[16];
89 static struct gic_kvm_info gic_v3_kvm_info;
90 static DEFINE_PER_CPU(bool, has_rss);
92 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
93 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
94 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
95 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
97 /* Our default, arbitrary priority value. Linux only uses one anyway. */
98 #define DEFAULT_PMR_VALUE 0xf0
100 static inline unsigned int gic_irq(struct irq_data *d)
105 static inline int gic_irq_in_rdist(struct irq_data *d)
107 return gic_irq(d) < 32;
110 static inline void __iomem *gic_dist_base(struct irq_data *d)
112 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */
113 return gic_data_rdist_sgi_base();
115 if (d->hwirq <= 1023) /* SPI -> dist_base */
116 return gic_data.dist_base;
121 static void gic_do_wait_for_rwp(void __iomem *base)
123 u32 count = 1000000; /* 1s! */
125 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
128 pr_err_ratelimited("RWP timeout, gone fishing\n");
136 /* Wait for completion of a distributor change */
137 static void gic_dist_wait_for_rwp(void)
139 gic_do_wait_for_rwp(gic_data.dist_base);
142 /* Wait for completion of a redistributor change */
143 static void gic_redist_wait_for_rwp(void)
145 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
150 static u64 __maybe_unused gic_read_iar(void)
152 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
153 return gic_read_iar_cavium_thunderx();
155 return gic_read_iar_common();
159 static void gic_enable_redist(bool enable)
162 u32 count = 1000000; /* 1s! */
165 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
168 rbase = gic_data_rdist_rd_base();
170 val = readl_relaxed(rbase + GICR_WAKER);
172 /* Wake up this CPU redistributor */
173 val &= ~GICR_WAKER_ProcessorSleep;
175 val |= GICR_WAKER_ProcessorSleep;
176 writel_relaxed(val, rbase + GICR_WAKER);
178 if (!enable) { /* Check that GICR_WAKER is writeable */
179 val = readl_relaxed(rbase + GICR_WAKER);
180 if (!(val & GICR_WAKER_ProcessorSleep))
181 return; /* No PM support in this redistributor */
185 val = readl_relaxed(rbase + GICR_WAKER);
186 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
192 pr_err_ratelimited("redistributor failed to %s...\n",
193 enable ? "wakeup" : "sleep");
197 * Routines to disable, enable, EOI and route interrupts
199 static int gic_peek_irq(struct irq_data *d, u32 offset)
201 u32 mask = 1 << (gic_irq(d) % 32);
204 if (gic_irq_in_rdist(d))
205 base = gic_data_rdist_sgi_base();
207 base = gic_data.dist_base;
209 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask);
212 static void gic_poke_irq(struct irq_data *d, u32 offset)
214 u32 mask = 1 << (gic_irq(d) % 32);
215 void (*rwp_wait)(void);
218 if (gic_irq_in_rdist(d)) {
219 base = gic_data_rdist_sgi_base();
220 rwp_wait = gic_redist_wait_for_rwp;
222 base = gic_data.dist_base;
223 rwp_wait = gic_dist_wait_for_rwp;
226 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4);
230 static void gic_mask_irq(struct irq_data *d)
232 gic_poke_irq(d, GICD_ICENABLER);
235 static void gic_eoimode1_mask_irq(struct irq_data *d)
239 * When masking a forwarded interrupt, make sure it is
240 * deactivated as well.
242 * This ensures that an interrupt that is getting
243 * disabled/masked will not get "stuck", because there is
244 * noone to deactivate it (guest is being terminated).
246 if (irqd_is_forwarded_to_vcpu(d))
247 gic_poke_irq(d, GICD_ICACTIVER);
250 static void gic_unmask_irq(struct irq_data *d)
252 gic_poke_irq(d, GICD_ISENABLER);
255 static inline bool gic_supports_nmi(void)
257 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
258 static_branch_likely(&supports_pseudo_nmis);
261 static int gic_irq_set_irqchip_state(struct irq_data *d,
262 enum irqchip_irq_state which, bool val)
266 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
270 case IRQCHIP_STATE_PENDING:
271 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
274 case IRQCHIP_STATE_ACTIVE:
275 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
278 case IRQCHIP_STATE_MASKED:
279 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
286 gic_poke_irq(d, reg);
290 static int gic_irq_get_irqchip_state(struct irq_data *d,
291 enum irqchip_irq_state which, bool *val)
293 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */
297 case IRQCHIP_STATE_PENDING:
298 *val = gic_peek_irq(d, GICD_ISPENDR);
301 case IRQCHIP_STATE_ACTIVE:
302 *val = gic_peek_irq(d, GICD_ISACTIVER);
305 case IRQCHIP_STATE_MASKED:
306 *val = !gic_peek_irq(d, GICD_ISENABLER);
316 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
318 void __iomem *base = gic_dist_base(d);
320 writeb_relaxed(prio, base + GICD_IPRIORITYR + gic_irq(d));
323 static int gic_irq_nmi_setup(struct irq_data *d)
325 struct irq_desc *desc = irq_to_desc(d->irq);
327 if (!gic_supports_nmi())
330 if (gic_peek_irq(d, GICD_ISENABLER)) {
331 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
336 * A secondary irq_chip should be in charge of LPI request,
337 * it should not be possible to get there
339 if (WARN_ON(gic_irq(d) >= 8192))
342 /* desc lock should already be held */
343 if (gic_irq(d) < 32) {
344 /* Setting up PPI as NMI, only switch handler for first NMI */
345 if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) {
346 refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1);
347 desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
350 desc->handle_irq = handle_fasteoi_nmi;
353 gic_irq_set_prio(d, GICD_INT_NMI_PRI);
358 static void gic_irq_nmi_teardown(struct irq_data *d)
360 struct irq_desc *desc = irq_to_desc(d->irq);
362 if (WARN_ON(!gic_supports_nmi()))
365 if (gic_peek_irq(d, GICD_ISENABLER)) {
366 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
371 * A secondary irq_chip should be in charge of LPI request,
372 * it should not be possible to get there
374 if (WARN_ON(gic_irq(d) >= 8192))
377 /* desc lock should already be held */
378 if (gic_irq(d) < 32) {
379 /* Tearing down NMI, only switch handler for last NMI */
380 if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16]))
381 desc->handle_irq = handle_percpu_devid_irq;
383 desc->handle_irq = handle_fasteoi_irq;
386 gic_irq_set_prio(d, GICD_INT_DEF_PRI);
389 static void gic_eoi_irq(struct irq_data *d)
391 gic_write_eoir(gic_irq(d));
394 static void gic_eoimode1_eoi_irq(struct irq_data *d)
397 * No need to deactivate an LPI, or an interrupt that
398 * is is getting forwarded to a vcpu.
400 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
402 gic_write_dir(gic_irq(d));
405 static int gic_set_type(struct irq_data *d, unsigned int type)
407 unsigned int irq = gic_irq(d);
408 void (*rwp_wait)(void);
411 /* Interrupt configuration for SGIs can't be changed */
415 /* SPIs have restrictions on the supported types */
416 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
417 type != IRQ_TYPE_EDGE_RISING)
420 if (gic_irq_in_rdist(d)) {
421 base = gic_data_rdist_sgi_base();
422 rwp_wait = gic_redist_wait_for_rwp;
424 base = gic_data.dist_base;
425 rwp_wait = gic_dist_wait_for_rwp;
428 return gic_configure_irq(irq, type, base, rwp_wait);
431 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
434 irqd_set_forwarded_to_vcpu(d);
436 irqd_clr_forwarded_to_vcpu(d);
440 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
444 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
445 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
446 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
447 MPIDR_AFFINITY_LEVEL(mpidr, 0));
452 static void gic_deactivate_unhandled(u32 irqnr)
454 if (static_branch_likely(&supports_deactivate_key)) {
456 gic_write_dir(irqnr);
458 gic_write_eoir(irqnr);
462 static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
464 bool irqs_enabled = interrupts_enabled(regs);
470 if (static_branch_likely(&supports_deactivate_key))
471 gic_write_eoir(irqnr);
473 * Leave the PSR.I bit set to prevent other NMIs to be
474 * received while handling this one.
475 * PSR.I will be restored when we ERET to the
476 * interrupted context.
478 err = handle_domain_nmi(gic_data.domain, irqnr, regs);
480 gic_deactivate_unhandled(irqnr);
486 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
490 irqnr = gic_read_iar();
492 if (gic_supports_nmi() &&
493 unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) {
494 gic_handle_nmi(irqnr, regs);
498 if (gic_prio_masking_enabled()) {
500 gic_arch_enable_irqs();
503 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
506 if (static_branch_likely(&supports_deactivate_key))
507 gic_write_eoir(irqnr);
511 err = handle_domain_irq(gic_data.domain, irqnr, regs);
513 WARN_ONCE(true, "Unexpected interrupt received!\n");
514 gic_deactivate_unhandled(irqnr);
519 gic_write_eoir(irqnr);
520 if (static_branch_likely(&supports_deactivate_key))
521 gic_write_dir(irqnr);
524 * Unlike GICv2, we don't need an smp_rmb() here.
525 * The control dependency from gic_read_iar to
526 * the ISB in gic_write_eoir is enough to ensure
527 * that any shared data read by handle_IPI will
528 * be read after the ACK.
530 handle_IPI(irqnr, regs);
532 WARN_ONCE(true, "Unexpected SGI received!\n");
537 static u32 gic_get_pribits(void)
541 pribits = gic_read_ctlr();
542 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
543 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
549 static bool gic_has_group0(void)
554 old_pmr = gic_read_pmr();
557 * Let's find out if Group0 is under control of EL3 or not by
558 * setting the highest possible, non-zero priority in PMR.
560 * If SCR_EL3.FIQ is set, the priority gets shifted down in
561 * order for the CPU interface to set bit 7, and keep the
562 * actual priority in the non-secure range. In the process, it
563 * looses the least significant bit and the actual priority
564 * becomes 0x80. Reading it back returns 0, indicating that
565 * we're don't have access to Group0.
567 gic_write_pmr(BIT(8 - gic_get_pribits()));
568 val = gic_read_pmr();
570 gic_write_pmr(old_pmr);
575 static void __init gic_dist_init(void)
579 void __iomem *base = gic_data.dist_base;
581 /* Disable the distributor */
582 writel_relaxed(0, base + GICD_CTLR);
583 gic_dist_wait_for_rwp();
586 * Configure SPIs as non-secure Group-1. This will only matter
587 * if the GIC only has a single security state. This will not
588 * do the right thing if the kernel is running in secure mode,
589 * but that's not the intended use case anyway.
591 for (i = 32; i < gic_data.irq_nr; i += 32)
592 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
594 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp);
596 /* Enable distributor with ARE, Group1 */
597 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
601 * Set all global interrupts to the boot CPU only. ARE must be
604 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
605 for (i = 32; i < gic_data.irq_nr; i++)
606 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
609 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
614 for (i = 0; i < gic_data.nr_redist_regions; i++) {
615 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
619 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
620 if (reg != GIC_PIDR2_ARCH_GICv3 &&
621 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
622 pr_warn("No redistributor present @%p\n", ptr);
627 typer = gic_read_typer(ptr + GICR_TYPER);
628 ret = fn(gic_data.redist_regions + i, ptr);
632 if (gic_data.redist_regions[i].single_redist)
635 if (gic_data.redist_stride) {
636 ptr += gic_data.redist_stride;
638 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
639 if (typer & GICR_TYPER_VLPIS)
640 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
642 } while (!(typer & GICR_TYPER_LAST));
645 return ret ? -ENODEV : 0;
648 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
650 unsigned long mpidr = cpu_logical_map(smp_processor_id());
655 * Convert affinity to a 32bit value that can be matched to
656 * GICR_TYPER bits [63:32].
658 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
659 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
660 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
661 MPIDR_AFFINITY_LEVEL(mpidr, 0));
663 typer = gic_read_typer(ptr + GICR_TYPER);
664 if ((typer >> 32) == aff) {
665 u64 offset = ptr - region->redist_base;
666 gic_data_rdist_rd_base() = ptr;
667 gic_data_rdist()->phys_base = region->phys_base + offset;
669 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
670 smp_processor_id(), mpidr,
671 (int)(region - gic_data.redist_regions),
672 &gic_data_rdist()->phys_base);
680 static int gic_populate_rdist(void)
682 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
685 /* We couldn't even deal with ourselves... */
686 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
688 (unsigned long)cpu_logical_map(smp_processor_id()));
692 static int __gic_update_vlpi_properties(struct redist_region *region,
695 u64 typer = gic_read_typer(ptr + GICR_TYPER);
696 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
697 gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS);
702 static void gic_update_vlpi_properties(void)
704 gic_iterate_rdists(__gic_update_vlpi_properties);
705 pr_info("%sVLPI support, %sdirect LPI support\n",
706 !gic_data.rdists.has_vlpis ? "no " : "",
707 !gic_data.rdists.has_direct_lpi ? "no " : "");
710 /* Check whether it's single security state view */
711 static inline bool gic_dist_security_disabled(void)
713 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
716 static void gic_cpu_sys_reg_init(void)
718 int i, cpu = smp_processor_id();
719 u64 mpidr = cpu_logical_map(cpu);
720 u64 need_rss = MPIDR_RS(mpidr);
725 * Need to check that the SRE bit has actually been set. If
726 * not, it means that SRE is disabled at EL2. We're going to
727 * die painfully, and there is nothing we can do about it.
729 * Kindly inform the luser.
731 if (!gic_enable_sre())
732 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
734 pribits = gic_get_pribits();
736 group0 = gic_has_group0();
738 /* Set priority mask register */
739 if (!gic_prio_masking_enabled()) {
740 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
743 * Mismatch configuration with boot CPU, the system is likely
744 * to die as interrupt masking will not work properly on all
747 WARN_ON(gic_supports_nmi() && group0 &&
748 !gic_dist_security_disabled());
752 * Some firmwares hand over to the kernel with the BPR changed from
753 * its reset value (and with a value large enough to prevent
754 * any pre-emptive interrupts from working at all). Writing a zero
755 * to BPR restores is reset value.
759 if (static_branch_likely(&supports_deactivate_key)) {
760 /* EOI drops priority only (mode 1) */
761 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
763 /* EOI deactivates interrupt too (mode 0) */
764 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
767 /* Always whack Group0 before Group1 */
772 write_gicreg(0, ICC_AP0R3_EL1);
773 write_gicreg(0, ICC_AP0R2_EL1);
775 write_gicreg(0, ICC_AP0R1_EL1);
778 write_gicreg(0, ICC_AP0R0_EL1);
787 write_gicreg(0, ICC_AP1R3_EL1);
788 write_gicreg(0, ICC_AP1R2_EL1);
790 write_gicreg(0, ICC_AP1R1_EL1);
793 write_gicreg(0, ICC_AP1R0_EL1);
798 /* ... and let's hit the road... */
801 /* Keep the RSS capability status in per_cpu variable */
802 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
804 /* Check all the CPUs have capable of sending SGIs to other CPUs */
805 for_each_online_cpu(i) {
806 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
808 need_rss |= MPIDR_RS(cpu_logical_map(i));
809 if (need_rss && (!have_rss))
810 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
811 cpu, (unsigned long)mpidr,
812 i, (unsigned long)cpu_logical_map(i));
816 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
817 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
818 * UNPREDICTABLE choice of :
819 * - The write is ignored.
820 * - The RS field is treated as 0.
822 if (need_rss && (!gic_data.has_rss))
823 pr_crit_once("RSS is required but GICD doesn't support it\n");
826 static bool gicv3_nolpi;
828 static int __init gicv3_nolpi_cfg(char *buf)
830 return strtobool(buf, &gicv3_nolpi);
832 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
834 static int gic_dist_supports_lpis(void)
836 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
837 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
841 static void gic_cpu_init(void)
845 /* Register ourselves with the rest of the world */
846 if (gic_populate_rdist())
849 gic_enable_redist(true);
851 rbase = gic_data_rdist_sgi_base();
853 /* Configure SGIs/PPIs as non-secure Group-1 */
854 writel_relaxed(~0, rbase + GICR_IGROUPR0);
856 gic_cpu_config(rbase, gic_redist_wait_for_rwp);
858 /* initialise system registers */
859 gic_cpu_sys_reg_init();
864 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
865 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
867 static int gic_starting_cpu(unsigned int cpu)
871 if (gic_dist_supports_lpis())
877 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
878 unsigned long cluster_id)
880 int next_cpu, cpu = *base_cpu;
881 unsigned long mpidr = cpu_logical_map(cpu);
884 while (cpu < nr_cpu_ids) {
885 tlist |= 1 << (mpidr & 0xf);
887 next_cpu = cpumask_next(cpu, mask);
888 if (next_cpu >= nr_cpu_ids)
892 mpidr = cpu_logical_map(cpu);
894 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
904 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
905 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
906 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
908 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
912 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
913 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
914 irq << ICC_SGI1R_SGI_ID_SHIFT |
915 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
916 MPIDR_TO_SGI_RS(cluster_id) |
917 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
919 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
920 gic_write_sgi1r(val);
923 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
927 if (WARN_ON(irq >= 16))
931 * Ensure that stores to Normal memory are visible to the
932 * other CPUs before issuing the IPI.
936 for_each_cpu(cpu, mask) {
937 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
940 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
941 gic_send_sgi(cluster_id, tlist, irq);
944 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
948 static void gic_smp_init(void)
950 set_smp_cross_call(gic_raise_softirq);
951 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
952 "irqchip/arm/gicv3:starting",
953 gic_starting_cpu, NULL);
956 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
965 cpu = cpumask_first(mask_val);
967 cpu = cpumask_any_and(mask_val, cpu_online_mask);
969 if (cpu >= nr_cpu_ids)
972 if (gic_irq_in_rdist(d))
975 /* If interrupt was enabled, disable it first */
976 enabled = gic_peek_irq(d, GICD_ISENABLER);
980 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8);
981 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
983 gic_write_irouter(val, reg);
986 * If the interrupt was enabled, enabled it again. Otherwise,
987 * just wait for the distributor to have digested our changes.
992 gic_dist_wait_for_rwp();
994 irq_data_update_effective_affinity(d, cpumask_of(cpu));
996 return IRQ_SET_MASK_OK_DONE;
999 #define gic_set_affinity NULL
1000 #define gic_smp_init() do { } while(0)
1003 #ifdef CONFIG_CPU_PM
1004 static int gic_cpu_pm_notifier(struct notifier_block *self,
1005 unsigned long cmd, void *v)
1007 if (cmd == CPU_PM_EXIT) {
1008 if (gic_dist_security_disabled())
1009 gic_enable_redist(true);
1010 gic_cpu_sys_reg_init();
1011 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1012 gic_write_grpen1(0);
1013 gic_enable_redist(false);
1018 static struct notifier_block gic_cpu_pm_notifier_block = {
1019 .notifier_call = gic_cpu_pm_notifier,
1022 static void gic_cpu_pm_init(void)
1024 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1028 static inline void gic_cpu_pm_init(void) { }
1029 #endif /* CONFIG_CPU_PM */
1031 static struct irq_chip gic_chip = {
1033 .irq_mask = gic_mask_irq,
1034 .irq_unmask = gic_unmask_irq,
1035 .irq_eoi = gic_eoi_irq,
1036 .irq_set_type = gic_set_type,
1037 .irq_set_affinity = gic_set_affinity,
1038 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1039 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1040 .irq_nmi_setup = gic_irq_nmi_setup,
1041 .irq_nmi_teardown = gic_irq_nmi_teardown,
1042 .flags = IRQCHIP_SET_TYPE_MASKED |
1043 IRQCHIP_SKIP_SET_WAKE |
1044 IRQCHIP_MASK_ON_SUSPEND,
1047 static struct irq_chip gic_eoimode1_chip = {
1049 .irq_mask = gic_eoimode1_mask_irq,
1050 .irq_unmask = gic_unmask_irq,
1051 .irq_eoi = gic_eoimode1_eoi_irq,
1052 .irq_set_type = gic_set_type,
1053 .irq_set_affinity = gic_set_affinity,
1054 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1055 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1056 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
1057 .irq_nmi_setup = gic_irq_nmi_setup,
1058 .irq_nmi_teardown = gic_irq_nmi_teardown,
1059 .flags = IRQCHIP_SET_TYPE_MASKED |
1060 IRQCHIP_SKIP_SET_WAKE |
1061 IRQCHIP_MASK_ON_SUSPEND,
1064 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
1066 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1069 struct irq_chip *chip = &gic_chip;
1071 if (static_branch_likely(&supports_deactivate_key))
1072 chip = &gic_eoimode1_chip;
1074 /* SGIs are private to the core kernel */
1078 if (hw >= gic_data.irq_nr && hw < 8192)
1081 if (hw >= GIC_ID_NR)
1086 irq_set_percpu_devid(irq);
1087 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1088 handle_percpu_devid_irq, NULL, NULL);
1089 irq_set_status_flags(irq, IRQ_NOAUTOEN);
1092 if (hw >= 32 && hw < gic_data.irq_nr) {
1093 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1094 handle_fasteoi_irq, NULL, NULL);
1096 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
1099 if (hw >= 8192 && hw < GIC_ID_NR) {
1100 if (!gic_dist_supports_lpis())
1102 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1103 handle_fasteoi_irq, NULL, NULL);
1109 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
1111 static int gic_irq_domain_translate(struct irq_domain *d,
1112 struct irq_fwspec *fwspec,
1113 unsigned long *hwirq,
1116 if (is_of_node(fwspec->fwnode)) {
1117 if (fwspec->param_count < 3)
1120 switch (fwspec->param[0]) {
1122 *hwirq = fwspec->param[1] + 32;
1125 case GIC_IRQ_TYPE_PARTITION:
1126 *hwirq = fwspec->param[1] + 16;
1128 case GIC_IRQ_TYPE_LPI: /* LPI */
1129 *hwirq = fwspec->param[1];
1135 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1138 * Make it clear that broken DTs are... broken.
1139 * Partitionned PPIs are an unfortunate exception.
1141 WARN_ON(*type == IRQ_TYPE_NONE &&
1142 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1146 if (is_fwnode_irqchip(fwspec->fwnode)) {
1147 if(fwspec->param_count != 2)
1150 *hwirq = fwspec->param[0];
1151 *type = fwspec->param[1];
1153 WARN_ON(*type == IRQ_TYPE_NONE);
1160 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1161 unsigned int nr_irqs, void *arg)
1164 irq_hw_number_t hwirq;
1165 unsigned int type = IRQ_TYPE_NONE;
1166 struct irq_fwspec *fwspec = arg;
1168 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1172 for (i = 0; i < nr_irqs; i++) {
1173 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1181 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1182 unsigned int nr_irqs)
1186 for (i = 0; i < nr_irqs; i++) {
1187 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1188 irq_set_handler(virq + i, NULL);
1189 irq_domain_reset_irq_data(d);
1193 static int gic_irq_domain_select(struct irq_domain *d,
1194 struct irq_fwspec *fwspec,
1195 enum irq_domain_bus_token bus_token)
1198 if (fwspec->fwnode != d->fwnode)
1201 /* If this is not DT, then we have a single domain */
1202 if (!is_of_node(fwspec->fwnode))
1206 * If this is a PPI and we have a 4th (non-null) parameter,
1207 * then we need to match the partition domain.
1209 if (fwspec->param_count >= 4 &&
1210 fwspec->param[0] == 1 && fwspec->param[3] != 0)
1211 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1213 return d == gic_data.domain;
1216 static const struct irq_domain_ops gic_irq_domain_ops = {
1217 .translate = gic_irq_domain_translate,
1218 .alloc = gic_irq_domain_alloc,
1219 .free = gic_irq_domain_free,
1220 .select = gic_irq_domain_select,
1223 static int partition_domain_translate(struct irq_domain *d,
1224 struct irq_fwspec *fwspec,
1225 unsigned long *hwirq,
1228 struct device_node *np;
1231 np = of_find_node_by_phandle(fwspec->param[3]);
1235 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1236 of_node_to_fwnode(np));
1241 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1246 static const struct irq_domain_ops partition_domain_ops = {
1247 .translate = partition_domain_translate,
1248 .select = gic_irq_domain_select,
1251 static bool gic_enable_quirk_msm8996(void *data)
1253 struct gic_chip_data *d = data;
1255 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1260 static void gic_enable_nmi_support(void)
1264 for (i = 0; i < 16; i++)
1265 refcount_set(&ppi_nmi_refs[i], 0);
1267 static_branch_enable(&supports_pseudo_nmis);
1269 if (static_branch_likely(&supports_deactivate_key))
1270 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1272 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1275 static int __init gic_init_bases(void __iomem *dist_base,
1276 struct redist_region *rdist_regs,
1277 u32 nr_redist_regions,
1279 struct fwnode_handle *handle)
1285 if (!is_hyp_mode_available())
1286 static_branch_disable(&supports_deactivate_key);
1288 if (static_branch_likely(&supports_deactivate_key))
1289 pr_info("GIC: Using split EOI/Deactivate mode\n");
1291 gic_data.fwnode = handle;
1292 gic_data.dist_base = dist_base;
1293 gic_data.redist_regions = rdist_regs;
1294 gic_data.nr_redist_regions = nr_redist_regions;
1295 gic_data.redist_stride = redist_stride;
1298 * Find out how many interrupts are supported.
1299 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
1301 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1302 gic_data.rdists.gicd_typer = typer;
1303 gic_irqs = GICD_TYPER_IRQS(typer);
1304 if (gic_irqs > 1020)
1306 gic_data.irq_nr = gic_irqs;
1308 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1310 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1311 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1312 gic_data.rdists.has_vlpis = true;
1313 gic_data.rdists.has_direct_lpi = true;
1315 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1320 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1321 pr_info("Distributor has %sRange Selector support\n",
1322 gic_data.has_rss ? "" : "no ");
1324 if (typer & GICD_TYPER_MBIS) {
1325 err = mbi_init(handle, gic_data.domain);
1327 pr_err("Failed to initialize MBIs\n");
1330 set_handle_irq(gic_handle_irq);
1332 gic_update_vlpi_properties();
1339 if (gic_dist_supports_lpis()) {
1340 its_init(handle, &gic_data.rdists, gic_data.domain);
1343 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1344 gicv2m_init(handle, gic_data.domain);
1347 if (gic_prio_masking_enabled()) {
1348 if (!gic_has_group0() || gic_dist_security_disabled())
1349 gic_enable_nmi_support();
1351 pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
1357 if (gic_data.domain)
1358 irq_domain_remove(gic_data.domain);
1359 free_percpu(gic_data.rdists.rdist);
1363 static int __init gic_validate_dist_version(void __iomem *dist_base)
1365 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1367 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1373 /* Create all possible partitions at boot time */
1374 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1376 struct device_node *parts_node, *child_part;
1377 int part_idx = 0, i;
1379 struct partition_affinity *parts;
1381 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1385 nr_parts = of_get_child_count(parts_node);
1390 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1391 if (WARN_ON(!parts))
1394 for_each_child_of_node(parts_node, child_part) {
1395 struct partition_affinity *part;
1398 part = &parts[part_idx];
1400 part->partition_id = of_node_to_fwnode(child_part);
1402 pr_info("GIC: PPI partition %pOFn[%d] { ",
1403 child_part, part_idx);
1405 n = of_property_count_elems_of_size(child_part, "affinity",
1409 for (i = 0; i < n; i++) {
1412 struct device_node *cpu_node;
1414 err = of_property_read_u32_index(child_part, "affinity",
1419 cpu_node = of_find_node_by_phandle(cpu_phandle);
1420 if (WARN_ON(!cpu_node))
1423 cpu = of_cpu_node_to_id(cpu_node);
1424 if (WARN_ON(cpu < 0))
1427 pr_cont("%pOF[%d] ", cpu_node, cpu);
1429 cpumask_set_cpu(cpu, &part->mask);
1436 for (i = 0; i < 16; i++) {
1438 struct partition_desc *desc;
1439 struct irq_fwspec ppi_fwspec = {
1440 .fwnode = gic_data.fwnode,
1443 [0] = GIC_IRQ_TYPE_PARTITION,
1445 [2] = IRQ_TYPE_NONE,
1449 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1452 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1453 irq, &partition_domain_ops);
1457 gic_data.ppi_descs[i] = desc;
1461 of_node_put(parts_node);
1464 static void __init gic_of_setup_kvm_info(struct device_node *node)
1470 gic_v3_kvm_info.type = GIC_V3;
1472 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1473 if (!gic_v3_kvm_info.maint_irq)
1476 if (of_property_read_u32(node, "#redistributor-regions",
1480 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
1481 ret = of_address_to_resource(node, gicv_idx, &r);
1483 gic_v3_kvm_info.vcpu = r;
1485 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1486 gic_set_kvm_info(&gic_v3_kvm_info);
1489 static const struct gic_quirk gic_quirks[] = {
1491 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1492 .compatible = "qcom,msm8996-gic-v3",
1493 .init = gic_enable_quirk_msm8996,
1499 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1501 void __iomem *dist_base;
1502 struct redist_region *rdist_regs;
1504 u32 nr_redist_regions;
1507 dist_base = of_iomap(node, 0);
1509 pr_err("%pOF: unable to map gic dist registers\n", node);
1513 err = gic_validate_dist_version(dist_base);
1515 pr_err("%pOF: no distributor detected, giving up\n", node);
1516 goto out_unmap_dist;
1519 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1520 nr_redist_regions = 1;
1522 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1526 goto out_unmap_dist;
1529 for (i = 0; i < nr_redist_regions; i++) {
1530 struct resource res;
1533 ret = of_address_to_resource(node, 1 + i, &res);
1534 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1535 if (ret || !rdist_regs[i].redist_base) {
1536 pr_err("%pOF: couldn't map region %d\n", node, i);
1538 goto out_unmap_rdist;
1540 rdist_regs[i].phys_base = res.start;
1543 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1546 gic_enable_of_quirks(node, gic_quirks, &gic_data);
1548 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1549 redist_stride, &node->fwnode);
1551 goto out_unmap_rdist;
1553 gic_populate_ppi_partitions(node);
1555 if (static_branch_likely(&supports_deactivate_key))
1556 gic_of_setup_kvm_info(node);
1560 for (i = 0; i < nr_redist_regions; i++)
1561 if (rdist_regs[i].redist_base)
1562 iounmap(rdist_regs[i].redist_base);
1569 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1574 void __iomem *dist_base;
1575 struct redist_region *redist_regs;
1576 u32 nr_redist_regions;
1580 phys_addr_t vcpu_base;
1581 } acpi_data __initdata;
1584 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
1586 static int count = 0;
1588 acpi_data.redist_regs[count].phys_base = phys_base;
1589 acpi_data.redist_regs[count].redist_base = redist_base;
1590 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
1595 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
1596 const unsigned long end)
1598 struct acpi_madt_generic_redistributor *redist =
1599 (struct acpi_madt_generic_redistributor *)header;
1600 void __iomem *redist_base;
1602 redist_base = ioremap(redist->base_address, redist->length);
1604 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
1608 gic_acpi_register_redist(redist->base_address, redist_base);
1613 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
1614 const unsigned long end)
1616 struct acpi_madt_generic_interrupt *gicc =
1617 (struct acpi_madt_generic_interrupt *)header;
1618 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1619 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1620 void __iomem *redist_base;
1622 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
1623 if (!(gicc->flags & ACPI_MADT_ENABLED))
1626 redist_base = ioremap(gicc->gicr_base_address, size);
1630 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1634 static int __init gic_acpi_collect_gicr_base(void)
1636 acpi_tbl_entry_handler redist_parser;
1637 enum acpi_madt_type type;
1639 if (acpi_data.single_redist) {
1640 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1641 redist_parser = gic_acpi_parse_madt_gicc;
1643 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1644 redist_parser = gic_acpi_parse_madt_redist;
1647 /* Collect redistributor base addresses in GICR entries */
1648 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1651 pr_info("No valid GICR entries exist\n");
1655 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
1656 const unsigned long end)
1658 /* Subtable presence means that redist exists, that's it */
1662 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
1663 const unsigned long end)
1665 struct acpi_madt_generic_interrupt *gicc =
1666 (struct acpi_madt_generic_interrupt *)header;
1669 * If GICC is enabled and has valid gicr base address, then it means
1670 * GICR base is presented via GICC
1672 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
1676 * It's perfectly valid firmware can pass disabled GICC entry, driver
1677 * should not treat as errors, skip the entry instead of probe fail.
1679 if (!(gicc->flags & ACPI_MADT_ENABLED))
1685 static int __init gic_acpi_count_gicr_regions(void)
1690 * Count how many redistributor regions we have. It is not allowed
1691 * to mix redistributor description, GICR and GICC subtables have to be
1692 * mutually exclusive.
1694 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1695 gic_acpi_match_gicr, 0);
1697 acpi_data.single_redist = false;
1701 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1702 gic_acpi_match_gicc, 0);
1704 acpi_data.single_redist = true;
1709 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
1710 struct acpi_probe_entry *ape)
1712 struct acpi_madt_generic_distributor *dist;
1715 dist = (struct acpi_madt_generic_distributor *)header;
1716 if (dist->version != ape->driver_data)
1719 /* We need to do that exercise anyway, the sooner the better */
1720 count = gic_acpi_count_gicr_regions();
1724 acpi_data.nr_redist_regions = count;
1728 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
1729 const unsigned long end)
1731 struct acpi_madt_generic_interrupt *gicc =
1732 (struct acpi_madt_generic_interrupt *)header;
1734 static int first_madt = true;
1736 /* Skip unusable CPUs */
1737 if (!(gicc->flags & ACPI_MADT_ENABLED))
1740 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1741 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1746 acpi_data.maint_irq = gicc->vgic_interrupt;
1747 acpi_data.maint_irq_mode = maint_irq_mode;
1748 acpi_data.vcpu_base = gicc->gicv_base_address;
1754 * The maintenance interrupt and GICV should be the same for every CPU
1756 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
1757 (acpi_data.maint_irq_mode != maint_irq_mode) ||
1758 (acpi_data.vcpu_base != gicc->gicv_base_address))
1764 static bool __init gic_acpi_collect_virt_info(void)
1768 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1769 gic_acpi_parse_virt_madt_gicc, 0);
1774 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
1775 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1776 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1778 static void __init gic_acpi_setup_kvm_info(void)
1782 if (!gic_acpi_collect_virt_info()) {
1783 pr_warn("Unable to get hardware information used for virtualization\n");
1787 gic_v3_kvm_info.type = GIC_V3;
1789 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1790 acpi_data.maint_irq_mode,
1795 gic_v3_kvm_info.maint_irq = irq;
1797 if (acpi_data.vcpu_base) {
1798 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
1800 vcpu->flags = IORESOURCE_MEM;
1801 vcpu->start = acpi_data.vcpu_base;
1802 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1805 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
1806 gic_set_kvm_info(&gic_v3_kvm_info);
1810 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
1812 struct acpi_madt_generic_distributor *dist;
1813 struct fwnode_handle *domain_handle;
1817 /* Get distributor base address */
1818 dist = (struct acpi_madt_generic_distributor *)header;
1819 acpi_data.dist_base = ioremap(dist->base_address,
1820 ACPI_GICV3_DIST_MEM_SIZE);
1821 if (!acpi_data.dist_base) {
1822 pr_err("Unable to map GICD registers\n");
1826 err = gic_validate_dist_version(acpi_data.dist_base);
1828 pr_err("No distributor detected at @%p, giving up\n",
1829 acpi_data.dist_base);
1830 goto out_dist_unmap;
1833 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
1834 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
1835 if (!acpi_data.redist_regs) {
1837 goto out_dist_unmap;
1840 err = gic_acpi_collect_gicr_base();
1842 goto out_redist_unmap;
1844 domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base);
1845 if (!domain_handle) {
1847 goto out_redist_unmap;
1850 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
1851 acpi_data.nr_redist_regions, 0, domain_handle);
1853 goto out_fwhandle_free;
1855 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1857 if (static_branch_likely(&supports_deactivate_key))
1858 gic_acpi_setup_kvm_info();
1863 irq_domain_free_fwnode(domain_handle);
1865 for (i = 0; i < acpi_data.nr_redist_regions; i++)
1866 if (acpi_data.redist_regs[i].redist_base)
1867 iounmap(acpi_data.redist_regs[i].redist_base);
1868 kfree(acpi_data.redist_regs);
1870 iounmap(acpi_data.dist_base);
1873 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1874 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
1876 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1877 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
1879 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1880 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,