2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/of_address.h>
10 #include <linux/of_irq.h>
11 #include <linux/slab.h>
12 #include <linux/irqchip.h>
13 #include <linux/syscore_ops.h>
16 #define GPC_MAX_IRQS (IMR_NUM * 32)
18 #define GPC_IMR1_CORE0 0x30
19 #define GPC_IMR1_CORE1 0x40
20 #define GPC_IMR1_CORE2 0x1c0
21 #define GPC_IMR1_CORE3 0x1d0
24 struct gpcv2_irqchip_data {
25 struct raw_spinlock rlock;
26 void __iomem *gpc_base;
27 u32 wakeup_sources[IMR_NUM];
28 u32 saved_irq_mask[IMR_NUM];
32 static struct gpcv2_irqchip_data *imx_gpcv2_instance;
34 static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
36 return cd->gpc_base + cd->cpu2wakeup + i * 4;
39 static int gpcv2_wakeup_source_save(void)
41 struct gpcv2_irqchip_data *cd;
45 cd = imx_gpcv2_instance;
49 for (i = 0; i < IMR_NUM; i++) {
50 reg = gpcv2_idx_to_reg(cd, i);
51 cd->saved_irq_mask[i] = readl_relaxed(reg);
52 writel_relaxed(cd->wakeup_sources[i], reg);
58 static void gpcv2_wakeup_source_restore(void)
60 struct gpcv2_irqchip_data *cd;
63 cd = imx_gpcv2_instance;
67 for (i = 0; i < IMR_NUM; i++)
68 writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
71 static struct syscore_ops imx_gpcv2_syscore_ops = {
72 .suspend = gpcv2_wakeup_source_save,
73 .resume = gpcv2_wakeup_source_restore,
76 static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
78 struct gpcv2_irqchip_data *cd = d->chip_data;
79 unsigned int idx = d->hwirq / 32;
83 raw_spin_lock_irqsave(&cd->rlock, flags);
84 mask = BIT(d->hwirq % 32);
85 val = cd->wakeup_sources[idx];
87 cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
88 raw_spin_unlock_irqrestore(&cd->rlock, flags);
91 * Do *not* call into the parent, as the GIC doesn't have any
98 static void imx_gpcv2_irq_unmask(struct irq_data *d)
100 struct gpcv2_irqchip_data *cd = d->chip_data;
104 raw_spin_lock(&cd->rlock);
105 reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
106 val = readl_relaxed(reg);
107 val &= ~BIT(d->hwirq % 32);
108 writel_relaxed(val, reg);
109 raw_spin_unlock(&cd->rlock);
111 irq_chip_unmask_parent(d);
114 static void imx_gpcv2_irq_mask(struct irq_data *d)
116 struct gpcv2_irqchip_data *cd = d->chip_data;
120 raw_spin_lock(&cd->rlock);
121 reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
122 val = readl_relaxed(reg);
123 val |= BIT(d->hwirq % 32);
124 writel_relaxed(val, reg);
125 raw_spin_unlock(&cd->rlock);
127 irq_chip_mask_parent(d);
130 static struct irq_chip gpcv2_irqchip_data_chip = {
132 .irq_eoi = irq_chip_eoi_parent,
133 .irq_mask = imx_gpcv2_irq_mask,
134 .irq_unmask = imx_gpcv2_irq_unmask,
135 .irq_set_wake = imx_gpcv2_irq_set_wake,
136 .irq_retrigger = irq_chip_retrigger_hierarchy,
138 .irq_set_affinity = irq_chip_set_affinity_parent,
142 static int imx_gpcv2_domain_translate(struct irq_domain *d,
143 struct irq_fwspec *fwspec,
144 unsigned long *hwirq,
147 if (is_of_node(fwspec->fwnode)) {
148 if (fwspec->param_count != 3)
151 /* No PPI should point to this domain */
152 if (fwspec->param[0] != 0)
155 *hwirq = fwspec->param[1];
156 *type = fwspec->param[2];
163 static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
164 unsigned int irq, unsigned int nr_irqs,
167 struct irq_fwspec *fwspec = data;
168 struct irq_fwspec parent_fwspec;
169 irq_hw_number_t hwirq;
174 err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq, &type);
178 if (hwirq >= GPC_MAX_IRQS)
181 for (i = 0; i < nr_irqs; i++) {
182 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
183 &gpcv2_irqchip_data_chip, domain->host_data);
186 parent_fwspec = *fwspec;
187 parent_fwspec.fwnode = domain->parent->fwnode;
188 return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
192 static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
193 .translate = imx_gpcv2_domain_translate,
194 .alloc = imx_gpcv2_domain_alloc,
195 .free = irq_domain_free_irqs_common,
198 static const struct of_device_id gpcv2_of_match[] = {
199 { .compatible = "fsl,imx7d-gpc", .data = (const void *) 2 },
200 { .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
204 static int __init imx_gpcv2_irqchip_init(struct device_node *node,
205 struct device_node *parent)
207 struct irq_domain *parent_domain, *domain;
208 struct gpcv2_irqchip_data *cd;
209 const struct of_device_id *id;
210 unsigned long core_num;
214 pr_err("%pOF: no parent, giving up\n", node);
218 id = of_match_node(gpcv2_of_match, node);
220 pr_err("%pOF: unknown compatibility string\n", node);
224 core_num = (unsigned long)id->data;
226 parent_domain = irq_find_host(parent);
227 if (!parent_domain) {
228 pr_err("%pOF: unable to get parent domain\n", node);
232 cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
234 pr_err("%pOF: kzalloc failed!\n", node);
238 raw_spin_lock_init(&cd->rlock);
240 cd->gpc_base = of_iomap(node, 0);
242 pr_err("%pOF: unable to map gpc registers\n", node);
247 domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
248 node, &gpcv2_irqchip_data_domain_ops, cd);
250 iounmap(cd->gpc_base);
254 irq_set_default_host(domain);
256 /* Initially mask all interrupts */
257 for (i = 0; i < IMR_NUM; i++) {
258 void __iomem *reg = cd->gpc_base + i * 4;
262 writel_relaxed(~0, reg + GPC_IMR1_CORE2);
263 writel_relaxed(~0, reg + GPC_IMR1_CORE3);
266 writel_relaxed(~0, reg + GPC_IMR1_CORE0);
267 writel_relaxed(~0, reg + GPC_IMR1_CORE1);
269 cd->wakeup_sources[i] = ~0;
272 /* Let CORE0 as the default CPU to wake up by GPC */
273 cd->cpu2wakeup = GPC_IMR1_CORE0;
276 * Due to hardware design failure, need to make sure GPR
277 * interrupt(#32) is unmasked during RUN mode to avoid entering
280 writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
282 imx_gpcv2_instance = cd;
283 register_syscore_ops(&imx_gpcv2_syscore_ops);
286 * Clear the OF_POPULATED flag set in of_irq_init so that
287 * later the GPC power domain driver will not be skipped.
289 of_node_clear_flag(node, OF_POPULATED);
293 IRQCHIP_DECLARE(imx_gpcv2_imx7d, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);
294 IRQCHIP_DECLARE(imx_gpcv2_imx8mq, "fsl,imx8mq-gpc", imx_gpcv2_irqchip_init);