1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
4 * Ingenic XBurst platform IRQ support
7 #include <linux/errno.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
12 #include <linux/irqchip.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/timex.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
20 #include <asm/mach-jz4740/irq.h>
22 struct ingenic_intc_data {
24 struct irq_domain *domain;
28 #define JZ_REG_INTC_STATUS 0x00
29 #define JZ_REG_INTC_MASK 0x04
30 #define JZ_REG_INTC_SET_MASK 0x08
31 #define JZ_REG_INTC_CLEAR_MASK 0x0c
32 #define JZ_REG_INTC_PENDING 0x10
33 #define CHIP_SIZE 0x20
35 static irqreturn_t intc_cascade(int irq, void *data)
37 struct ingenic_intc_data *intc = irq_get_handler_data(irq);
38 struct irq_domain *domain = intc->domain;
39 struct irq_chip_generic *gc;
43 for (i = 0; i < intc->num_chips; i++) {
44 gc = irq_get_domain_generic_chip(domain, i * 32);
46 pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING);
51 int bit = __fls(pending);
53 irq = irq_find_mapping(domain, bit + (i * 32));
54 generic_handle_irq(irq);
62 static struct irqaction intc_cascade_action = {
63 .handler = intc_cascade,
64 .name = "SoC intc cascade interrupt",
67 static int __init ingenic_intc_of_init(struct device_node *node,
70 struct ingenic_intc_data *intc;
71 struct irq_chip_generic *gc;
72 struct irq_chip_type *ct;
73 struct irq_domain *domain;
74 int parent_irq, err = 0;
77 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
83 parent_irq = irq_of_parse_and_map(node, 0);
89 err = irq_set_handler_data(parent_irq, intc);
93 intc->num_chips = num_chips;
94 intc->base = of_iomap(node, 0);
100 domain = irq_domain_add_legacy(node, num_chips * 32,
102 &irq_generic_chip_ops, NULL);
108 intc->domain = domain;
110 err = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC",
112 IRQ_NOPROBE | IRQ_LEVEL, 0);
114 goto out_domain_remove;
116 for (i = 0; i < num_chips; i++) {
117 gc = irq_get_domain_generic_chip(domain, i * 32);
119 gc->wake_enabled = IRQ_MSK(32);
120 gc->reg_base = intc->base + (i * CHIP_SIZE);
123 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
124 ct->regs.disable = JZ_REG_INTC_SET_MASK;
125 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
126 ct->chip.irq_mask = irq_gc_mask_disable_reg;
127 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
128 ct->chip.irq_set_wake = irq_gc_set_wake;
129 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
132 irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
135 setup_irq(parent_irq, &intc_cascade_action);
139 irq_domain_remove(domain);
143 irq_dispose_mapping(parent_irq);
150 static int __init intc_1chip_of_init(struct device_node *node,
151 struct device_node *parent)
153 return ingenic_intc_of_init(node, 1);
155 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
156 IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
158 static int __init intc_2chip_of_init(struct device_node *node,
159 struct device_node *parent)
161 return ingenic_intc_of_init(node, 2);
163 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
164 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
165 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);