1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Jerome Brunet <jbrunet@baylibre.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/module.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/irqchip.h>
17 #include <linux/of_address.h>
20 #define MAX_INPUT_MUX 256
22 #define REG_EDGE_POL 0x00
23 #define REG_PIN_03_SEL 0x04
24 #define REG_PIN_47_SEL 0x08
25 #define REG_FILTER_SEL 0x0c
27 #define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + (x)))
28 #define REG_EDGE_POL_EDGE(x) BIT(x)
29 #define REG_EDGE_POL_LOW(x) BIT(16 + (x))
30 #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
31 #define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
33 struct meson_gpio_irq_params {
34 unsigned int nr_hwirq;
37 static const struct meson_gpio_irq_params meson8_params = {
41 static const struct meson_gpio_irq_params meson8b_params = {
45 static const struct meson_gpio_irq_params gxbb_params = {
49 static const struct meson_gpio_irq_params gxl_params = {
53 static const struct meson_gpio_irq_params axg_params = {
57 static const struct of_device_id meson_irq_gpio_matches[] = {
58 { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
59 { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
60 { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
61 { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
62 { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
63 { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
67 struct meson_gpio_irq_controller {
68 unsigned int nr_hwirq;
70 u32 channel_irqs[NUM_CHANNEL];
71 DECLARE_BITMAP(channel_map, NUM_CHANNEL);
75 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
76 unsigned int reg, u32 mask, u32 val)
80 tmp = readl_relaxed(ctl->base + reg);
83 writel_relaxed(tmp, ctl->base + reg);
86 static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel)
88 return (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
92 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
96 unsigned int reg, idx;
98 spin_lock(&ctl->lock);
100 /* Find a free channel */
101 idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
102 if (idx >= NUM_CHANNEL) {
103 spin_unlock(&ctl->lock);
104 pr_err("No channel available\n");
108 /* Mark the channel as used */
109 set_bit(idx, ctl->channel_map);
112 * Setup the mux of the channel to route the signal of the pad
113 * to the appropriate input of the GIC
115 reg = meson_gpio_irq_channel_to_reg(idx);
116 meson_gpio_irq_update_bits(ctl, reg,
117 0xff << REG_PIN_SEL_SHIFT(idx),
118 hwirq << REG_PIN_SEL_SHIFT(idx));
121 * Get the hwirq number assigned to this channel through
122 * a pointer the channel_irq table. The added benifit of this
123 * method is that we can also retrieve the channel index with
124 * it, using the table base.
126 *channel_hwirq = &(ctl->channel_irqs[idx]);
128 spin_unlock(&ctl->lock);
130 pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
131 hwirq, idx, **channel_hwirq);
137 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
140 return channel_hwirq - ctl->channel_irqs;
144 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
149 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
150 clear_bit(idx, ctl->channel_map);
153 static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
160 idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
163 * The controller has a filter block to operate in either LEVEL or
164 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
165 * EDGE_FALLING support (which the GIC does not support), the filter
166 * block is also able to invert the input signal it gets before
167 * providing it to the GIC.
169 type &= IRQ_TYPE_SENSE_MASK;
171 if (type == IRQ_TYPE_EDGE_BOTH)
174 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
175 val |= REG_EDGE_POL_EDGE(idx);
177 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
178 val |= REG_EDGE_POL_LOW(idx);
180 spin_lock(&ctl->lock);
182 meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
183 REG_EDGE_POL_MASK(idx), val);
185 spin_unlock(&ctl->lock);
190 static unsigned int meson_gpio_irq_type_output(unsigned int type)
192 unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
194 type &= ~IRQ_TYPE_SENSE_MASK;
197 * The polarity of the signal provided to the GIC should always
200 if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
201 type |= IRQ_TYPE_LEVEL_HIGH;
202 else if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
203 type |= IRQ_TYPE_EDGE_RISING;
208 static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
210 struct meson_gpio_irq_controller *ctl = data->domain->host_data;
211 u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
214 ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
218 return irq_chip_set_type_parent(data,
219 meson_gpio_irq_type_output(type));
222 static struct irq_chip meson_gpio_irq_chip = {
223 .name = "meson-gpio-irqchip",
224 .irq_mask = irq_chip_mask_parent,
225 .irq_unmask = irq_chip_unmask_parent,
226 .irq_eoi = irq_chip_eoi_parent,
227 .irq_set_type = meson_gpio_irq_set_type,
228 .irq_retrigger = irq_chip_retrigger_hierarchy,
230 .irq_set_affinity = irq_chip_set_affinity_parent,
232 .flags = IRQCHIP_SET_TYPE_MASKED,
235 static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
236 struct irq_fwspec *fwspec,
237 unsigned long *hwirq,
240 if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
241 *hwirq = fwspec->param[0];
242 *type = fwspec->param[1];
249 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
254 struct irq_fwspec fwspec;
256 fwspec.fwnode = domain->parent->fwnode;
257 fwspec.param_count = 3;
258 fwspec.param[0] = 0; /* SPI */
259 fwspec.param[1] = hwirq;
260 fwspec.param[2] = meson_gpio_irq_type_output(type);
262 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
265 static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
267 unsigned int nr_irqs,
270 struct irq_fwspec *fwspec = data;
271 struct meson_gpio_irq_controller *ctl = domain->host_data;
277 if (WARN_ON(nr_irqs != 1))
280 ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
284 ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
288 ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
289 *channel_hwirq, type);
291 pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
292 meson_gpio_irq_release_channel(ctl, channel_hwirq);
296 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
297 &meson_gpio_irq_chip, channel_hwirq);
302 static void meson_gpio_irq_domain_free(struct irq_domain *domain,
304 unsigned int nr_irqs)
306 struct meson_gpio_irq_controller *ctl = domain->host_data;
307 struct irq_data *irq_data;
310 if (WARN_ON(nr_irqs != 1))
313 irq_domain_free_irqs_parent(domain, virq, 1);
315 irq_data = irq_domain_get_irq_data(domain, virq);
316 channel_hwirq = irq_data_get_irq_chip_data(irq_data);
318 meson_gpio_irq_release_channel(ctl, channel_hwirq);
321 static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
322 .alloc = meson_gpio_irq_domain_alloc,
323 .free = meson_gpio_irq_domain_free,
324 .translate = meson_gpio_irq_domain_translate,
327 static int __init meson_gpio_irq_parse_dt(struct device_node *node,
328 struct meson_gpio_irq_controller *ctl)
330 const struct of_device_id *match;
331 const struct meson_gpio_irq_params *params;
334 match = of_match_node(meson_irq_gpio_matches, node);
338 params = match->data;
339 ctl->nr_hwirq = params->nr_hwirq;
341 ret = of_property_read_variable_u32_array(node,
342 "amlogic,channel-interrupts",
347 pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
354 static int __init meson_gpio_irq_of_init(struct device_node *node,
355 struct device_node *parent)
357 struct irq_domain *domain, *parent_domain;
358 struct meson_gpio_irq_controller *ctl;
362 pr_err("missing parent interrupt node\n");
366 parent_domain = irq_find_host(parent);
367 if (!parent_domain) {
368 pr_err("unable to obtain parent domain\n");
372 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
376 spin_lock_init(&ctl->lock);
378 ctl->base = of_iomap(node, 0);
384 ret = meson_gpio_irq_parse_dt(node, ctl);
386 goto free_channel_irqs;
388 domain = irq_domain_create_hierarchy(parent_domain, 0, ctl->nr_hwirq,
389 of_node_to_fwnode(node),
390 &meson_gpio_irq_domain_ops,
393 pr_err("failed to add domain\n");
395 goto free_channel_irqs;
398 pr_info("%d to %d gpio interrupt mux initialized\n",
399 ctl->nr_hwirq, NUM_CHANNEL);
411 IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc",
412 meson_gpio_irq_of_init);