1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 Magnus Damm
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/spinlock.h>
11 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/err.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
21 #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
23 #define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
24 #define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
25 #define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
26 #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
27 /* SYS-CPU vs. RT-CPU */
28 #define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
29 #define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
30 #define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
31 #define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
32 #define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
33 #define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
34 #define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
35 #define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
36 #define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
37 #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
38 /* IRQn Configuration Register */
48 void __iomem *cpu_int_base;
49 struct irqc_irq irq[IRQC_IRQ_MAX];
50 unsigned int number_of_irqs;
51 struct platform_device *pdev;
52 struct irq_chip_generic *gc;
53 struct irq_domain *irq_domain;
57 static struct irqc_priv *irq_data_to_priv(struct irq_data *data)
59 return data->domain->host_data;
62 static void irqc_dbg(struct irqc_irq *i, char *str)
64 dev_dbg(&i->p->pdev->dev, "%s (%d:%d)\n",
65 str, i->requested_irq, i->hw_irq);
68 static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
69 [IRQ_TYPE_LEVEL_LOW] = 0x01,
70 [IRQ_TYPE_LEVEL_HIGH] = 0x02,
71 [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */
72 [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */
73 [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */
76 static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
78 struct irqc_priv *p = irq_data_to_priv(d);
79 int hw_irq = irqd_to_hwirq(d);
80 unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
83 irqc_dbg(&p->irq[hw_irq], "sense");
88 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
91 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
95 static int irqc_irq_set_wake(struct irq_data *d, unsigned int on)
97 struct irqc_priv *p = irq_data_to_priv(d);
98 int hw_irq = irqd_to_hwirq(d);
100 irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
102 atomic_inc(&p->wakeup_path);
104 atomic_dec(&p->wakeup_path);
109 static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
111 struct irqc_irq *i = dev_id;
112 struct irqc_priv *p = i->p;
113 u32 bit = BIT(i->hw_irq);
115 irqc_dbg(i, "demux1");
117 if (ioread32(p->iomem + DETECT_STATUS) & bit) {
118 iowrite32(bit, p->iomem + DETECT_STATUS);
119 irqc_dbg(i, "demux2");
120 generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq));
126 static int irqc_probe(struct platform_device *pdev)
130 struct resource *irq;
131 const char *name = dev_name(&pdev->dev);
135 p = kzalloc(sizeof(*p), GFP_KERNEL);
137 dev_err(&pdev->dev, "failed to allocate driver data\n");
143 platform_set_drvdata(pdev, p);
145 pm_runtime_enable(&pdev->dev);
146 pm_runtime_get_sync(&pdev->dev);
148 /* get hold of manadatory IOMEM */
149 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
151 dev_err(&pdev->dev, "not enough IOMEM resources\n");
156 /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
157 for (k = 0; k < IRQC_IRQ_MAX; k++) {
158 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
163 p->irq[k].hw_irq = k;
164 p->irq[k].requested_irq = irq->start;
167 p->number_of_irqs = k;
168 if (p->number_of_irqs < 1) {
169 dev_err(&pdev->dev, "not enough IRQ resources\n");
174 /* ioremap IOMEM and setup read/write callbacks */
175 p->iomem = ioremap_nocache(io->start, resource_size(io));
177 dev_err(&pdev->dev, "failed to remap IOMEM\n");
182 p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
184 p->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
186 &irq_generic_chip_ops, p);
187 if (!p->irq_domain) {
189 dev_err(&pdev->dev, "cannot initialize irq domain\n");
193 ret = irq_alloc_domain_generic_chips(p->irq_domain, p->number_of_irqs,
194 1, name, handle_level_irq,
195 0, 0, IRQ_GC_INIT_NESTED_LOCK);
197 dev_err(&pdev->dev, "cannot allocate generic chip\n");
201 p->gc = irq_get_domain_generic_chip(p->irq_domain, 0);
202 p->gc->reg_base = p->cpu_int_base;
203 p->gc->chip_types[0].regs.enable = IRQC_EN_SET;
204 p->gc->chip_types[0].regs.disable = IRQC_EN_STS;
205 p->gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
206 p->gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
207 p->gc->chip_types[0].chip.irq_set_type = irqc_irq_set_type;
208 p->gc->chip_types[0].chip.irq_set_wake = irqc_irq_set_wake;
209 p->gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND;
211 /* request interrupts one by one */
212 for (k = 0; k < p->number_of_irqs; k++) {
213 if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
214 0, name, &p->irq[k])) {
215 dev_err(&pdev->dev, "failed to request IRQ\n");
221 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
226 free_irq(p->irq[k].requested_irq, &p->irq[k]);
229 irq_domain_remove(p->irq_domain);
233 pm_runtime_put(&pdev->dev);
234 pm_runtime_disable(&pdev->dev);
240 static int irqc_remove(struct platform_device *pdev)
242 struct irqc_priv *p = platform_get_drvdata(pdev);
245 for (k = 0; k < p->number_of_irqs; k++)
246 free_irq(p->irq[k].requested_irq, &p->irq[k]);
248 irq_domain_remove(p->irq_domain);
250 pm_runtime_put(&pdev->dev);
251 pm_runtime_disable(&pdev->dev);
256 static int __maybe_unused irqc_suspend(struct device *dev)
258 struct irqc_priv *p = dev_get_drvdata(dev);
260 if (atomic_read(&p->wakeup_path))
261 device_set_wakeup_path(dev);
266 static SIMPLE_DEV_PM_OPS(irqc_pm_ops, irqc_suspend, NULL);
268 static const struct of_device_id irqc_dt_ids[] = {
269 { .compatible = "renesas,irqc", },
272 MODULE_DEVICE_TABLE(of, irqc_dt_ids);
274 static struct platform_driver irqc_device_driver = {
276 .remove = irqc_remove,
278 .name = "renesas_irqc",
279 .of_match_table = irqc_dt_ids,
284 static int __init irqc_init(void)
286 return platform_driver_register(&irqc_device_driver);
288 postcore_initcall(irqc_init);
290 static void __exit irqc_exit(void)
292 platform_driver_unregister(&irqc_device_driver);
294 module_exit(irqc_exit);
296 MODULE_AUTHOR("Magnus Damm");
297 MODULE_DESCRIPTION("Renesas IRQC Driver");
298 MODULE_LICENSE("GPL v2");