1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 #include <linux/bitops.h>
9 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/irqchip.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
18 #define IRQS_PER_BANK 32
20 struct stm32_exti_bank {
29 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
38 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
42 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
51 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
60 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
69 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
75 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
77 const struct stm32_exti_bank *stm32_bank = gc->private;
79 return irq_reg_readl(gc, stm32_bank->pr_ofst);
82 static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask)
84 const struct stm32_exti_bank *stm32_bank = gc->private;
86 irq_reg_writel(gc, mask, stm32_bank->pr_ofst);
89 static void stm32_irq_handler(struct irq_desc *desc)
91 struct irq_domain *domain = irq_desc_get_handler_data(desc);
92 struct irq_chip *chip = irq_desc_get_chip(desc);
93 unsigned int virq, nbanks = domain->gc->num_chips;
94 struct irq_chip_generic *gc;
95 const struct stm32_exti_bank *stm32_bank;
96 unsigned long pending;
97 int n, i, irq_base = 0;
99 chained_irq_enter(chip, desc);
101 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
102 gc = irq_get_domain_generic_chip(domain, irq_base);
103 stm32_bank = gc->private;
105 while ((pending = stm32_exti_pending(gc))) {
106 for_each_set_bit(n, &pending, IRQS_PER_BANK) {
107 virq = irq_find_mapping(domain, irq_base + n);
108 generic_handle_irq(virq);
109 stm32_exti_irq_ack(gc, BIT(n));
114 chained_irq_exit(chip, desc);
117 static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
119 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
120 const struct stm32_exti_bank *stm32_bank = gc->private;
121 int pin = data->hwirq % IRQS_PER_BANK;
126 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
127 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
130 case IRQ_TYPE_EDGE_RISING:
134 case IRQ_TYPE_EDGE_FALLING:
138 case IRQ_TYPE_EDGE_BOTH:
147 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
148 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
155 static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
157 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
158 const struct stm32_exti_bank *stm32_bank = gc->private;
159 int pin = data->hwirq % IRQS_PER_BANK;
164 imr = irq_reg_readl(gc, stm32_bank->imr_ofst);
169 irq_reg_writel(gc, imr, stm32_bank->imr_ofst);
176 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
177 unsigned int nr_irqs, void *data)
179 struct irq_chip_generic *gc;
180 struct irq_fwspec *fwspec = data;
181 irq_hw_number_t hwirq;
183 hwirq = fwspec->param[0];
184 gc = irq_get_domain_generic_chip(d, hwirq);
186 irq_map_generic_chip(d, virq, hwirq);
187 irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
188 handle_simple_irq, NULL, NULL);
193 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
194 unsigned int nr_irqs)
196 struct irq_data *data = irq_domain_get_irq_data(d, virq);
198 irq_domain_reset_irq_data(data);
201 struct irq_domain_ops irq_exti_domain_ops = {
202 .map = irq_map_generic_chip,
203 .xlate = irq_domain_xlate_onetwocell,
204 .alloc = stm32_exti_alloc,
205 .free = stm32_exti_free,
209 __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
210 int bank_nr, struct device_node *node)
212 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
213 int nr_irqs, nr_exti, ret, i;
214 struct irq_chip_generic *gc;
215 struct irq_domain *domain;
218 base = of_iomap(node, 0);
220 pr_err("%pOF: Unable to map registers\n", node);
224 domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
225 &irq_exti_domain_ops, NULL);
227 pr_err("%s: Could not register interrupt domain.\n",
233 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
234 handle_edge_irq, clr, 0, 0);
236 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
238 goto out_free_domain;
241 for (i = 0; i < bank_nr; i++) {
242 const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
245 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
248 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
249 gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
250 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
251 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
252 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
253 gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
254 gc->chip_types->regs.ack = stm32_bank->pr_ofst;
255 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
256 gc->private = (void *)stm32_bank;
258 /* Determine number of irqs supported */
259 writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
260 irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
261 nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
264 * This IP has no reset, so after hot reboot we should
265 * clear registers to avoid residue
267 writel_relaxed(0, base + stm32_bank->imr_ofst);
268 writel_relaxed(0, base + stm32_bank->emr_ofst);
269 writel_relaxed(0, base + stm32_bank->rtsr_ofst);
270 writel_relaxed(0, base + stm32_bank->ftsr_ofst);
271 writel_relaxed(~0UL, base + stm32_bank->pr_ofst);
273 pr_info("%s: bank%d, External IRQs available:%#x\n",
274 node->full_name, i, irqs_mask);
277 nr_irqs = of_irq_count(node);
278 for (i = 0; i < nr_irqs; i++) {
279 unsigned int irq = irq_of_parse_and_map(node, i);
281 irq_set_handler_data(irq, domain);
282 irq_set_chained_handler(irq, stm32_irq_handler);
288 irq_domain_remove(domain);
294 static int __init stm32f4_exti_of_init(struct device_node *np,
295 struct device_node *parent)
297 return stm32_exti_init(stm32f4xx_exti_banks,
298 ARRAY_SIZE(stm32f4xx_exti_banks), np);
301 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
303 static int __init stm32h7_exti_of_init(struct device_node *np,
304 struct device_node *parent)
306 return stm32_exti_init(stm32h7xx_exti_banks,
307 ARRAY_SIZE(stm32h7xx_exti_banks), np);
310 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);