1 // SPDX-License-Identifier: GPL-2.0
3 * Device driver for the PMU on 68K-based Apple PowerBooks
5 * The VIA (versatile interface adapter) interfaces to the PMU,
6 * a 6805 microprocessor core whose primary function is to control
7 * battery charging and system power on the PowerBooks.
8 * The PMU also controls the ADB (Apple Desktop Bus) which connects
9 * to the keyboard and mouse, as well as the non-volatile RAM
10 * and the RTC (real time clock) chip.
12 * Adapted for 68K PMU by Joshua M. Thompson
14 * Based largely on the PowerMac PMU code by Paul Mackerras and
17 * Also based on the PMU driver from MkLinux by Apple Computer, Inc.
18 * and the Open Software Foundation, Inc.
22 #include <linux/types.h>
23 #include <linux/errno.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/miscdevice.h>
27 #include <linux/blkdev.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
32 #include <linux/adb.h>
33 #include <linux/pmu.h>
34 #include <linux/cuda.h>
36 #include <asm/macintosh.h>
37 #include <asm/macints.h>
38 #include <asm/mac_via.h>
40 #include <asm/pgtable.h>
42 #include <linux/uaccess.h>
44 /* Misc minor number allocated for /dev/pmu */
47 /* VIA registers - spaced 0x200 bytes apart */
48 #define RS 0x200 /* skip between registers */
49 #define B 0 /* B-side data */
50 #define A RS /* A-side data */
51 #define DIRB (2*RS) /* B-side direction (1=output) */
52 #define DIRA (3*RS) /* A-side direction (1=output) */
53 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
54 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
55 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
56 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
57 #define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */
58 #define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */
59 #define SR (10*RS) /* Shift register */
60 #define ACR (11*RS) /* Auxiliary control register */
61 #define PCR (12*RS) /* Peripheral control register */
62 #define IFR (13*RS) /* Interrupt flag register */
63 #define IER (14*RS) /* Interrupt enable register */
64 #define ANH (15*RS) /* A-side data, no handshake */
66 /* Bits in B data register: both active low */
67 #define TACK 0x02 /* Transfer acknowledge (input) */
68 #define TREQ 0x04 /* Transfer request (output) */
71 #define SR_CTRL 0x1c /* Shift register control bits */
72 #define SR_EXT 0x0c /* Shift on external clock */
73 #define SR_OUT 0x10 /* Shift out if 1 */
75 /* Bits in IFR and IER */
76 #define SR_INT 0x04 /* Shift register full/empty */
77 #define CB1_INT 0x10 /* transition on CB1 input */
79 static enum pmu_state {
87 static struct adb_request *current_req;
88 static struct adb_request *last_req;
89 static struct adb_request *req_awaiting_reply;
90 static unsigned char interrupt_data[32];
91 static unsigned char *reply_ptr;
92 static int data_index;
94 static int adb_int_pending;
95 static int pmu_adb_flags;
96 static int adb_dev_map;
97 static struct adb_request bright_req_1, bright_req_2, bright_req_3;
98 static int pmu_kind = PMU_UNKNOWN;
99 static int pmu_fully_inited;
103 static int pmu_probe(void);
104 static int pmu_init(void);
105 static void pmu_start(void);
106 static irqreturn_t pmu_interrupt(int irq, void *arg);
107 static int pmu_send_request(struct adb_request *req, int sync);
108 static int pmu_autopoll(int devs);
110 static int pmu_reset_bus(void);
112 static int init_pmu(void);
113 static void pmu_start(void);
114 static void send_byte(int x);
115 static void recv_byte(void);
116 static void pmu_done(struct adb_request *req);
117 static void pmu_handle_data(unsigned char *data, int len);
118 static void set_volume(int level);
119 static void pmu_enable_backlight(int on);
120 static void pmu_set_brightness(int level);
122 struct adb_driver via_pmu_driver = {
126 .send_request = pmu_send_request,
127 .autopoll = pmu_autopoll,
129 .reset_bus = pmu_reset_bus,
133 * This table indicates for each PMU opcode:
134 * - the number of data bytes to be sent with the command, or -1
135 * if a length byte should be sent,
136 * - the number of response bytes which the PMU will return, or
137 * -1 if it will send a length byte.
139 static s8 pmu_data_len[256][2] = {
140 /* 0 1 2 3 4 5 6 7 */
141 /*00*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
142 /*08*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
143 /*10*/ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
144 /*18*/ { 0, 1},{ 0, 1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{ 0, 0},
145 /*20*/ {-1, 0},{ 0, 0},{ 2, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},
146 /*28*/ { 0,-1},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{ 0,-1},
147 /*30*/ { 4, 0},{20, 0},{-1, 0},{ 3, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
148 /*38*/ { 0, 4},{ 0,20},{ 2,-1},{ 2, 1},{ 3,-1},{-1,-1},{-1,-1},{ 4, 0},
149 /*40*/ { 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
150 /*48*/ { 0, 1},{ 0, 1},{-1,-1},{ 1, 0},{ 1, 0},{-1,-1},{-1,-1},{-1,-1},
151 /*50*/ { 1, 0},{ 0, 0},{ 2, 0},{ 2, 0},{-1, 0},{ 1, 0},{ 3, 0},{ 1, 0},
152 /*58*/ { 0, 1},{ 1, 0},{ 0, 2},{ 0, 2},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},
153 /*60*/ { 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
154 /*68*/ { 0, 3},{ 0, 3},{ 0, 2},{ 0, 8},{ 0,-1},{ 0,-1},{-1,-1},{-1,-1},
155 /*70*/ { 1, 0},{ 1, 0},{ 1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
156 /*78*/ { 0,-1},{ 0,-1},{-1,-1},{-1,-1},{-1,-1},{ 5, 1},{ 4, 1},{ 4, 1},
157 /*80*/ { 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
158 /*88*/ { 0, 5},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
159 /*90*/ { 1, 0},{ 2, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
160 /*98*/ { 0, 1},{ 0, 1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
161 /*a0*/ { 2, 0},{ 2, 0},{ 2, 0},{ 4, 0},{-1, 0},{ 0, 0},{-1, 0},{-1, 0},
162 /*a8*/ { 1, 1},{ 1, 0},{ 3, 0},{ 2, 0},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
163 /*b0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
164 /*b8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
165 /*c0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
166 /*c8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
167 /*d0*/ { 0, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
168 /*d8*/ { 1, 1},{ 1, 1},{-1,-1},{-1,-1},{ 0, 1},{ 0,-1},{-1,-1},{-1,-1},
169 /*e0*/ {-1, 0},{ 4, 0},{ 0, 1},{-1, 0},{-1, 0},{ 4, 0},{-1, 0},{-1, 0},
170 /*e8*/ { 3,-1},{-1,-1},{ 0, 1},{-1,-1},{ 0,-1},{-1,-1},{-1,-1},{ 0, 0},
171 /*f0*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
172 /*f8*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},
175 int __init find_via_pmu(void)
177 switch (macintosh_config->adb_type) {
179 pmu_kind = PMU_68K_V1;
182 pmu_kind = PMU_68K_V2;
185 pmu_kind = PMU_UNKNOWN;
194 pr_info("adb: PMU 68K driver v0.5 for Unified ADB\n");
199 pmu_kind = PMU_UNKNOWN;
203 static int pmu_probe(void)
205 if (pmu_kind == PMU_UNKNOWN)
210 static int pmu_init(void)
212 if (pmu_kind == PMU_UNKNOWN)
217 static int __init via_pmu_start(void)
219 if (pmu_kind == PMU_UNKNOWN)
222 if (request_irq(IRQ_MAC_ADB_SR, pmu_interrupt, 0, "PMU_SR",
224 pr_err("%s: can't get SR irq\n", __func__);
227 if (request_irq(IRQ_MAC_ADB_CL, pmu_interrupt, 0, "PMU_CL",
229 pr_err("%s: can't get CL irq\n", __func__);
230 free_irq(IRQ_MAC_ADB_SR, pmu_interrupt);
234 pmu_fully_inited = 1;
236 /* Enable backlight */
237 pmu_enable_backlight(1);
242 arch_initcall(via_pmu_start);
244 static int __init init_pmu(void)
247 volatile struct adb_request req;
249 via2[B] |= TREQ; /* negate TREQ */
250 via2[DIRB] = (via2[DIRB] | TREQ) & ~TACK; /* TACK in, TREQ out */
252 pmu_request((struct adb_request *) &req, NULL, 2, PMU_SET_INTR_MASK, PMU_INT_ADB);
254 while (!req.complete) {
256 printk(KERN_ERR "pmu_init: no response from PMU\n");
263 /* ack all pending interrupts */
265 interrupt_data[0] = 1;
266 while (interrupt_data[0] || pmu_state != idle) {
268 printk(KERN_ERR "pmu_init: timed out acking intrs\n");
271 if (pmu_state == idle) {
273 pmu_interrupt(0, NULL);
279 pmu_request((struct adb_request *) &req, NULL, 2, PMU_SET_INTR_MASK,
280 PMU_INT_ADB_AUTO|PMU_INT_SNDBRT|PMU_INT_ADB);
282 while (!req.complete) {
284 printk(KERN_ERR "pmu_init: no response from PMU\n");
291 bright_req_1.complete = 1;
292 bright_req_2.complete = 1;
293 bright_req_3.complete = 1;
304 /* Send an ADB command */
306 pmu_send_request(struct adb_request *req, int sync)
310 if (!pmu_fully_inited)
318 switch (req->data[0]) {
320 for (i = 0; i < req->nbytes - 1; ++i)
321 req->data[i] = req->data[i+1];
323 if (pmu_data_len[req->data[0]][1] != 0) {
324 req->reply[0] = ADB_RET_OK;
328 ret = pmu_queue_request(req);
331 switch (req->data[1]) {
333 if (req->nbytes != 2)
335 req->data[0] = PMU_READ_RTC;
338 req->reply[0] = CUDA_PACKET;
340 req->reply[2] = CUDA_GET_TIME;
341 ret = pmu_queue_request(req);
344 if (req->nbytes != 6)
346 req->data[0] = PMU_SET_RTC;
348 for (i = 1; i <= 4; ++i)
349 req->data[i] = req->data[i+1];
351 req->reply[0] = CUDA_PACKET;
353 req->reply[2] = CUDA_SET_TIME;
354 ret = pmu_queue_request(req);
357 if (req->nbytes != 4)
359 req->data[0] = PMU_READ_NVRAM;
360 req->data[1] = req->data[2];
361 req->data[2] = req->data[3];
364 req->reply[0] = CUDA_PACKET;
366 req->reply[2] = CUDA_GET_PRAM;
367 ret = pmu_queue_request(req);
370 if (req->nbytes != 5)
372 req->data[0] = PMU_WRITE_NVRAM;
373 req->data[1] = req->data[2];
374 req->data[2] = req->data[3];
375 req->data[3] = req->data[4];
378 req->reply[0] = CUDA_PACKET;
380 req->reply[2] = CUDA_SET_PRAM;
381 ret = pmu_queue_request(req);
386 for (i = req->nbytes - 1; i > 1; --i)
387 req->data[i+2] = req->data[i];
388 req->data[3] = req->nbytes - 2;
389 req->data[2] = pmu_adb_flags;
390 /*req->data[1] = req->data[1];*/
391 req->data[0] = PMU_ADB_CMD;
393 req->reply_expected = 1;
395 ret = pmu_queue_request(req);
405 while (!req->complete)
412 /* Enable/disable autopolling */
414 pmu_autopoll(int devs)
416 struct adb_request req;
418 if (!pmu_fully_inited) return -ENXIO;
422 pmu_request(&req, NULL, 5, PMU_ADB_CMD, 0, 0x86,
423 adb_dev_map >> 8, adb_dev_map);
426 pmu_request(&req, NULL, 1, PMU_ADB_POLL_OFF);
429 while (!req.complete)
434 /* Reset the ADB bus */
438 struct adb_request req;
440 int save_autopoll = adb_dev_map;
442 if (!pmu_fully_inited) return -ENXIO;
444 /* anyone got a better idea?? */
449 req.data[0] = PMU_ADB_CMD;
451 req.data[2] = 3; /* ADB_BUSRESET ??? */
455 req.reply_expected = 1;
456 if (pmu_queue_request(&req) != 0)
458 printk(KERN_ERR "pmu_adb_reset_bus: pmu_queue_request failed\n");
461 while (!req.complete)
464 while (!req.complete) {
466 printk(KERN_ERR "pmu_adb_reset_bus (reset): no response from PMU\n");
473 if (save_autopoll != 0)
474 pmu_autopoll(save_autopoll);
479 /* Construct and send a pmu request */
481 pmu_request(struct adb_request *req, void (*done)(struct adb_request *),
487 if (nbytes < 0 || nbytes > 32) {
488 printk(KERN_ERR "pmu_request: bad nbytes (%d)\n", nbytes);
492 req->nbytes = nbytes;
494 va_start(list, nbytes);
495 for (i = 0; i < nbytes; ++i)
496 req->data[i] = va_arg(list, int);
498 if (pmu_data_len[req->data[0]][1] != 0) {
499 req->reply[0] = ADB_RET_OK;
503 req->reply_expected = 0;
504 return pmu_queue_request(req);
508 pmu_queue_request(struct adb_request *req)
513 if (req->nbytes <= 0) {
517 nsend = pmu_data_len[req->data[0]][0];
518 if (nsend >= 0 && req->nbytes != nsend + 1) {
526 local_irq_save(flags);
528 if (current_req != 0) {
529 last_req->next = req;
534 if (pmu_state == idle)
538 local_irq_restore(flags);
545 via1[ACR] |= SR_CTRL;
547 via2[B] &= ~TREQ; /* assert TREQ */
555 via1[ACR] = (via1[ACR] | SR_EXT) & ~SR_OUT;
556 c = via1[SR]; /* resets SR */
564 struct adb_request *req;
566 /* assert pmu_state == idle */
567 /* get the packet to send */
568 local_irq_save(flags);
570 if (req == 0 || pmu_state != idle
571 || (req->reply_expected && req_awaiting_reply))
576 data_len = pmu_data_len[req->data[0]][0];
578 /* set the shift register to shift out and send a byte */
579 send_byte(req->data[0]);
582 local_irq_restore(flags);
590 local_irq_save(flags);
591 if (via1[IFR] & SR_INT) {
593 pmu_interrupt(IRQ_MAC_ADB_SR, NULL);
595 if (via1[IFR] & CB1_INT) {
597 pmu_interrupt(IRQ_MAC_ADB_CL, NULL);
599 local_irq_restore(flags);
603 pmu_interrupt(int irq, void *dev_id)
605 struct adb_request *req;
606 int timeout, bite = 0; /* to prevent compiler warning */
609 printk("pmu_interrupt: irq %d state %d acr %02X, b %02X data_index %d/%d adb_int_pending %d\n",
610 irq, pmu_state, (uint) via1[ACR], (uint) via2[B], data_index, data_len, adb_int_pending);
613 if (irq == IRQ_MAC_ADB_CL) { /* CB1 interrupt */
615 } else if (irq == IRQ_MAC_ADB_SR) { /* SR interrupt */
616 if (via2[B] & TACK) {
617 printk(KERN_DEBUG "PMU: SR_INT but ack still high! (%x)\n", via2[B]);
620 /* if reading grab the byte */
621 if ((via1[ACR] & SR_OUT) == 0) bite = via1[SR];
623 /* reset TREQ and wait for TACK to go high */
626 while (!(via2[B] & TACK)) {
628 printk(KERN_ERR "PMU not responding (!ack)\n");
638 data_len = req->nbytes - 1;
642 if (data_index <= data_len) {
643 send_byte(req->data[data_index++]);
647 data_len = pmu_data_len[req->data[0]][1];
650 current_req = req->next;
651 if (req->reply_expected)
652 req_awaiting_reply = req;
658 reply_ptr = req->reply + req->reply_len;
666 pmu_state = reading_intr;
667 reply_ptr = interrupt_data;
673 if (data_len == -1) {
676 printk(KERN_ERR "PMU: bad reply len %d\n",
679 reply_ptr[data_index++] = bite;
681 if (data_index < data_len) {
686 if (pmu_state == reading_intr) {
687 pmu_handle_data(interrupt_data, data_index);
690 current_req = req->next;
691 req->reply_len += data_index;
699 printk(KERN_ERR "pmu_interrupt: unknown state %d?\n",
704 if (pmu_state == idle) {
705 if (adb_int_pending) {
707 send_byte(PMU_INT_ACK);
709 } else if (current_req) {
715 printk("pmu_interrupt: exit state %d acr %02X, b %02X data_index %d/%d adb_int_pending %d\n",
716 pmu_state, (uint) via1[ACR], (uint) via2[B], data_index, data_len, adb_int_pending);
722 pmu_done(struct adb_request *req)
729 /* Interrupt data could be the result data from an ADB cmd */
731 pmu_handle_data(unsigned char *data, int len)
733 static int show_pmu_ints = 1;
740 if (data[0] & PMU_INT_ADB) {
741 if ((data[0] & PMU_INT_ADB_AUTO) == 0) {
742 struct adb_request *req = req_awaiting_reply;
744 printk(KERN_ERR "PMU: extra ADB reply\n");
747 req_awaiting_reply = NULL;
751 memcpy(req->reply, data + 1, len - 1);
752 req->reply_len = len - 1;
756 adb_input(data+1, len-1, 1);
759 if (data[0] == 0x08 && len == 3) {
760 /* sound/brightness buttons pressed */
761 pmu_set_brightness(data[1] >> 3);
763 } else if (show_pmu_ints
764 && !(data[0] == PMU_INT_TICK && len == 1)) {
766 printk(KERN_DEBUG "pmu intr");
767 for (i = 0; i < len; ++i)
768 printk(" %.2x", data[i]);
774 static int backlight_level = -1;
775 static int backlight_enabled = 0;
777 #define LEVEL_TO_BRIGHT(lev) ((lev) < 1? 0x7f: 0x4a - ((lev) << 1))
780 pmu_enable_backlight(int on)
782 struct adb_request req;
785 /* first call: get current backlight value */
786 if (backlight_level < 0) {
790 pmu_request(&req, NULL, 3, PMU_READ_NVRAM, 0x14, 0xe);
791 while (!req.complete)
793 printk(KERN_DEBUG "pmu: nvram returned bright: %d\n", (int)req.reply[1]);
794 backlight_level = req.reply[1];
797 backlight_enabled = 0;
801 pmu_request(&req, NULL, 2, PMU_BACKLIGHT_BRIGHT,
802 LEVEL_TO_BRIGHT(backlight_level));
803 while (!req.complete)
806 pmu_request(&req, NULL, 2, PMU_POWER_CTRL,
807 PMU_POW_BACKLIGHT | (on ? PMU_POW_ON : PMU_POW_OFF));
808 while (!req.complete)
810 backlight_enabled = on;
814 pmu_set_brightness(int level)
818 backlight_level = level;
819 bright = LEVEL_TO_BRIGHT(level);
820 if (!backlight_enabled)
822 if (bright_req_1.complete)
823 pmu_request(&bright_req_1, NULL, 2, PMU_BACKLIGHT_BRIGHT,
825 if (bright_req_2.complete)
826 pmu_request(&bright_req_2, NULL, 2, PMU_POWER_CTRL,
827 PMU_POW_BACKLIGHT | (bright < 0x7f ? PMU_POW_ON : PMU_POW_OFF));
831 pmu_enable_irled(int on)
833 struct adb_request req;
835 pmu_request(&req, NULL, 2, PMU_POWER_CTRL, PMU_POW_IRLED |
836 (on ? PMU_POW_ON : PMU_POW_OFF));
837 while (!req.complete)
842 set_volume(int level)
849 return (pmu_kind != PMU_UNKNOWN);