1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
7 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/mailbox_controller.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/slab.h>
15 /* Transmit Register */
16 #define IMX_MU_xTRn(x) (0x00 + 4 * (x))
17 /* Receive Register */
18 #define IMX_MU_xRRn(x) (0x10 + 4 * (x))
20 #define IMX_MU_xSR 0x20
21 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
22 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
23 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
24 #define IMX_MU_xSR_BRDIP BIT(9)
26 /* Control Register */
27 #define IMX_MU_xCR 0x24
28 /* General Purpose Interrupt Enable */
29 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
30 /* Receive Interrupt Enable */
31 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
32 /* Transmit Interrupt Enable */
33 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
34 /* General Purpose Interrupt Request */
35 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
37 #define IMX_MU_CHANS 16
38 #define IMX_MU_CHAN_NAME_SIZE 20
40 enum imx_mu_chan_type {
41 IMX_MU_TYPE_TX, /* Tx */
42 IMX_MU_TYPE_RX, /* Rx */
43 IMX_MU_TYPE_TXDB, /* Tx doorbell */
44 IMX_MU_TYPE_RXDB, /* Rx doorbell */
47 struct imx_mu_con_priv {
49 char irq_desc[IMX_MU_CHAN_NAME_SIZE];
50 enum imx_mu_chan_type type;
51 struct mbox_chan *chan;
52 struct tasklet_struct txdb_tasklet;
58 spinlock_t xcr_lock; /* control register lock */
60 struct mbox_controller mbox;
61 struct mbox_chan mbox_chans[IMX_MU_CHANS];
63 struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
70 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
72 return container_of(mbox, struct imx_mu_priv, mbox);
75 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
77 iowrite32(val, priv->base + offs);
80 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
82 return ioread32(priv->base + offs);
85 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
90 spin_lock_irqsave(&priv->xcr_lock, flags);
91 val = imx_mu_read(priv, IMX_MU_xCR);
94 imx_mu_write(priv, val, IMX_MU_xCR);
95 spin_unlock_irqrestore(&priv->xcr_lock, flags);
100 static void imx_mu_txdb_tasklet(unsigned long data)
102 struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
104 mbox_chan_txdone(cp->chan, 0);
107 static irqreturn_t imx_mu_isr(int irq, void *p)
109 struct mbox_chan *chan = p;
110 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
111 struct imx_mu_con_priv *cp = chan->con_priv;
114 ctrl = imx_mu_read(priv, IMX_MU_xCR);
115 val = imx_mu_read(priv, IMX_MU_xSR);
119 val &= IMX_MU_xSR_TEn(cp->idx) &
120 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
123 val &= IMX_MU_xSR_RFn(cp->idx) &
124 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
126 case IMX_MU_TYPE_RXDB:
127 val &= IMX_MU_xSR_GIPn(cp->idx) &
128 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
137 if (val == IMX_MU_xSR_TEn(cp->idx)) {
138 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
139 mbox_chan_txdone(chan, 0);
140 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
141 dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx));
142 mbox_chan_received_data(chan, (void *)&dat);
143 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
144 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR);
145 mbox_chan_received_data(chan, NULL);
147 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
154 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
156 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
157 struct imx_mu_con_priv *cp = chan->con_priv;
162 imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx));
163 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
165 case IMX_MU_TYPE_TXDB:
166 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
167 tasklet_schedule(&cp->txdb_tasklet);
170 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
177 static int imx_mu_startup(struct mbox_chan *chan)
179 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
180 struct imx_mu_con_priv *cp = chan->con_priv;
183 if (cp->type == IMX_MU_TYPE_TXDB) {
184 /* Tx doorbell don't have ACK support */
185 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
190 ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED, cp->irq_desc,
194 "Unable to acquire IRQ %d\n", priv->irq);
200 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
202 case IMX_MU_TYPE_RXDB:
203 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
212 static void imx_mu_shutdown(struct mbox_chan *chan)
214 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
215 struct imx_mu_con_priv *cp = chan->con_priv;
217 if (cp->type == IMX_MU_TYPE_TXDB)
218 tasklet_kill(&cp->txdb_tasklet);
220 imx_mu_xcr_rmw(priv, 0,
221 IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx));
223 free_irq(priv->irq, chan);
226 static const struct mbox_chan_ops imx_mu_ops = {
227 .send_data = imx_mu_send_data,
228 .startup = imx_mu_startup,
229 .shutdown = imx_mu_shutdown,
232 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
233 const struct of_phandle_args *sp)
237 if (sp->args_count != 2) {
238 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
239 return ERR_PTR(-EINVAL);
242 type = sp->args[0]; /* channel type */
243 idx = sp->args[1]; /* index */
244 chan = type * 4 + idx;
246 if (chan >= mbox->num_chans) {
247 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
248 return ERR_PTR(-EINVAL);
251 return &mbox->chans[chan];
254 static void imx_mu_init_generic(struct imx_mu_priv *priv)
259 /* Set default MU configuration */
260 imx_mu_write(priv, 0, IMX_MU_xCR);
263 static int imx_mu_probe(struct platform_device *pdev)
265 struct device *dev = &pdev->dev;
266 struct device_node *np = dev->of_node;
267 struct resource *iomem;
268 struct imx_mu_priv *priv;
272 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
278 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
279 priv->base = devm_ioremap_resource(&pdev->dev, iomem);
280 if (IS_ERR(priv->base))
281 return PTR_ERR(priv->base);
283 priv->irq = platform_get_irq(pdev, 0);
287 priv->clk = devm_clk_get(dev, NULL);
288 if (IS_ERR(priv->clk)) {
289 if (PTR_ERR(priv->clk) != -ENOENT)
290 return PTR_ERR(priv->clk);
295 ret = clk_prepare_enable(priv->clk);
297 dev_err(dev, "Failed to enable clock\n");
301 for (i = 0; i < IMX_MU_CHANS; i++) {
302 struct imx_mu_con_priv *cp = &priv->con_priv[i];
306 cp->chan = &priv->mbox_chans[i];
307 priv->mbox_chans[i].con_priv = cp;
308 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
309 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
312 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
314 spin_lock_init(&priv->xcr_lock);
316 priv->mbox.dev = dev;
317 priv->mbox.ops = &imx_mu_ops;
318 priv->mbox.chans = priv->mbox_chans;
319 priv->mbox.num_chans = IMX_MU_CHANS;
320 priv->mbox.of_xlate = imx_mu_xlate;
321 priv->mbox.txdone_irq = true;
323 platform_set_drvdata(pdev, priv);
325 imx_mu_init_generic(priv);
327 return devm_mbox_controller_register(dev, &priv->mbox);
330 static int imx_mu_remove(struct platform_device *pdev)
332 struct imx_mu_priv *priv = platform_get_drvdata(pdev);
334 clk_disable_unprepare(priv->clk);
339 static const struct of_device_id imx_mu_dt_ids[] = {
340 { .compatible = "fsl,imx6sx-mu" },
343 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
345 static struct platform_driver imx_mu_driver = {
346 .probe = imx_mu_probe,
347 .remove = imx_mu_remove,
350 .of_match_table = imx_mu_dt_ids,
353 module_platform_driver(imx_mu_driver);
355 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
356 MODULE_DESCRIPTION("Message Unit driver for i.MX");
357 MODULE_LICENSE("GPL v2");