1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2018 MediaTek Inc.
5 #include <linux/bitops.h>
7 #include <linux/clk-provider.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/errno.h>
10 #include <linux/interrupt.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/mailbox_controller.h>
16 #include <linux/mailbox/mtk-cmdq-mailbox.h>
17 #include <linux/of_device.h>
19 #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT)
20 #define CMDQ_IRQ_MASK 0xffff
21 #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
23 #define CMDQ_CURR_IRQ_STATUS 0x10
24 #define CMDQ_THR_SLOT_CYCLES 0x30
25 #define CMDQ_THR_BASE 0x100
26 #define CMDQ_THR_SIZE 0x80
27 #define CMDQ_THR_WARM_RESET 0x00
28 #define CMDQ_THR_ENABLE_TASK 0x04
29 #define CMDQ_THR_SUSPEND_TASK 0x08
30 #define CMDQ_THR_CURR_STATUS 0x0c
31 #define CMDQ_THR_IRQ_STATUS 0x10
32 #define CMDQ_THR_IRQ_ENABLE 0x14
33 #define CMDQ_THR_CURR_ADDR 0x20
34 #define CMDQ_THR_END_ADDR 0x24
35 #define CMDQ_THR_WAIT_TOKEN 0x30
36 #define CMDQ_THR_PRIORITY 0x40
38 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
39 #define CMDQ_THR_ENABLED 0x1
40 #define CMDQ_THR_DISABLED 0x0
41 #define CMDQ_THR_SUSPEND 0x1
42 #define CMDQ_THR_RESUME 0x0
43 #define CMDQ_THR_STATUS_SUSPENDED BIT(1)
44 #define CMDQ_THR_DO_WARM_RESET BIT(0)
45 #define CMDQ_THR_IRQ_DONE 0x1
46 #define CMDQ_THR_IRQ_ERROR 0x12
47 #define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
48 #define CMDQ_THR_IS_WAITING BIT(31)
50 #define CMDQ_JUMP_BY_OFFSET 0x10000000
51 #define CMDQ_JUMP_BY_PA 0x10000001
54 struct mbox_chan *chan;
56 struct list_head task_busy_list;
63 struct list_head list_entry;
65 struct cmdq_thread *thread;
66 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
70 struct mbox_controller mbox;
74 struct cmdq_thread *thread;
79 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
83 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
85 /* If already disabled, treat as suspended successful. */
86 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
89 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
90 status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
91 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
92 (u32)(thread->base - cmdq->base));
99 static void cmdq_thread_resume(struct cmdq_thread *thread)
101 writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
104 static void cmdq_init(struct cmdq *cmdq)
106 WARN_ON(clk_enable(cmdq->clock) < 0);
107 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
108 clk_disable(cmdq->clock);
111 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
115 writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
116 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
117 warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
119 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
120 (u32)(thread->base - cmdq->base));
127 static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
129 cmdq_thread_reset(cmdq, thread);
130 writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
133 /* notify GCE to re-fetch commands by setting GCE thread PC */
134 static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
136 writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
137 thread->base + CMDQ_THR_CURR_ADDR);
140 static void cmdq_task_insert_into_thread(struct cmdq_task *task)
142 struct device *dev = task->cmdq->mbox.dev;
143 struct cmdq_thread *thread = task->thread;
144 struct cmdq_task *prev_task = list_last_entry(
145 &thread->task_busy_list, typeof(*task), list_entry);
146 u64 *prev_task_base = prev_task->pkt->va_base;
148 /* let previous task jump to this task */
149 dma_sync_single_for_cpu(dev, prev_task->pa_base,
150 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
151 prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
152 (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
153 dma_sync_single_for_device(dev, prev_task->pa_base,
154 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
156 cmdq_thread_invalidate_fetched_data(thread);
159 static bool cmdq_command_is_wfe(u64 cmd)
161 u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
162 u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32;
163 u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0xffffffff;
165 return ((cmd & wfe_mask) == (wfe_op | wfe_option));
168 /* we assume tasks in the same display GCE thread are waiting the same event. */
169 static void cmdq_task_remove_wfe(struct cmdq_task *task)
171 struct device *dev = task->cmdq->mbox.dev;
172 u64 *base = task->pkt->va_base;
175 dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size,
177 for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
178 if (cmdq_command_is_wfe(base[i]))
179 base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
181 dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
185 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
187 return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
190 static void cmdq_thread_wait_end(struct cmdq_thread *thread,
191 unsigned long end_pa)
193 struct device *dev = thread->chan->mbox->dev;
194 unsigned long curr_pa;
196 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR,
197 curr_pa, curr_pa == end_pa, 1, 20))
198 dev_err(dev, "GCE thread cannot run to end.\n");
201 static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status sta)
203 struct cmdq_task_cb *cb = &task->pkt->async_cb;
204 struct cmdq_cb_data data;
206 WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL);
208 data.data = cb->data;
211 list_del(&task->list_entry);
214 static void cmdq_task_handle_error(struct cmdq_task *task)
216 struct cmdq_thread *thread = task->thread;
217 struct cmdq_task *next_task;
219 dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
220 WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
221 next_task = list_first_entry_or_null(&thread->task_busy_list,
222 struct cmdq_task, list_entry);
224 writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
225 cmdq_thread_resume(thread);
228 static void cmdq_thread_irq_handler(struct cmdq *cmdq,
229 struct cmdq_thread *thread)
231 struct cmdq_task *task, *tmp, *curr_task = NULL;
232 u32 curr_pa, irq_flag, task_end_pa;
235 irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
236 writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
239 * When ISR call this function, another CPU core could run
240 * "release task" right before we acquire the spin lock, and thus
241 * reset / disable this GCE thread, so we need to check the enable
242 * bit of this GCE thread.
244 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
247 if (irq_flag & CMDQ_THR_IRQ_ERROR)
249 else if (irq_flag & CMDQ_THR_IRQ_DONE)
254 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
256 list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
258 task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
259 if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
262 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
263 cmdq_task_exec_done(task, CMDQ_CB_NORMAL);
266 cmdq_task_exec_done(task, CMDQ_CB_ERROR);
267 cmdq_task_handle_error(curr_task);
275 if (list_empty(&thread->task_busy_list)) {
276 cmdq_thread_disable(cmdq, thread);
277 clk_disable(cmdq->clock);
281 static irqreturn_t cmdq_irq_handler(int irq, void *dev)
283 struct cmdq *cmdq = dev;
284 unsigned long irq_status, flags = 0L;
287 irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;
288 if (!(irq_status ^ CMDQ_IRQ_MASK))
291 for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) {
292 struct cmdq_thread *thread = &cmdq->thread[bit];
294 spin_lock_irqsave(&thread->chan->lock, flags);
295 cmdq_thread_irq_handler(cmdq, thread);
296 spin_unlock_irqrestore(&thread->chan->lock, flags);
302 static int cmdq_suspend(struct device *dev)
304 struct cmdq *cmdq = dev_get_drvdata(dev);
305 struct cmdq_thread *thread;
307 bool task_running = false;
309 cmdq->suspended = true;
311 for (i = 0; i < cmdq->thread_nr; i++) {
312 thread = &cmdq->thread[i];
313 if (!list_empty(&thread->task_busy_list)) {
320 dev_warn(dev, "exist running task(s) in suspend\n");
322 clk_unprepare(cmdq->clock);
327 static int cmdq_resume(struct device *dev)
329 struct cmdq *cmdq = dev_get_drvdata(dev);
331 WARN_ON(clk_prepare(cmdq->clock) < 0);
332 cmdq->suspended = false;
336 static int cmdq_remove(struct platform_device *pdev)
338 struct cmdq *cmdq = platform_get_drvdata(pdev);
340 clk_unprepare(cmdq->clock);
345 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
347 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
348 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
349 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
350 struct cmdq_task *task;
351 unsigned long curr_pa, end_pa;
353 /* Client should not flush new tasks if suspended. */
354 WARN_ON(cmdq->suspended);
356 task = kzalloc(sizeof(*task), GFP_ATOMIC);
361 INIT_LIST_HEAD(&task->list_entry);
362 task->pa_base = pkt->pa_base;
363 task->thread = thread;
366 if (list_empty(&thread->task_busy_list)) {
367 WARN_ON(clk_enable(cmdq->clock) < 0);
368 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
370 writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
371 writel(task->pa_base + pkt->cmd_buf_size,
372 thread->base + CMDQ_THR_END_ADDR);
373 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
374 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
375 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
377 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
378 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
379 end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
382 * Atomic execution should remove the following wfe, i.e. only
383 * wait event at first task, and prevent to pause when running.
385 if (thread->atomic_exec) {
386 /* GCE is executing if command is not WFE */
387 if (!cmdq_thread_is_in_wfe(thread)) {
388 cmdq_thread_resume(thread);
389 cmdq_thread_wait_end(thread, end_pa);
390 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
391 /* set to this task directly */
392 writel(task->pa_base,
393 thread->base + CMDQ_THR_CURR_ADDR);
395 cmdq_task_insert_into_thread(task);
396 cmdq_task_remove_wfe(task);
397 smp_mb(); /* modify jump before enable thread */
401 if (curr_pa == end_pa - CMDQ_INST_SIZE ||
403 /* set to this task directly */
404 writel(task->pa_base,
405 thread->base + CMDQ_THR_CURR_ADDR);
407 cmdq_task_insert_into_thread(task);
408 smp_mb(); /* modify jump before enable thread */
411 writel(task->pa_base + pkt->cmd_buf_size,
412 thread->base + CMDQ_THR_END_ADDR);
413 cmdq_thread_resume(thread);
415 list_move_tail(&task->list_entry, &thread->task_busy_list);
420 static int cmdq_mbox_startup(struct mbox_chan *chan)
425 static void cmdq_mbox_shutdown(struct mbox_chan *chan)
429 static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
430 .send_data = cmdq_mbox_send_data,
431 .startup = cmdq_mbox_startup,
432 .shutdown = cmdq_mbox_shutdown,
435 static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
436 const struct of_phandle_args *sp)
438 int ind = sp->args[0];
439 struct cmdq_thread *thread;
441 if (ind >= mbox->num_chans)
442 return ERR_PTR(-EINVAL);
444 thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
445 thread->priority = sp->args[1];
446 thread->atomic_exec = (sp->args[2] != 0);
447 thread->chan = &mbox->chans[ind];
449 return &mbox->chans[ind];
452 static int cmdq_probe(struct platform_device *pdev)
454 struct device *dev = &pdev->dev;
455 struct resource *res;
459 cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
463 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
464 cmdq->base = devm_ioremap_resource(dev, res);
465 if (IS_ERR(cmdq->base)) {
466 dev_err(dev, "failed to ioremap gce\n");
467 return PTR_ERR(cmdq->base);
470 cmdq->irq = platform_get_irq(pdev, 0);
472 dev_err(dev, "failed to get irq\n");
475 err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
478 dev_err(dev, "failed to register ISR (%d)\n", err);
482 dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
483 dev, cmdq->base, cmdq->irq);
485 cmdq->clock = devm_clk_get(dev, "gce");
486 if (IS_ERR(cmdq->clock)) {
487 dev_err(dev, "failed to get gce clk\n");
488 return PTR_ERR(cmdq->clock);
491 cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
492 cmdq->mbox.dev = dev;
493 cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
494 sizeof(*cmdq->mbox.chans), GFP_KERNEL);
495 if (!cmdq->mbox.chans)
498 cmdq->mbox.num_chans = cmdq->thread_nr;
499 cmdq->mbox.ops = &cmdq_mbox_chan_ops;
500 cmdq->mbox.of_xlate = cmdq_xlate;
502 /* make use of TXDONE_BY_ACK */
503 cmdq->mbox.txdone_irq = false;
504 cmdq->mbox.txdone_poll = false;
506 cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
507 sizeof(*cmdq->thread), GFP_KERNEL);
511 for (i = 0; i < cmdq->thread_nr; i++) {
512 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
514 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
515 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
518 err = devm_mbox_controller_register(dev, &cmdq->mbox);
520 dev_err(dev, "failed to register mailbox: %d\n", err);
524 platform_set_drvdata(pdev, cmdq);
525 WARN_ON(clk_prepare(cmdq->clock) < 0);
532 static const struct dev_pm_ops cmdq_pm_ops = {
533 .suspend = cmdq_suspend,
534 .resume = cmdq_resume,
537 static const struct of_device_id cmdq_of_ids[] = {
538 {.compatible = "mediatek,mt8173-gce", .data = (void *)16},
542 static struct platform_driver cmdq_drv = {
544 .remove = cmdq_remove,
548 .of_match_table = cmdq_of_ids,
552 static int __init cmdq_drv_init(void)
554 return platform_driver_register(&cmdq_drv);
557 static void __exit cmdq_drv_exit(void)
559 platform_driver_unregister(&cmdq_drv);
562 subsys_initcall(cmdq_drv_init);
563 module_exit(cmdq_drv_exit);
565 MODULE_LICENSE("GPL v2");