1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder
5 Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
6 Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org>
10 http://products.zarlink.com/product_profiles/MT312.htm
11 http://products.zarlink.com/product_profiles/SL1935.htm
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/slab.h>
22 #include <media/dvb_frontend.h>
23 #include "mt312_priv.h"
26 /* Max transfer size done by I2C transfer functions */
27 #define MAX_XFER_SIZE 64
30 struct i2c_adapter *i2c;
31 /* configuration settings */
32 const struct mt312_config *config;
33 struct dvb_frontend frontend;
41 #define dprintk(args...) \
44 printk(KERN_DEBUG "mt312: " args); \
47 #define MT312_PLL_CLK 10000000UL /* 10 MHz */
48 #define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */
50 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
51 u8 *buf, const size_t count)
54 struct i2c_msg msg[2];
55 u8 regbuf[1] = { reg };
57 msg[0].addr = state->config->demod_address;
61 msg[1].addr = state->config->demod_address;
62 msg[1].flags = I2C_M_RD;
66 ret = i2c_transfer(state->i2c, msg, 2);
69 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
75 dprintk("R(%d):", reg & 0x7f);
76 for (i = 0; i < count; i++)
77 printk(KERN_CONT " %02x", buf[i]);
84 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
85 const u8 *src, const size_t count)
88 u8 buf[MAX_XFER_SIZE];
91 if (1 + count > sizeof(buf)) {
93 "mt312: write: len=%zu is too big!\n", count);
99 dprintk("W(%d):", reg & 0x7f);
100 for (i = 0; i < count; i++)
101 printk(KERN_CONT " %02x", src[i]);
106 memcpy(&buf[1], src, count);
108 msg.addr = state->config->demod_address;
113 ret = i2c_transfer(state->i2c, &msg, 1);
116 dprintk("%s: ret == %d\n", __func__, ret);
123 static inline int mt312_readreg(struct mt312_state *state,
124 const enum mt312_reg_addr reg, u8 *val)
126 return mt312_read(state, reg, val, 1);
129 static inline int mt312_writereg(struct mt312_state *state,
130 const enum mt312_reg_addr reg, const u8 val)
132 u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
135 return mt312_write(state, reg, &tmp, 1);
138 static inline u32 mt312_div(u32 a, u32 b)
140 return (a + (b / 2)) / b;
143 static int mt312_reset(struct mt312_state *state, const u8 full)
145 return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
148 static int mt312_get_inversion(struct mt312_state *state,
149 enum fe_spectral_inversion *i)
154 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
158 if (vit_mode & 0x80) /* auto inversion was used */
159 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
164 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
173 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
177 if (sym_rate_h & 0x80) {
178 /* symbol rate search was used */
179 ret = mt312_writereg(state, MON_CTRL, 0x03);
183 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
187 monitor = (buf[0] << 8) | buf[1];
189 dprintk("sr(auto) = %u\n",
190 mt312_div(monitor * 15625, 4));
192 ret = mt312_writereg(state, MON_CTRL, 0x05);
196 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
200 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
202 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
206 sym_rat_op = (buf[0] << 8) | buf[1];
208 dprintk("sym_rat_op=%d dec_ratio=%d\n",
209 sym_rat_op, dec_ratio);
210 dprintk("*sr(manual) = %lu\n",
211 (((state->xtal * 8192) / (sym_rat_op + 8192)) *
218 static int mt312_get_code_rate(struct mt312_state *state, enum fe_code_rate *cr)
220 const enum fe_code_rate fec_tab[8] =
221 { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
222 FEC_AUTO, FEC_AUTO };
227 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
231 *cr = fec_tab[(fec_status >> 4) & 0x07];
236 static int mt312_initfe(struct dvb_frontend *fe)
238 struct mt312_state *state = fe->demodulator_priv;
243 ret = mt312_writereg(state, CONFIG,
244 (state->freq_mult == 6 ? 0x88 : 0x8c));
248 /* wait at least 150 usec */
252 ret = mt312_reset(state, 1);
256 /* Per datasheet, write correct values. 09/28/03 ACCJr.
257 * If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
259 u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
260 0x01, 0x00, 0x00, 0x00 };
262 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
270 ret = mt312_writereg(state, GPP_CTRL, 0x80);
274 /* configure ZL10313 for optimal ADC performance */
277 ret = mt312_write(state, HW_CTRL, buf, 2);
281 /* enable MPEG output and ADCs */
282 ret = mt312_writereg(state, HW_CTRL, 0x00);
286 ret = mt312_writereg(state, MPEG_CTRL, 0x00);
294 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000);
297 buf[1] = mt312_div(state->xtal, 22000 * 4);
299 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
303 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
307 /* different MOCLK polarity */
317 ret = mt312_writereg(state, OP_CTRL, buf[0]);
325 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
329 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
336 static int mt312_send_master_cmd(struct dvb_frontend *fe,
337 struct dvb_diseqc_master_cmd *c)
339 struct mt312_state *state = fe->demodulator_priv;
343 if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
346 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
350 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
354 ret = mt312_writereg(state, DISEQC_MODE,
355 (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
360 /* is there a better way to wait for message to be transmitted */
363 /* set DISEQC_MODE[2:0] to zero if a return message is expected */
364 if (c->msg[0] & 0x02) {
365 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
373 static int mt312_send_burst(struct dvb_frontend *fe,
374 const enum fe_sec_mini_cmd c)
376 struct mt312_state *state = fe->demodulator_priv;
377 const u8 mini_tab[2] = { 0x02, 0x03 };
385 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
389 ret = mt312_writereg(state, DISEQC_MODE,
390 (diseqc_mode & 0x40) | mini_tab[c]);
397 static int mt312_set_tone(struct dvb_frontend *fe,
398 const enum fe_sec_tone_mode t)
400 struct mt312_state *state = fe->demodulator_priv;
401 const u8 tone_tab[2] = { 0x01, 0x00 };
406 if (t > SEC_TONE_OFF)
409 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
413 ret = mt312_writereg(state, DISEQC_MODE,
414 (diseqc_mode & 0x40) | tone_tab[t]);
421 static int mt312_set_voltage(struct dvb_frontend *fe,
422 const enum fe_sec_voltage v)
424 struct mt312_state *state = fe->demodulator_priv;
425 const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
428 if (v > SEC_VOLTAGE_OFF)
432 if (state->config->voltage_inverted)
435 return mt312_writereg(state, DISEQC_MODE, val);
438 static int mt312_read_status(struct dvb_frontend *fe, enum fe_status *s)
440 struct mt312_state *state = fe->demodulator_priv;
446 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
450 dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n",
451 status[0], status[1], status[2]);
453 if (status[0] & 0xc0)
454 *s |= FE_HAS_SIGNAL; /* signal noise ratio */
455 if (status[0] & 0x04)
456 *s |= FE_HAS_CARRIER; /* qpsk carrier lock */
457 if (status[2] & 0x02)
458 *s |= FE_HAS_VITERBI; /* viterbi lock */
459 if (status[2] & 0x04)
460 *s |= FE_HAS_SYNC; /* byte align lock */
461 if (status[0] & 0x01)
462 *s |= FE_HAS_LOCK; /* qpsk lock */
467 static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
469 struct mt312_state *state = fe->demodulator_priv;
473 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
477 *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
482 static int mt312_read_signal_strength(struct dvb_frontend *fe,
483 u16 *signal_strength)
485 struct mt312_state *state = fe->demodulator_priv;
491 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
495 agc = (buf[0] << 6) | (buf[1] >> 2);
496 err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
498 *signal_strength = agc;
500 dprintk("agc=%08x err_db=%hd\n", agc, err_db);
505 static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
507 struct mt312_state *state = fe->demodulator_priv;
511 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
515 *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
520 static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
522 struct mt312_state *state = fe->demodulator_priv;
526 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
530 *ubc = (buf[0] << 8) | buf[1];
535 static int mt312_set_frontend(struct dvb_frontend *fe)
537 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
538 struct mt312_state *state = fe->demodulator_priv;
540 u8 buf[5], config_val;
543 const u8 fec_tab[10] =
544 { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
545 const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
547 dprintk("%s: Freq %d\n", __func__, p->frequency);
549 if ((p->frequency < fe->ops.info.frequency_min_hz / kHz)
550 || (p->frequency > fe->ops.info.frequency_max_hz / kHz))
553 if (((int)p->inversion < INVERSION_OFF)
554 || (p->inversion > INVERSION_ON))
557 if ((p->symbol_rate < fe->ops.info.symbol_rate_min)
558 || (p->symbol_rate > fe->ops.info.symbol_rate_max))
561 if (((int)p->fec_inner < FEC_NONE)
562 || (p->fec_inner > FEC_AUTO))
565 if ((p->fec_inner == FEC_4_5)
566 || (p->fec_inner == FEC_8_9))
571 /* For now we will do this only for the VP310.
572 * It should be better for the mt312 as well,
573 * but tuning will be slower. ACCJr 09/29/03
575 ret = mt312_readreg(state, CONFIG, &config_val);
578 if (p->symbol_rate >= 30000000) {
579 /* Note that 30MS/s should use 90MHz */
580 if (state->freq_mult == 6) {
581 /* We are running 60MHz */
582 state->freq_mult = 9;
583 ret = mt312_initfe(fe);
588 if (state->freq_mult == 9) {
589 /* We are running 90MHz */
590 state->freq_mult = 6;
591 ret = mt312_initfe(fe);
606 if (fe->ops.tuner_ops.set_params) {
607 fe->ops.tuner_ops.set_params(fe);
608 if (fe->ops.i2c_gate_ctrl)
609 fe->ops.i2c_gate_ctrl(fe, 0);
612 /* sr = (u16)(sr * 256.0 / 1000000.0) */
613 sr = mt312_div(p->symbol_rate * 4, 15625);
616 buf[0] = (sr >> 8) & 0x3f;
617 buf[1] = (sr >> 0) & 0xff;
620 buf[2] = inv_tab[p->inversion] | fec_tab[p->fec_inner];
623 buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
625 if (p->symbol_rate < 10000000)
626 buf[3] |= 0x04; /* use afc mode */
631 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
635 ret = mt312_reset(state, 0);
642 static int mt312_get_frontend(struct dvb_frontend *fe,
643 struct dtv_frontend_properties *p)
645 struct mt312_state *state = fe->demodulator_priv;
648 ret = mt312_get_inversion(state, &p->inversion);
652 ret = mt312_get_symbol_rate(state, &p->symbol_rate);
656 ret = mt312_get_code_rate(state, &p->fec_inner);
663 static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
665 struct mt312_state *state = fe->demodulator_priv;
672 ret = mt312_readreg(state, GPP_CTRL, &val);
676 /* preserve this bit to not accidentally shutdown ADC */
686 ret = mt312_writereg(state, GPP_CTRL, val);
692 static int mt312_sleep(struct dvb_frontend *fe)
694 struct mt312_state *state = fe->demodulator_priv;
698 /* reset all registers to defaults */
699 ret = mt312_reset(state, 1);
703 if (state->id == ID_ZL10313) {
705 ret = mt312_writereg(state, GPP_CTRL, 0x00);
709 /* full shutdown of ADCs, mpeg bus tristated */
710 ret = mt312_writereg(state, HW_CTRL, 0x0d);
715 ret = mt312_readreg(state, CONFIG, &config);
720 ret = mt312_writereg(state, CONFIG, config & 0x7f);
727 static int mt312_get_tune_settings(struct dvb_frontend *fe,
728 struct dvb_frontend_tune_settings *fesettings)
730 fesettings->min_delay_ms = 50;
731 fesettings->step_size = 0;
732 fesettings->max_drift = 0;
736 static void mt312_release(struct dvb_frontend *fe)
738 struct mt312_state *state = fe->demodulator_priv;
742 #define MT312_SYS_CLK 90000000UL /* 90 MHz */
743 static const struct dvb_frontend_ops mt312_ops = {
744 .delsys = { SYS_DVBS },
746 .name = "Zarlink ???? DVB-S",
747 .frequency_min_hz = 950 * MHz,
748 .frequency_max_hz = 2150 * MHz,
749 /* FIXME: adjust freq to real used xtal */
750 .frequency_stepsize_hz = MT312_PLL_CLK / 128,
751 .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
752 .symbol_rate_max = MT312_SYS_CLK / 2,
754 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
755 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
756 FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
760 .release = mt312_release,
762 .init = mt312_initfe,
763 .sleep = mt312_sleep,
764 .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
766 .set_frontend = mt312_set_frontend,
767 .get_frontend = mt312_get_frontend,
768 .get_tune_settings = mt312_get_tune_settings,
770 .read_status = mt312_read_status,
771 .read_ber = mt312_read_ber,
772 .read_signal_strength = mt312_read_signal_strength,
773 .read_snr = mt312_read_snr,
774 .read_ucblocks = mt312_read_ucblocks,
776 .diseqc_send_master_cmd = mt312_send_master_cmd,
777 .diseqc_send_burst = mt312_send_burst,
778 .set_tone = mt312_set_tone,
779 .set_voltage = mt312_set_voltage,
782 struct dvb_frontend *mt312_attach(const struct mt312_config *config,
783 struct i2c_adapter *i2c)
785 struct mt312_state *state = NULL;
787 /* allocate memory for the internal state */
788 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
792 /* setup the state */
793 state->config = config;
796 /* check if the demod is there */
797 if (mt312_readreg(state, ID, &state->id) < 0)
800 /* create dvb_frontend */
801 memcpy(&state->frontend.ops, &mt312_ops,
802 sizeof(struct dvb_frontend_ops));
803 state->frontend.demodulator_priv = state;
807 strscpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S",
808 sizeof(state->frontend.ops.info.name));
809 state->xtal = MT312_PLL_CLK;
810 state->freq_mult = 9;
813 strscpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S",
814 sizeof(state->frontend.ops.info.name));
815 state->xtal = MT312_PLL_CLK;
816 state->freq_mult = 6;
819 strscpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S",
820 sizeof(state->frontend.ops.info.name));
821 state->xtal = MT312_PLL_CLK_10_111;
822 state->freq_mult = 9;
825 printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313 are supported chips.\n");
829 return &state->frontend;
835 EXPORT_SYMBOL(mt312_attach);
837 module_param(debug, int, 0644);
838 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
840 MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
841 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
842 MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
843 MODULE_LICENSE("GPL");