1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017 Intel Corporation.
4 #include <linux/acpi.h>
6 #include <linux/module.h>
7 #include <linux/pm_runtime.h>
8 #include <media/v4l2-ctrls.h>
9 #include <media/v4l2-device.h>
11 #define OV13858_REG_VALUE_08BIT 1
12 #define OV13858_REG_VALUE_16BIT 2
13 #define OV13858_REG_VALUE_24BIT 3
15 #define OV13858_REG_MODE_SELECT 0x0100
16 #define OV13858_MODE_STANDBY 0x00
17 #define OV13858_MODE_STREAMING 0x01
19 #define OV13858_REG_SOFTWARE_RST 0x0103
20 #define OV13858_SOFTWARE_RST 0x01
22 /* PLL1 generates PCLK and MIPI_PHY_CLK */
23 #define OV13858_REG_PLL1_CTRL_0 0x0300
24 #define OV13858_REG_PLL1_CTRL_1 0x0301
25 #define OV13858_REG_PLL1_CTRL_2 0x0302
26 #define OV13858_REG_PLL1_CTRL_3 0x0303
27 #define OV13858_REG_PLL1_CTRL_4 0x0304
28 #define OV13858_REG_PLL1_CTRL_5 0x0305
30 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
31 #define OV13858_REG_PLL2_CTRL_B 0x030b
32 #define OV13858_REG_PLL2_CTRL_C 0x030c
33 #define OV13858_REG_PLL2_CTRL_D 0x030d
34 #define OV13858_REG_PLL2_CTRL_E 0x030e
35 #define OV13858_REG_PLL2_CTRL_F 0x030f
36 #define OV13858_REG_PLL2_CTRL_12 0x0312
37 #define OV13858_REG_MIPI_SC_CTRL0 0x3016
38 #define OV13858_REG_MIPI_SC_CTRL1 0x3022
41 #define OV13858_REG_CHIP_ID 0x300a
42 #define OV13858_CHIP_ID 0x00d855
44 /* V_TIMING internal */
45 #define OV13858_REG_VTS 0x380e
46 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */
47 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */
48 #define OV13858_VTS_MAX 0x7fff
50 /* HBLANK control - read only */
51 #define OV13858_PPL_270MHZ 2244
52 #define OV13858_PPL_540MHZ 4488
54 /* Exposure control */
55 #define OV13858_REG_EXPOSURE 0x3500
56 #define OV13858_EXPOSURE_MIN 4
57 #define OV13858_EXPOSURE_STEP 1
58 #define OV13858_EXPOSURE_DEFAULT 0x640
60 /* Analog gain control */
61 #define OV13858_REG_ANALOG_GAIN 0x3508
62 #define OV13858_ANA_GAIN_MIN 0
63 #define OV13858_ANA_GAIN_MAX 0x1fff
64 #define OV13858_ANA_GAIN_STEP 1
65 #define OV13858_ANA_GAIN_DEFAULT 0x80
67 /* Digital gain control */
68 #define OV13858_REG_B_MWB_GAIN 0x5100
69 #define OV13858_REG_G_MWB_GAIN 0x5102
70 #define OV13858_REG_R_MWB_GAIN 0x5104
71 #define OV13858_DGTL_GAIN_MIN 0
72 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */
73 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */
74 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
76 /* Test Pattern Control */
77 #define OV13858_REG_TEST_PATTERN 0x4503
78 #define OV13858_TEST_PATTERN_ENABLE BIT(7)
79 #define OV13858_TEST_PATTERN_MASK 0xfc
81 /* Number of frames to skip */
82 #define OV13858_NUM_OF_SKIP_FRAMES 2
89 struct ov13858_reg_list {
91 const struct ov13858_reg *regs;
94 /* Link frequency config */
95 struct ov13858_link_freq_config {
98 /* PLL registers for this link frequency */
99 struct ov13858_reg_list reg_list;
102 /* Mode : resolution and related config&values */
103 struct ov13858_mode {
113 /* Index of Link frequency config to be used */
115 /* Default register values */
116 struct ov13858_reg_list reg_list;
119 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
120 static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
122 {OV13858_REG_PLL1_CTRL_0, 0x07},
123 {OV13858_REG_PLL1_CTRL_1, 0x01},
124 {OV13858_REG_PLL1_CTRL_2, 0xc2},
125 {OV13858_REG_PLL1_CTRL_3, 0x00},
126 {OV13858_REG_PLL1_CTRL_4, 0x00},
127 {OV13858_REG_PLL1_CTRL_5, 0x01},
130 {OV13858_REG_PLL2_CTRL_B, 0x05},
131 {OV13858_REG_PLL2_CTRL_C, 0x01},
132 {OV13858_REG_PLL2_CTRL_D, 0x0e},
133 {OV13858_REG_PLL2_CTRL_E, 0x05},
134 {OV13858_REG_PLL2_CTRL_F, 0x01},
135 {OV13858_REG_PLL2_CTRL_12, 0x01},
136 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
137 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
141 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
144 static const struct ov13858_reg mipi_data_rate_540mbps[] = {
146 {OV13858_REG_PLL1_CTRL_0, 0x07},
147 {OV13858_REG_PLL1_CTRL_1, 0x01},
148 {OV13858_REG_PLL1_CTRL_2, 0xc2},
149 {OV13858_REG_PLL1_CTRL_3, 0x01},
150 {OV13858_REG_PLL1_CTRL_4, 0x00},
151 {OV13858_REG_PLL1_CTRL_5, 0x01},
154 {OV13858_REG_PLL2_CTRL_B, 0x05},
155 {OV13858_REG_PLL2_CTRL_C, 0x01},
156 {OV13858_REG_PLL2_CTRL_D, 0x0e},
157 {OV13858_REG_PLL2_CTRL_E, 0x05},
158 {OV13858_REG_PLL2_CTRL_F, 0x01},
159 {OV13858_REG_PLL2_CTRL_12, 0x01},
160 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
161 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
164 static const struct ov13858_reg mode_4224x3136_regs[] = {
355 static const struct ov13858_reg mode_2112x1568_regs[] = {
546 static const struct ov13858_reg mode_2112x1188_regs[] = {
737 static const struct ov13858_reg mode_1056x784_regs[] = {
928 static const char * const ov13858_test_pattern_menu[] = {
930 "Vertical Color Bar Type 1",
931 "Vertical Color Bar Type 2",
932 "Vertical Color Bar Type 3",
933 "Vertical Color Bar Type 4"
936 /* Configurations for supported link frequencies */
937 #define OV13858_NUM_OF_LINK_FREQS 2
938 #define OV13858_LINK_FREQ_540MHZ 540000000ULL
939 #define OV13858_LINK_FREQ_270MHZ 270000000ULL
940 #define OV13858_LINK_FREQ_INDEX_0 0
941 #define OV13858_LINK_FREQ_INDEX_1 1
944 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
945 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
947 static u64 link_freq_to_pixel_rate(u64 f)
955 /* Menu items for LINK_FREQ V4L2 control */
956 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
957 OV13858_LINK_FREQ_540MHZ,
958 OV13858_LINK_FREQ_270MHZ
961 /* Link frequency configs */
962 static const struct ov13858_link_freq_config
963 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
965 .pixels_per_line = OV13858_PPL_540MHZ,
967 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
968 .regs = mipi_data_rate_1080mbps,
972 .pixels_per_line = OV13858_PPL_270MHZ,
974 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
975 .regs = mipi_data_rate_540mbps,
981 static const struct ov13858_mode supported_modes[] = {
985 .vts_def = OV13858_VTS_30FPS,
986 .vts_min = OV13858_VTS_30FPS,
988 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
989 .regs = mode_4224x3136_regs,
991 .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
996 .vts_def = OV13858_VTS_30FPS,
999 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
1000 .regs = mode_2112x1568_regs,
1002 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1007 .vts_def = OV13858_VTS_30FPS,
1010 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1011 .regs = mode_2112x1188_regs,
1013 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1018 .vts_def = OV13858_VTS_30FPS,
1021 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1022 .regs = mode_1056x784_regs,
1024 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1029 struct v4l2_subdev sd;
1030 struct media_pad pad;
1032 struct v4l2_ctrl_handler ctrl_handler;
1034 struct v4l2_ctrl *link_freq;
1035 struct v4l2_ctrl *pixel_rate;
1036 struct v4l2_ctrl *vblank;
1037 struct v4l2_ctrl *hblank;
1038 struct v4l2_ctrl *exposure;
1041 const struct ov13858_mode *cur_mode;
1043 /* Mutex for serialized access */
1046 /* Streaming on/off */
1050 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
1052 /* Read registers up to 4 at a time */
1053 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1056 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1057 struct i2c_msg msgs[2];
1061 __be16 reg_addr_be = cpu_to_be16(reg);
1066 data_be_p = (u8 *)&data_be;
1067 /* Write register address */
1068 msgs[0].addr = client->addr;
1071 msgs[0].buf = (u8 *)®_addr_be;
1073 /* Read data from register */
1074 msgs[1].addr = client->addr;
1075 msgs[1].flags = I2C_M_RD;
1077 msgs[1].buf = &data_be_p[4 - len];
1079 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1080 if (ret != ARRAY_SIZE(msgs))
1083 *val = be32_to_cpu(data_be);
1088 /* Write registers up to 4 at a time */
1089 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1092 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1101 buf[1] = reg & 0xff;
1103 val = cpu_to_be32(__val);
1109 buf[buf_i++] = val_p[val_i++];
1111 if (i2c_master_send(client, buf, len + 2) != len + 2)
1117 /* Write a list of registers */
1118 static int ov13858_write_regs(struct ov13858 *ov13858,
1119 const struct ov13858_reg *regs, u32 len)
1121 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1125 for (i = 0; i < len; i++) {
1126 ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1129 dev_err_ratelimited(
1131 "Failed to write reg 0x%4.4x. error = %d\n",
1132 regs[i].address, ret);
1141 static int ov13858_write_reg_list(struct ov13858 *ov13858,
1142 const struct ov13858_reg_list *r_list)
1144 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1147 /* Open sub-device */
1148 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1150 struct ov13858 *ov13858 = to_ov13858(sd);
1151 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
1155 mutex_lock(&ov13858->mutex);
1157 /* Initialize try_fmt */
1158 try_fmt->width = ov13858->cur_mode->width;
1159 try_fmt->height = ov13858->cur_mode->height;
1160 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1161 try_fmt->field = V4L2_FIELD_NONE;
1163 /* No crop or compose */
1164 mutex_unlock(&ov13858->mutex);
1169 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1173 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
1174 OV13858_REG_VALUE_16BIT, d_gain);
1178 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
1179 OV13858_REG_VALUE_16BIT, d_gain);
1183 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
1184 OV13858_REG_VALUE_16BIT, d_gain);
1189 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1194 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1195 OV13858_REG_VALUE_08BIT, &val);
1200 val &= OV13858_TEST_PATTERN_MASK;
1201 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1203 val &= ~OV13858_TEST_PATTERN_ENABLE;
1206 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1207 OV13858_REG_VALUE_08BIT, val);
1210 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1212 struct ov13858 *ov13858 = container_of(ctrl->handler,
1213 struct ov13858, ctrl_handler);
1214 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1218 /* Propagate change of current control to all related controls */
1220 case V4L2_CID_VBLANK:
1221 /* Update max exposure while meeting expected vblanking */
1222 max = ov13858->cur_mode->height + ctrl->val - 8;
1223 __v4l2_ctrl_modify_range(ov13858->exposure,
1224 ov13858->exposure->minimum,
1225 max, ov13858->exposure->step, max);
1230 * Applying V4L2 control value only happens
1231 * when power is up for streaming
1233 if (!pm_runtime_get_if_in_use(&client->dev))
1238 case V4L2_CID_ANALOGUE_GAIN:
1239 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1240 OV13858_REG_VALUE_16BIT, ctrl->val);
1242 case V4L2_CID_DIGITAL_GAIN:
1243 ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1245 case V4L2_CID_EXPOSURE:
1246 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1247 OV13858_REG_VALUE_24BIT,
1250 case V4L2_CID_VBLANK:
1251 /* Update VTS that meets expected vertical blanking */
1252 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1253 OV13858_REG_VALUE_16BIT,
1254 ov13858->cur_mode->height
1257 case V4L2_CID_TEST_PATTERN:
1258 ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1261 dev_info(&client->dev,
1262 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1263 ctrl->id, ctrl->val);
1267 pm_runtime_put(&client->dev);
1272 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1273 .s_ctrl = ov13858_set_ctrl,
1276 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1277 struct v4l2_subdev_pad_config *cfg,
1278 struct v4l2_subdev_mbus_code_enum *code)
1280 /* Only one bayer order(GRBG) is supported */
1281 if (code->index > 0)
1284 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1289 static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1290 struct v4l2_subdev_pad_config *cfg,
1291 struct v4l2_subdev_frame_size_enum *fse)
1293 if (fse->index >= ARRAY_SIZE(supported_modes))
1296 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1299 fse->min_width = supported_modes[fse->index].width;
1300 fse->max_width = fse->min_width;
1301 fse->min_height = supported_modes[fse->index].height;
1302 fse->max_height = fse->min_height;
1307 static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1308 struct v4l2_subdev_format *fmt)
1310 fmt->format.width = mode->width;
1311 fmt->format.height = mode->height;
1312 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1313 fmt->format.field = V4L2_FIELD_NONE;
1316 static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1317 struct v4l2_subdev_pad_config *cfg,
1318 struct v4l2_subdev_format *fmt)
1320 struct v4l2_mbus_framefmt *framefmt;
1321 struct v4l2_subdev *sd = &ov13858->sd;
1323 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1324 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1325 fmt->format = *framefmt;
1327 ov13858_update_pad_format(ov13858->cur_mode, fmt);
1333 static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1334 struct v4l2_subdev_pad_config *cfg,
1335 struct v4l2_subdev_format *fmt)
1337 struct ov13858 *ov13858 = to_ov13858(sd);
1340 mutex_lock(&ov13858->mutex);
1341 ret = ov13858_do_get_pad_format(ov13858, cfg, fmt);
1342 mutex_unlock(&ov13858->mutex);
1348 ov13858_set_pad_format(struct v4l2_subdev *sd,
1349 struct v4l2_subdev_pad_config *cfg,
1350 struct v4l2_subdev_format *fmt)
1352 struct ov13858 *ov13858 = to_ov13858(sd);
1353 const struct ov13858_mode *mode;
1354 struct v4l2_mbus_framefmt *framefmt;
1361 mutex_lock(&ov13858->mutex);
1363 /* Only one raw bayer(GRBG) order is supported */
1364 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1365 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1367 mode = v4l2_find_nearest_size(supported_modes,
1368 ARRAY_SIZE(supported_modes),
1370 fmt->format.width, fmt->format.height);
1371 ov13858_update_pad_format(mode, fmt);
1372 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1373 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1374 *framefmt = fmt->format;
1376 ov13858->cur_mode = mode;
1377 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1378 link_freq = link_freq_menu_items[mode->link_freq_index];
1379 pixel_rate = link_freq_to_pixel_rate(link_freq);
1380 __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate);
1382 /* Update limits and set FPS to default */
1383 vblank_def = ov13858->cur_mode->vts_def -
1384 ov13858->cur_mode->height;
1385 vblank_min = ov13858->cur_mode->vts_min -
1386 ov13858->cur_mode->height;
1387 __v4l2_ctrl_modify_range(
1388 ov13858->vblank, vblank_min,
1389 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1391 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
1393 link_freq_configs[mode->link_freq_index].pixels_per_line
1394 - ov13858->cur_mode->width;
1395 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1396 h_blank, 1, h_blank);
1399 mutex_unlock(&ov13858->mutex);
1404 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1406 *frames = OV13858_NUM_OF_SKIP_FRAMES;
1411 /* Start streaming */
1412 static int ov13858_start_streaming(struct ov13858 *ov13858)
1414 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1415 const struct ov13858_reg_list *reg_list;
1416 int ret, link_freq_index;
1418 /* Get out of from software reset */
1419 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1420 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1422 dev_err(&client->dev, "%s failed to set powerup registers\n",
1428 link_freq_index = ov13858->cur_mode->link_freq_index;
1429 reg_list = &link_freq_configs[link_freq_index].reg_list;
1430 ret = ov13858_write_reg_list(ov13858, reg_list);
1432 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1436 /* Apply default values of current mode */
1437 reg_list = &ov13858->cur_mode->reg_list;
1438 ret = ov13858_write_reg_list(ov13858, reg_list);
1440 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1444 /* Apply customized values from user */
1445 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1449 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1450 OV13858_REG_VALUE_08BIT,
1451 OV13858_MODE_STREAMING);
1454 /* Stop streaming */
1455 static int ov13858_stop_streaming(struct ov13858 *ov13858)
1457 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1458 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1461 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1463 struct ov13858 *ov13858 = to_ov13858(sd);
1464 struct i2c_client *client = v4l2_get_subdevdata(sd);
1467 mutex_lock(&ov13858->mutex);
1468 if (ov13858->streaming == enable) {
1469 mutex_unlock(&ov13858->mutex);
1474 ret = pm_runtime_get_sync(&client->dev);
1476 pm_runtime_put_noidle(&client->dev);
1481 * Apply default & customized values
1482 * and then start streaming.
1484 ret = ov13858_start_streaming(ov13858);
1488 ov13858_stop_streaming(ov13858);
1489 pm_runtime_put(&client->dev);
1492 ov13858->streaming = enable;
1493 mutex_unlock(&ov13858->mutex);
1498 pm_runtime_put(&client->dev);
1500 mutex_unlock(&ov13858->mutex);
1505 static int __maybe_unused ov13858_suspend(struct device *dev)
1507 struct i2c_client *client = to_i2c_client(dev);
1508 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1509 struct ov13858 *ov13858 = to_ov13858(sd);
1511 if (ov13858->streaming)
1512 ov13858_stop_streaming(ov13858);
1517 static int __maybe_unused ov13858_resume(struct device *dev)
1519 struct i2c_client *client = to_i2c_client(dev);
1520 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1521 struct ov13858 *ov13858 = to_ov13858(sd);
1524 if (ov13858->streaming) {
1525 ret = ov13858_start_streaming(ov13858);
1533 ov13858_stop_streaming(ov13858);
1534 ov13858->streaming = false;
1538 /* Verify chip ID */
1539 static int ov13858_identify_module(struct ov13858 *ov13858)
1541 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1545 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1546 OV13858_REG_VALUE_24BIT, &val);
1550 if (val != OV13858_CHIP_ID) {
1551 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1552 OV13858_CHIP_ID, val);
1559 static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1560 .s_stream = ov13858_set_stream,
1563 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1564 .enum_mbus_code = ov13858_enum_mbus_code,
1565 .get_fmt = ov13858_get_pad_format,
1566 .set_fmt = ov13858_set_pad_format,
1567 .enum_frame_size = ov13858_enum_frame_size,
1570 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1571 .g_skip_frames = ov13858_get_skip_frames,
1574 static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1575 .video = &ov13858_video_ops,
1576 .pad = &ov13858_pad_ops,
1577 .sensor = &ov13858_sensor_ops,
1580 static const struct media_entity_operations ov13858_subdev_entity_ops = {
1581 .link_validate = v4l2_subdev_link_validate,
1584 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1585 .open = ov13858_open,
1588 /* Initialize control handlers */
1589 static int ov13858_init_controls(struct ov13858 *ov13858)
1591 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1592 struct v4l2_ctrl_handler *ctrl_hdlr;
1599 const struct ov13858_mode *mode;
1602 ctrl_hdlr = &ov13858->ctrl_handler;
1603 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
1607 mutex_init(&ov13858->mutex);
1608 ctrl_hdlr->lock = &ov13858->mutex;
1609 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1612 OV13858_NUM_OF_LINK_FREQS - 1,
1614 link_freq_menu_items);
1615 if (ov13858->link_freq)
1616 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1618 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1619 pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1620 /* By default, PIXEL_RATE is read only */
1621 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1622 V4L2_CID_PIXEL_RATE,
1623 pixel_rate_min, pixel_rate_max,
1626 mode = ov13858->cur_mode;
1627 vblank_def = mode->vts_def - mode->height;
1628 vblank_min = mode->vts_min - mode->height;
1629 ov13858->vblank = v4l2_ctrl_new_std(
1630 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1631 vblank_min, OV13858_VTS_MAX - mode->height, 1,
1634 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1636 ov13858->hblank = v4l2_ctrl_new_std(
1637 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1638 hblank, hblank, 1, hblank);
1639 if (ov13858->hblank)
1640 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1642 exposure_max = mode->vts_def - 8;
1643 ov13858->exposure = v4l2_ctrl_new_std(
1644 ctrl_hdlr, &ov13858_ctrl_ops,
1645 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1646 exposure_max, OV13858_EXPOSURE_STEP,
1647 OV13858_EXPOSURE_DEFAULT);
1649 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1650 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1651 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1654 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1655 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1656 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1658 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1659 V4L2_CID_TEST_PATTERN,
1660 ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1661 0, 0, ov13858_test_pattern_menu);
1662 if (ctrl_hdlr->error) {
1663 ret = ctrl_hdlr->error;
1664 dev_err(&client->dev, "%s control init failed (%d)\n",
1669 ov13858->sd.ctrl_handler = ctrl_hdlr;
1674 v4l2_ctrl_handler_free(ctrl_hdlr);
1675 mutex_destroy(&ov13858->mutex);
1680 static void ov13858_free_controls(struct ov13858 *ov13858)
1682 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1683 mutex_destroy(&ov13858->mutex);
1686 static int ov13858_probe(struct i2c_client *client,
1687 const struct i2c_device_id *devid)
1689 struct ov13858 *ov13858;
1693 device_property_read_u32(&client->dev, "clock-frequency", &val);
1694 if (val != 19200000)
1697 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1701 /* Initialize subdev */
1702 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1704 /* Check module identity */
1705 ret = ov13858_identify_module(ov13858);
1707 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1711 /* Set default mode to max resolution */
1712 ov13858->cur_mode = &supported_modes[0];
1714 ret = ov13858_init_controls(ov13858);
1718 /* Initialize subdev */
1719 ov13858->sd.internal_ops = &ov13858_internal_ops;
1720 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1721 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1722 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1724 /* Initialize source pad */
1725 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1726 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1728 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1729 goto error_handler_free;
1732 ret = v4l2_async_register_subdev_sensor_common(&ov13858->sd);
1734 goto error_media_entity;
1737 * Device is already turned on by i2c-core with ACPI domain PM.
1738 * Enable runtime PM and turn off the device.
1740 pm_runtime_set_active(&client->dev);
1741 pm_runtime_enable(&client->dev);
1742 pm_runtime_idle(&client->dev);
1747 media_entity_cleanup(&ov13858->sd.entity);
1750 ov13858_free_controls(ov13858);
1751 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1756 static int ov13858_remove(struct i2c_client *client)
1758 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1759 struct ov13858 *ov13858 = to_ov13858(sd);
1761 v4l2_async_unregister_subdev(sd);
1762 media_entity_cleanup(&sd->entity);
1763 ov13858_free_controls(ov13858);
1765 pm_runtime_disable(&client->dev);
1770 static const struct i2c_device_id ov13858_id_table[] = {
1775 MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1777 static const struct dev_pm_ops ov13858_pm_ops = {
1778 SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume)
1782 static const struct acpi_device_id ov13858_acpi_ids[] = {
1787 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1790 static struct i2c_driver ov13858_i2c_driver = {
1793 .pm = &ov13858_pm_ops,
1794 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1796 .probe = ov13858_probe,
1797 .remove = ov13858_remove,
1798 .id_table = ov13858_id_table,
1801 module_i2c_driver(ov13858_i2c_driver);
1803 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1804 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
1805 MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>");
1806 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1807 MODULE_LICENSE("GPL v2");