1 // SPDX-License-Identifier: GPL-2.0-only
3 * Omnivision OV2659 CMOS Image Sensor driver
5 * Copyright (C) 2015 Texas Instruments, Inc.
7 * Benoit Parrot <bparrot@ti.com>
8 * Lad, Prabhakar <prabhakar.csengg@gmail.com>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/of_graph.h>
17 #include <linux/pm_runtime.h>
19 #include <media/i2c/ov2659.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-event.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-image-sizes.h>
24 #include <media/v4l2-subdev.h>
26 #define DRIVER_NAME "ov2659"
29 * OV2659 register definitions
31 #define REG_SOFTWARE_STANDBY 0x0100
32 #define REG_SOFTWARE_RESET 0x0103
33 #define REG_IO_CTRL00 0x3000
34 #define REG_IO_CTRL01 0x3001
35 #define REG_IO_CTRL02 0x3002
36 #define REG_OUTPUT_VALUE00 0x3008
37 #define REG_OUTPUT_VALUE01 0x3009
38 #define REG_OUTPUT_VALUE02 0x300d
39 #define REG_OUTPUT_SELECT00 0x300e
40 #define REG_OUTPUT_SELECT01 0x300f
41 #define REG_OUTPUT_SELECT02 0x3010
42 #define REG_OUTPUT_DRIVE 0x3011
43 #define REG_INPUT_READOUT00 0x302d
44 #define REG_INPUT_READOUT01 0x302e
45 #define REG_INPUT_READOUT02 0x302f
47 #define REG_SC_PLL_CTRL0 0x3003
48 #define REG_SC_PLL_CTRL1 0x3004
49 #define REG_SC_PLL_CTRL2 0x3005
50 #define REG_SC_PLL_CTRL3 0x3006
51 #define REG_SC_CHIP_ID_H 0x300a
52 #define REG_SC_CHIP_ID_L 0x300b
53 #define REG_SC_PWC 0x3014
54 #define REG_SC_CLKRST0 0x301a
55 #define REG_SC_CLKRST1 0x301b
56 #define REG_SC_CLKRST2 0x301c
57 #define REG_SC_CLKRST3 0x301d
58 #define REG_SC_SUB_ID 0x302a
59 #define REG_SC_SCCB_ID 0x302b
61 #define REG_GROUP_ADDRESS_00 0x3200
62 #define REG_GROUP_ADDRESS_01 0x3201
63 #define REG_GROUP_ADDRESS_02 0x3202
64 #define REG_GROUP_ADDRESS_03 0x3203
65 #define REG_GROUP_ACCESS 0x3208
67 #define REG_AWB_R_GAIN_H 0x3400
68 #define REG_AWB_R_GAIN_L 0x3401
69 #define REG_AWB_G_GAIN_H 0x3402
70 #define REG_AWB_G_GAIN_L 0x3403
71 #define REG_AWB_B_GAIN_H 0x3404
72 #define REG_AWB_B_GAIN_L 0x3405
73 #define REG_AWB_MANUAL_CONTROL 0x3406
75 #define REG_TIMING_HS_H 0x3800
76 #define REG_TIMING_HS_L 0x3801
77 #define REG_TIMING_VS_H 0x3802
78 #define REG_TIMING_VS_L 0x3803
79 #define REG_TIMING_HW_H 0x3804
80 #define REG_TIMING_HW_L 0x3805
81 #define REG_TIMING_VH_H 0x3806
82 #define REG_TIMING_VH_L 0x3807
83 #define REG_TIMING_DVPHO_H 0x3808
84 #define REG_TIMING_DVPHO_L 0x3809
85 #define REG_TIMING_DVPVO_H 0x380a
86 #define REG_TIMING_DVPVO_L 0x380b
87 #define REG_TIMING_HTS_H 0x380c
88 #define REG_TIMING_HTS_L 0x380d
89 #define REG_TIMING_VTS_H 0x380e
90 #define REG_TIMING_VTS_L 0x380f
91 #define REG_TIMING_HOFFS_H 0x3810
92 #define REG_TIMING_HOFFS_L 0x3811
93 #define REG_TIMING_VOFFS_H 0x3812
94 #define REG_TIMING_VOFFS_L 0x3813
95 #define REG_TIMING_XINC 0x3814
96 #define REG_TIMING_YINC 0x3815
97 #define REG_TIMING_VERT_FORMAT 0x3820
98 #define REG_TIMING_HORIZ_FORMAT 0x3821
100 #define REG_FORMAT_CTRL00 0x4300
102 #define REG_VFIFO_READ_START_H 0x4608
103 #define REG_VFIFO_READ_START_L 0x4609
105 #define REG_DVP_CTRL02 0x4708
107 #define REG_ISP_CTRL00 0x5000
108 #define REG_ISP_CTRL01 0x5001
109 #define REG_ISP_CTRL02 0x5002
111 #define REG_LENC_RED_X0_H 0x500c
112 #define REG_LENC_RED_X0_L 0x500d
113 #define REG_LENC_RED_Y0_H 0x500e
114 #define REG_LENC_RED_Y0_L 0x500f
115 #define REG_LENC_RED_A1 0x5010
116 #define REG_LENC_RED_B1 0x5011
117 #define REG_LENC_RED_A2_B2 0x5012
118 #define REG_LENC_GREEN_X0_H 0x5013
119 #define REG_LENC_GREEN_X0_L 0x5014
120 #define REG_LENC_GREEN_Y0_H 0x5015
121 #define REG_LENC_GREEN_Y0_L 0x5016
122 #define REG_LENC_GREEN_A1 0x5017
123 #define REG_LENC_GREEN_B1 0x5018
124 #define REG_LENC_GREEN_A2_B2 0x5019
125 #define REG_LENC_BLUE_X0_H 0x501a
126 #define REG_LENC_BLUE_X0_L 0x501b
127 #define REG_LENC_BLUE_Y0_H 0x501c
128 #define REG_LENC_BLUE_Y0_L 0x501d
129 #define REG_LENC_BLUE_A1 0x501e
130 #define REG_LENC_BLUE_B1 0x501f
131 #define REG_LENC_BLUE_A2_B2 0x5020
133 #define REG_AWB_CTRL00 0x5035
134 #define REG_AWB_CTRL01 0x5036
135 #define REG_AWB_CTRL02 0x5037
136 #define REG_AWB_CTRL03 0x5038
137 #define REG_AWB_CTRL04 0x5039
138 #define REG_AWB_LOCAL_LIMIT 0x503a
139 #define REG_AWB_CTRL12 0x5049
140 #define REG_AWB_CTRL13 0x504a
141 #define REG_AWB_CTRL14 0x504b
143 #define REG_SHARPENMT_THRESH1 0x5064
144 #define REG_SHARPENMT_THRESH2 0x5065
145 #define REG_SHARPENMT_OFFSET1 0x5066
146 #define REG_SHARPENMT_OFFSET2 0x5067
147 #define REG_DENOISE_THRESH1 0x5068
148 #define REG_DENOISE_THRESH2 0x5069
149 #define REG_DENOISE_OFFSET1 0x506a
150 #define REG_DENOISE_OFFSET2 0x506b
151 #define REG_SHARPEN_THRESH1 0x506c
152 #define REG_SHARPEN_THRESH2 0x506d
153 #define REG_CIP_CTRL00 0x506e
154 #define REG_CIP_CTRL01 0x506f
156 #define REG_CMX_SIGN 0x5079
157 #define REG_CMX_MISC_CTRL 0x507a
159 #define REG_PRE_ISP_CTRL00 0x50a0
160 #define TEST_PATTERN_ENABLE BIT(7)
161 #define VERTICAL_COLOR_BAR_MASK 0x53
163 #define REG_NULL 0x0000 /* Array end token */
165 #define OV265X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
166 #define OV2659_ID 0x2656
168 struct sensor_register {
173 struct ov2659_framesize {
177 const struct sensor_register *regs;
180 struct ov2659_pll_ctrl {
186 struct ov2659_pixfmt {
188 /* Output format Register Value (REG_FORMAT_CTRL00) */
189 struct sensor_register *format_ctrl_regs;
192 struct pll_ctrl_reg {
198 struct v4l2_subdev sd;
199 struct media_pad pad;
200 struct v4l2_mbus_framefmt format;
201 unsigned int xvclk_frequency;
202 const struct ov2659_platform_data *pdata;
204 struct i2c_client *client;
205 struct v4l2_ctrl_handler ctrls;
206 struct v4l2_ctrl *link_frequency;
207 const struct ov2659_framesize *frame_size;
208 struct sensor_register *format_ctrl_regs;
209 struct ov2659_pll_ctrl pll;
211 /* used to control the sensor PWDN pin */
212 struct gpio_desc *pwdn_gpio;
213 /* used to control the sensor RESETB pin */
214 struct gpio_desc *resetb_gpio;
217 static const struct sensor_register ov2659_init_regs[] = {
218 { REG_IO_CTRL00, 0x03 },
219 { REG_IO_CTRL01, 0xff },
220 { REG_IO_CTRL02, 0xe0 },
228 { REG_TIMING_HS_H, 0x00 },
229 { REG_TIMING_HS_L, 0x00 },
230 { REG_TIMING_VS_H, 0x00 },
231 { REG_TIMING_VS_L, 0x00 },
232 { REG_TIMING_HW_H, 0x06 },
233 { REG_TIMING_HW_L, 0x5f },
234 { REG_TIMING_VH_H, 0x04 },
235 { REG_TIMING_VH_L, 0xb7 },
236 { REG_TIMING_DVPHO_H, 0x03 },
237 { REG_TIMING_DVPHO_L, 0x20 },
238 { REG_TIMING_DVPVO_H, 0x02 },
239 { REG_TIMING_DVPVO_L, 0x58 },
240 { REG_TIMING_HTS_H, 0x05 },
241 { REG_TIMING_HTS_L, 0x14 },
242 { REG_TIMING_VTS_H, 0x02 },
243 { REG_TIMING_VTS_L, 0x68 },
244 { REG_TIMING_HOFFS_L, 0x08 },
245 { REG_TIMING_VOFFS_L, 0x02 },
246 { REG_TIMING_XINC, 0x31 },
247 { REG_TIMING_YINC, 0x31 },
258 { REG_DVP_CTRL02, 0x01 },
266 { REG_TIMING_VERT_FORMAT, 0x81 },
267 { REG_TIMING_HORIZ_FORMAT, 0x01 },
269 { REG_VFIFO_READ_START_H, 0x00 },
270 { REG_VFIFO_READ_START_L, 0x80 },
271 { REG_FORMAT_CTRL00, 0x30 },
273 { REG_ISP_CTRL00, 0xfb },
274 { REG_ISP_CTRL01, 0x1f },
275 { REG_ISP_CTRL02, 0x00 },
301 { REG_CMX_SIGN, 0x98 },
302 { REG_CMX_MISC_CTRL, 0x21 },
303 { REG_AWB_CTRL00, 0x6a },
304 { REG_AWB_CTRL01, 0x11 },
305 { REG_AWB_CTRL02, 0x92 },
306 { REG_AWB_CTRL03, 0x21 },
307 { REG_AWB_CTRL04, 0xe1 },
308 { REG_AWB_LOCAL_LIMIT, 0x01 },
322 { REG_AWB_CTRL12, 0x70 },
323 { REG_AWB_CTRL13, 0xf0 },
324 { REG_AWB_CTRL14, 0xf0 },
325 { REG_LENC_RED_X0_H, 0x03 },
326 { REG_LENC_RED_X0_L, 0x20 },
327 { REG_LENC_RED_Y0_H, 0x02 },
328 { REG_LENC_RED_Y0_L, 0x5c },
329 { REG_LENC_RED_A1, 0x48 },
330 { REG_LENC_RED_B1, 0x00 },
331 { REG_LENC_RED_A2_B2, 0x66 },
332 { REG_LENC_GREEN_X0_H, 0x03 },
333 { REG_LENC_GREEN_X0_L, 0x30 },
334 { REG_LENC_GREEN_Y0_H, 0x02 },
335 { REG_LENC_GREEN_Y0_L, 0x7c },
336 { REG_LENC_GREEN_A1, 0x40 },
337 { REG_LENC_GREEN_B1, 0x00 },
338 { REG_LENC_GREEN_A2_B2, 0x66 },
339 { REG_LENC_BLUE_X0_H, 0x03 },
340 { REG_LENC_BLUE_X0_L, 0x10 },
341 { REG_LENC_BLUE_Y0_H, 0x02 },
342 { REG_LENC_BLUE_Y0_L, 0x7c },
343 { REG_LENC_BLUE_A1, 0x3a },
344 { REG_LENC_BLUE_B1, 0x00 },
345 { REG_LENC_BLUE_A2_B2, 0x66 },
346 { REG_CIP_CTRL00, 0x44 },
347 { REG_SHARPENMT_THRESH1, 0x08 },
348 { REG_SHARPENMT_THRESH2, 0x10 },
349 { REG_SHARPENMT_OFFSET1, 0x12 },
350 { REG_SHARPENMT_OFFSET2, 0x02 },
351 { REG_SHARPEN_THRESH1, 0x08 },
352 { REG_SHARPEN_THRESH2, 0x10 },
353 { REG_CIP_CTRL01, 0xa6 },
354 { REG_DENOISE_THRESH1, 0x08 },
355 { REG_DENOISE_THRESH2, 0x10 },
356 { REG_DENOISE_OFFSET1, 0x04 },
357 { REG_DENOISE_OFFSET2, 0x12 },
361 { REG_CMX_MISC_CTRL, 0x01 },
379 static struct sensor_register ov2659_720p[] = {
380 { REG_TIMING_HS_H, 0x00 },
381 { REG_TIMING_HS_L, 0xa0 },
382 { REG_TIMING_VS_H, 0x00 },
383 { REG_TIMING_VS_L, 0xf0 },
384 { REG_TIMING_HW_H, 0x05 },
385 { REG_TIMING_HW_L, 0xbf },
386 { REG_TIMING_VH_H, 0x03 },
387 { REG_TIMING_VH_L, 0xcb },
388 { REG_TIMING_DVPHO_H, 0x05 },
389 { REG_TIMING_DVPHO_L, 0x00 },
390 { REG_TIMING_DVPVO_H, 0x02 },
391 { REG_TIMING_DVPVO_L, 0xd0 },
392 { REG_TIMING_HTS_H, 0x06 },
393 { REG_TIMING_HTS_L, 0x4c },
394 { REG_TIMING_VTS_H, 0x02 },
395 { REG_TIMING_VTS_L, 0xe8 },
396 { REG_TIMING_HOFFS_L, 0x10 },
397 { REG_TIMING_VOFFS_L, 0x06 },
398 { REG_TIMING_XINC, 0x11 },
399 { REG_TIMING_YINC, 0x11 },
400 { REG_TIMING_VERT_FORMAT, 0x80 },
401 { REG_TIMING_HORIZ_FORMAT, 0x00 },
407 { REG_VFIFO_READ_START_H, 0x00 },
408 { REG_VFIFO_READ_START_L, 0x80 },
409 { REG_ISP_CTRL02, 0x00 },
414 static struct sensor_register ov2659_uxga[] = {
415 { REG_TIMING_HS_H, 0x00 },
416 { REG_TIMING_HS_L, 0x00 },
417 { REG_TIMING_VS_H, 0x00 },
418 { REG_TIMING_VS_L, 0x00 },
419 { REG_TIMING_HW_H, 0x06 },
420 { REG_TIMING_HW_L, 0x5f },
421 { REG_TIMING_VH_H, 0x04 },
422 { REG_TIMING_VH_L, 0xbb },
423 { REG_TIMING_DVPHO_H, 0x06 },
424 { REG_TIMING_DVPHO_L, 0x40 },
425 { REG_TIMING_DVPVO_H, 0x04 },
426 { REG_TIMING_DVPVO_L, 0xb0 },
427 { REG_TIMING_HTS_H, 0x07 },
428 { REG_TIMING_HTS_L, 0x9f },
429 { REG_TIMING_VTS_H, 0x04 },
430 { REG_TIMING_VTS_L, 0xd0 },
431 { REG_TIMING_HOFFS_L, 0x10 },
432 { REG_TIMING_VOFFS_L, 0x06 },
433 { REG_TIMING_XINC, 0x11 },
434 { REG_TIMING_YINC, 0x11 },
452 { REG_TIMING_VERT_FORMAT, 0x80 },
453 { REG_TIMING_HORIZ_FORMAT, 0x00 },
455 { REG_VFIFO_READ_START_H, 0x00 },
456 { REG_VFIFO_READ_START_L, 0x80 },
457 { REG_ISP_CTRL02, 0x00 },
462 static struct sensor_register ov2659_sxga[] = {
463 { REG_TIMING_HS_H, 0x00 },
464 { REG_TIMING_HS_L, 0x00 },
465 { REG_TIMING_VS_H, 0x00 },
466 { REG_TIMING_VS_L, 0x00 },
467 { REG_TIMING_HW_H, 0x06 },
468 { REG_TIMING_HW_L, 0x5f },
469 { REG_TIMING_VH_H, 0x04 },
470 { REG_TIMING_VH_L, 0xb7 },
471 { REG_TIMING_DVPHO_H, 0x05 },
472 { REG_TIMING_DVPHO_L, 0x00 },
473 { REG_TIMING_DVPVO_H, 0x04 },
474 { REG_TIMING_DVPVO_L, 0x00 },
475 { REG_TIMING_HTS_H, 0x07 },
476 { REG_TIMING_HTS_L, 0x9c },
477 { REG_TIMING_VTS_H, 0x04 },
478 { REG_TIMING_VTS_L, 0xd0 },
479 { REG_TIMING_HOFFS_L, 0x10 },
480 { REG_TIMING_VOFFS_L, 0x06 },
481 { REG_TIMING_XINC, 0x11 },
482 { REG_TIMING_YINC, 0x11 },
500 { REG_TIMING_VERT_FORMAT, 0x80 },
501 { REG_TIMING_HORIZ_FORMAT, 0x00 },
503 { REG_VFIFO_READ_START_H, 0x00 },
504 { REG_VFIFO_READ_START_L, 0x80 },
505 { REG_ISP_CTRL02, 0x00 },
510 static struct sensor_register ov2659_xga[] = {
511 { REG_TIMING_HS_H, 0x00 },
512 { REG_TIMING_HS_L, 0x00 },
513 { REG_TIMING_VS_H, 0x00 },
514 { REG_TIMING_VS_L, 0x00 },
515 { REG_TIMING_HW_H, 0x06 },
516 { REG_TIMING_HW_L, 0x5f },
517 { REG_TIMING_VH_H, 0x04 },
518 { REG_TIMING_VH_L, 0xb7 },
519 { REG_TIMING_DVPHO_H, 0x04 },
520 { REG_TIMING_DVPHO_L, 0x00 },
521 { REG_TIMING_DVPVO_H, 0x03 },
522 { REG_TIMING_DVPVO_L, 0x00 },
523 { REG_TIMING_HTS_H, 0x07 },
524 { REG_TIMING_HTS_L, 0x9c },
525 { REG_TIMING_VTS_H, 0x04 },
526 { REG_TIMING_VTS_L, 0xd0 },
527 { REG_TIMING_HOFFS_L, 0x10 },
528 { REG_TIMING_VOFFS_L, 0x06 },
529 { REG_TIMING_XINC, 0x11 },
530 { REG_TIMING_YINC, 0x11 },
548 { REG_TIMING_VERT_FORMAT, 0x80 },
549 { REG_TIMING_HORIZ_FORMAT, 0x00 },
551 { REG_VFIFO_READ_START_H, 0x00 },
552 { REG_VFIFO_READ_START_L, 0x80 },
553 { REG_ISP_CTRL02, 0x00 },
558 static struct sensor_register ov2659_svga[] = {
559 { REG_TIMING_HS_H, 0x00 },
560 { REG_TIMING_HS_L, 0x00 },
561 { REG_TIMING_VS_H, 0x00 },
562 { REG_TIMING_VS_L, 0x00 },
563 { REG_TIMING_HW_H, 0x06 },
564 { REG_TIMING_HW_L, 0x5f },
565 { REG_TIMING_VH_H, 0x04 },
566 { REG_TIMING_VH_L, 0xb7 },
567 { REG_TIMING_DVPHO_H, 0x03 },
568 { REG_TIMING_DVPHO_L, 0x20 },
569 { REG_TIMING_DVPVO_H, 0x02 },
570 { REG_TIMING_DVPVO_L, 0x58 },
571 { REG_TIMING_HTS_H, 0x05 },
572 { REG_TIMING_HTS_L, 0x14 },
573 { REG_TIMING_VTS_H, 0x02 },
574 { REG_TIMING_VTS_L, 0x68 },
575 { REG_TIMING_HOFFS_L, 0x08 },
576 { REG_TIMING_VOFFS_L, 0x02 },
577 { REG_TIMING_XINC, 0x31 },
578 { REG_TIMING_YINC, 0x31 },
596 { REG_TIMING_VERT_FORMAT, 0x81 },
597 { REG_TIMING_HORIZ_FORMAT, 0x01 },
599 { REG_VFIFO_READ_START_H, 0x00 },
600 { REG_VFIFO_READ_START_L, 0x80 },
601 { REG_ISP_CTRL02, 0x00 },
606 static struct sensor_register ov2659_vga[] = {
607 { REG_TIMING_HS_H, 0x00 },
608 { REG_TIMING_HS_L, 0x00 },
609 { REG_TIMING_VS_H, 0x00 },
610 { REG_TIMING_VS_L, 0x00 },
611 { REG_TIMING_HW_H, 0x06 },
612 { REG_TIMING_HW_L, 0x5f },
613 { REG_TIMING_VH_H, 0x04 },
614 { REG_TIMING_VH_L, 0xb7 },
615 { REG_TIMING_DVPHO_H, 0x02 },
616 { REG_TIMING_DVPHO_L, 0x80 },
617 { REG_TIMING_DVPVO_H, 0x01 },
618 { REG_TIMING_DVPVO_L, 0xe0 },
619 { REG_TIMING_HTS_H, 0x05 },
620 { REG_TIMING_HTS_L, 0x14 },
621 { REG_TIMING_VTS_H, 0x02 },
622 { REG_TIMING_VTS_L, 0x68 },
623 { REG_TIMING_HOFFS_L, 0x08 },
624 { REG_TIMING_VOFFS_L, 0x02 },
625 { REG_TIMING_XINC, 0x31 },
626 { REG_TIMING_YINC, 0x31 },
644 { REG_TIMING_VERT_FORMAT, 0x81 },
645 { REG_TIMING_HORIZ_FORMAT, 0x01 },
647 { REG_VFIFO_READ_START_H, 0x00 },
648 { REG_VFIFO_READ_START_L, 0xa0 },
649 { REG_ISP_CTRL02, 0x10 },
654 static struct sensor_register ov2659_qvga[] = {
655 { REG_TIMING_HS_H, 0x00 },
656 { REG_TIMING_HS_L, 0x00 },
657 { REG_TIMING_VS_H, 0x00 },
658 { REG_TIMING_VS_L, 0x00 },
659 { REG_TIMING_HW_H, 0x06 },
660 { REG_TIMING_HW_L, 0x5f },
661 { REG_TIMING_VH_H, 0x04 },
662 { REG_TIMING_VH_L, 0xb7 },
663 { REG_TIMING_DVPHO_H, 0x01 },
664 { REG_TIMING_DVPHO_L, 0x40 },
665 { REG_TIMING_DVPVO_H, 0x00 },
666 { REG_TIMING_DVPVO_L, 0xf0 },
667 { REG_TIMING_HTS_H, 0x05 },
668 { REG_TIMING_HTS_L, 0x14 },
669 { REG_TIMING_VTS_H, 0x02 },
670 { REG_TIMING_VTS_L, 0x68 },
671 { REG_TIMING_HOFFS_L, 0x08 },
672 { REG_TIMING_VOFFS_L, 0x02 },
673 { REG_TIMING_XINC, 0x31 },
674 { REG_TIMING_YINC, 0x31 },
692 { REG_TIMING_VERT_FORMAT, 0x81 },
693 { REG_TIMING_HORIZ_FORMAT, 0x01 },
695 { REG_VFIFO_READ_START_H, 0x00 },
696 { REG_VFIFO_READ_START_L, 0xa0 },
697 { REG_ISP_CTRL02, 0x10 },
701 static const struct pll_ctrl_reg ctrl3[] = {
718 static const struct pll_ctrl_reg ctrl1[] = {
737 static const struct ov2659_framesize ov2659_framesizes[] = {
742 .max_exp_lines = 248,
747 .max_exp_lines = 498,
752 .max_exp_lines = 498,
757 .max_exp_lines = 498,
762 .max_exp_lines = 498,
767 .max_exp_lines = 1048,
772 .max_exp_lines = 498,
777 static struct sensor_register ov2659_format_yuyv[] = {
778 { REG_FORMAT_CTRL00, 0x30 },
783 static struct sensor_register ov2659_format_uyvy[] = {
784 { REG_FORMAT_CTRL00, 0x32 },
789 static struct sensor_register ov2659_format_bggr[] = {
790 { REG_FORMAT_CTRL00, 0x00 },
795 static struct sensor_register ov2659_format_rgb565[] = {
796 { REG_FORMAT_CTRL00, 0x60 },
800 static const struct ov2659_pixfmt ov2659_formats[] = {
802 .code = MEDIA_BUS_FMT_YUYV8_2X8,
803 .format_ctrl_regs = ov2659_format_yuyv,
805 .code = MEDIA_BUS_FMT_UYVY8_2X8,
806 .format_ctrl_regs = ov2659_format_uyvy,
808 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
809 .format_ctrl_regs = ov2659_format_rgb565,
811 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
812 .format_ctrl_regs = ov2659_format_bggr,
816 static inline struct ov2659 *to_ov2659(struct v4l2_subdev *sd)
818 return container_of(sd, struct ov2659, sd);
821 /* sensor register write */
822 static int ov2659_write(struct i2c_client *client, u16 reg, u8 val)
832 msg.addr = client->addr;
833 msg.flags = client->flags;
835 msg.len = sizeof(buf);
837 ret = i2c_transfer(client->adapter, &msg, 1);
841 dev_dbg(&client->dev,
842 "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val);
847 /* sensor register read */
848 static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val)
850 struct i2c_msg msg[2];
857 msg[0].addr = client->addr;
858 msg[0].flags = client->flags;
860 msg[0].len = sizeof(buf);
862 msg[1].addr = client->addr;
863 msg[1].flags = client->flags | I2C_M_RD;
867 ret = i2c_transfer(client->adapter, msg, 2);
873 dev_dbg(&client->dev,
874 "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val);
879 static int ov2659_write_array(struct i2c_client *client,
880 const struct sensor_register *regs)
884 for (i = 0; ret == 0 && regs[i].addr; i++)
885 ret = ov2659_write(client, regs[i].addr, regs[i].value);
890 static void ov2659_pll_calc_params(struct ov2659 *ov2659)
892 const struct ov2659_platform_data *pdata = ov2659->pdata;
893 u8 ctrl1_reg = 0, ctrl2_reg = 0, ctrl3_reg = 0;
894 struct i2c_client *client = ov2659->client;
895 unsigned int desired = pdata->link_frequency;
896 u32 prediv, postdiv, mult;
901 for (i = 0; ctrl1[i].div != 0; i++) {
902 postdiv = ctrl1[i].div;
903 for (j = 0; ctrl3[j].div != 0; j++) {
904 prediv = ctrl3[j].div;
905 for (mult = 1; mult <= 63; mult++) {
906 actual = ov2659->xvclk_frequency;
910 delta = actual - desired;
913 if ((delta < bestdelta) || (bestdelta == -1)) {
915 ctrl1_reg = ctrl1[i].reg;
917 ctrl3_reg = ctrl3[j].reg;
923 ov2659->pll.ctrl1 = ctrl1_reg;
924 ov2659->pll.ctrl2 = ctrl2_reg;
925 ov2659->pll.ctrl3 = ctrl3_reg;
927 dev_dbg(&client->dev,
928 "Actual reg config: ctrl1_reg: %02x ctrl2_reg: %02x ctrl3_reg: %02x\n",
929 ctrl1_reg, ctrl2_reg, ctrl3_reg);
932 static int ov2659_set_pixel_clock(struct ov2659 *ov2659)
934 struct i2c_client *client = ov2659->client;
935 struct sensor_register pll_regs[] = {
936 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1},
937 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2},
938 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3},
942 dev_dbg(&client->dev, "%s\n", __func__);
944 return ov2659_write_array(client, pll_regs);
947 static void ov2659_get_default_format(struct v4l2_mbus_framefmt *format)
949 format->width = ov2659_framesizes[2].width;
950 format->height = ov2659_framesizes[2].height;
951 format->colorspace = V4L2_COLORSPACE_SRGB;
952 format->code = ov2659_formats[0].code;
953 format->field = V4L2_FIELD_NONE;
956 static void ov2659_set_streaming(struct ov2659 *ov2659, int on)
958 struct i2c_client *client = ov2659->client;
963 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
965 ret = ov2659_write(client, REG_SOFTWARE_STANDBY, on);
967 dev_err(&client->dev, "ov2659 soft standby failed\n");
970 static int ov2659_init(struct v4l2_subdev *sd, u32 val)
972 struct i2c_client *client = v4l2_get_subdevdata(sd);
974 return ov2659_write_array(client, ov2659_init_regs);
978 * V4L2 subdev video and pad level operations
981 static int ov2659_enum_mbus_code(struct v4l2_subdev *sd,
982 struct v4l2_subdev_pad_config *cfg,
983 struct v4l2_subdev_mbus_code_enum *code)
985 struct i2c_client *client = v4l2_get_subdevdata(sd);
987 dev_dbg(&client->dev, "%s:\n", __func__);
989 if (code->index >= ARRAY_SIZE(ov2659_formats))
992 code->code = ov2659_formats[code->index].code;
997 static int ov2659_enum_frame_sizes(struct v4l2_subdev *sd,
998 struct v4l2_subdev_pad_config *cfg,
999 struct v4l2_subdev_frame_size_enum *fse)
1001 struct i2c_client *client = v4l2_get_subdevdata(sd);
1002 int i = ARRAY_SIZE(ov2659_formats);
1004 dev_dbg(&client->dev, "%s:\n", __func__);
1006 if (fse->index >= ARRAY_SIZE(ov2659_framesizes))
1010 if (fse->code == ov2659_formats[i].code)
1013 fse->code = ov2659_formats[i].code;
1015 fse->min_width = ov2659_framesizes[fse->index].width;
1016 fse->max_width = fse->min_width;
1017 fse->max_height = ov2659_framesizes[fse->index].height;
1018 fse->min_height = fse->max_height;
1023 static int ov2659_get_fmt(struct v4l2_subdev *sd,
1024 struct v4l2_subdev_pad_config *cfg,
1025 struct v4l2_subdev_format *fmt)
1027 struct i2c_client *client = v4l2_get_subdevdata(sd);
1028 struct ov2659 *ov2659 = to_ov2659(sd);
1030 dev_dbg(&client->dev, "ov2659_get_fmt\n");
1032 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1033 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1034 struct v4l2_mbus_framefmt *mf;
1036 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1037 mutex_lock(&ov2659->lock);
1039 mutex_unlock(&ov2659->lock);
1046 mutex_lock(&ov2659->lock);
1047 fmt->format = ov2659->format;
1048 mutex_unlock(&ov2659->lock);
1050 dev_dbg(&client->dev, "ov2659_get_fmt: %x %dx%d\n",
1051 ov2659->format.code, ov2659->format.width,
1052 ov2659->format.height);
1057 static void __ov2659_try_frame_size(struct v4l2_mbus_framefmt *mf,
1058 const struct ov2659_framesize **size)
1060 const struct ov2659_framesize *fsize = &ov2659_framesizes[0];
1061 const struct ov2659_framesize *match = NULL;
1062 int i = ARRAY_SIZE(ov2659_framesizes);
1063 unsigned int min_err = UINT_MAX;
1066 int err = abs(fsize->width - mf->width)
1067 + abs(fsize->height - mf->height);
1068 if ((err < min_err) && (fsize->regs[0].addr)) {
1076 match = &ov2659_framesizes[2];
1078 mf->width = match->width;
1079 mf->height = match->height;
1085 static int ov2659_set_fmt(struct v4l2_subdev *sd,
1086 struct v4l2_subdev_pad_config *cfg,
1087 struct v4l2_subdev_format *fmt)
1089 struct i2c_client *client = v4l2_get_subdevdata(sd);
1090 int index = ARRAY_SIZE(ov2659_formats);
1091 struct v4l2_mbus_framefmt *mf = &fmt->format;
1092 const struct ov2659_framesize *size = NULL;
1093 struct ov2659 *ov2659 = to_ov2659(sd);
1096 dev_dbg(&client->dev, "ov2659_set_fmt\n");
1098 __ov2659_try_frame_size(mf, &size);
1100 while (--index >= 0)
1101 if (ov2659_formats[index].code == mf->code)
1106 mf->code = ov2659_formats[index].code;
1109 mf->colorspace = V4L2_COLORSPACE_SRGB;
1110 mf->field = V4L2_FIELD_NONE;
1112 mutex_lock(&ov2659->lock);
1114 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1115 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1116 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1122 if (ov2659->streaming) {
1123 mutex_unlock(&ov2659->lock);
1127 ov2659->frame_size = size;
1128 ov2659->format = fmt->format;
1129 ov2659->format_ctrl_regs =
1130 ov2659_formats[index].format_ctrl_regs;
1132 if (ov2659->format.code != MEDIA_BUS_FMT_SBGGR8_1X8)
1133 val = ov2659->pdata->link_frequency / 2;
1135 val = ov2659->pdata->link_frequency;
1137 ret = v4l2_ctrl_s_ctrl_int64(ov2659->link_frequency, val);
1139 dev_warn(&client->dev,
1140 "failed to set link_frequency rate (%d)\n",
1144 mutex_unlock(&ov2659->lock);
1148 static int ov2659_set_frame_size(struct ov2659 *ov2659)
1150 struct i2c_client *client = ov2659->client;
1152 dev_dbg(&client->dev, "%s\n", __func__);
1154 return ov2659_write_array(ov2659->client, ov2659->frame_size->regs);
1157 static int ov2659_set_format(struct ov2659 *ov2659)
1159 struct i2c_client *client = ov2659->client;
1161 dev_dbg(&client->dev, "%s\n", __func__);
1163 return ov2659_write_array(ov2659->client, ov2659->format_ctrl_regs);
1166 static int ov2659_s_stream(struct v4l2_subdev *sd, int on)
1168 struct i2c_client *client = v4l2_get_subdevdata(sd);
1169 struct ov2659 *ov2659 = to_ov2659(sd);
1172 dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
1174 mutex_lock(&ov2659->lock);
1178 if (ov2659->streaming == on)
1182 /* Stop Streaming Sequence */
1183 ov2659_set_streaming(ov2659, 0);
1184 ov2659->streaming = on;
1185 pm_runtime_put(&client->dev);
1189 ret = pm_runtime_get_sync(&client->dev);
1191 pm_runtime_put_noidle(&client->dev);
1195 ret = ov2659_init(sd, 0);
1197 ret = ov2659_set_pixel_clock(ov2659);
1199 ret = ov2659_set_frame_size(ov2659);
1201 ret = ov2659_set_format(ov2659);
1203 ov2659_set_streaming(ov2659, 1);
1204 ov2659->streaming = on;
1208 mutex_unlock(&ov2659->lock);
1212 static int ov2659_set_test_pattern(struct ov2659 *ov2659, int value)
1214 struct i2c_client *client = v4l2_get_subdevdata(&ov2659->sd);
1218 ret = ov2659_read(client, REG_PRE_ISP_CTRL00, &val);
1224 val &= ~TEST_PATTERN_ENABLE;
1227 val &= VERTICAL_COLOR_BAR_MASK;
1228 val |= TEST_PATTERN_ENABLE;
1232 return ov2659_write(client, REG_PRE_ISP_CTRL00, val);
1235 static int ov2659_s_ctrl(struct v4l2_ctrl *ctrl)
1237 struct ov2659 *ov2659 =
1238 container_of(ctrl->handler, struct ov2659, ctrls);
1239 struct i2c_client *client = ov2659->client;
1241 /* V4L2 controls values will be applied only when power is already up */
1242 if (!pm_runtime_get_if_in_use(&client->dev))
1246 case V4L2_CID_TEST_PATTERN:
1247 return ov2659_set_test_pattern(ov2659, ctrl->val);
1250 pm_runtime_put(&client->dev);
1254 static const struct v4l2_ctrl_ops ov2659_ctrl_ops = {
1255 .s_ctrl = ov2659_s_ctrl,
1258 static const char * const ov2659_test_pattern_menu[] = {
1260 "Vertical Color Bars",
1263 static int ov2659_power_off(struct device *dev)
1265 struct i2c_client *client = to_i2c_client(dev);
1266 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1267 struct ov2659 *ov2659 = to_ov2659(sd);
1269 dev_dbg(&client->dev, "%s:\n", __func__);
1271 gpiod_set_value(ov2659->pwdn_gpio, 1);
1276 static int ov2659_power_on(struct device *dev)
1278 struct i2c_client *client = to_i2c_client(dev);
1279 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1280 struct ov2659 *ov2659 = to_ov2659(sd);
1282 dev_dbg(&client->dev, "%s:\n", __func__);
1284 gpiod_set_value(ov2659->pwdn_gpio, 0);
1286 if (ov2659->resetb_gpio) {
1287 gpiod_set_value(ov2659->resetb_gpio, 1);
1288 usleep_range(500, 1000);
1289 gpiod_set_value(ov2659->resetb_gpio, 0);
1290 usleep_range(3000, 5000);
1296 /* -----------------------------------------------------------------------------
1297 * V4L2 subdev internal operations
1300 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1301 static int ov2659_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1303 struct i2c_client *client = v4l2_get_subdevdata(sd);
1304 struct v4l2_mbus_framefmt *format =
1305 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1307 dev_dbg(&client->dev, "%s:\n", __func__);
1309 ov2659_get_default_format(format);
1315 static const struct v4l2_subdev_core_ops ov2659_subdev_core_ops = {
1316 .log_status = v4l2_ctrl_subdev_log_status,
1317 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1318 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1321 static const struct v4l2_subdev_video_ops ov2659_subdev_video_ops = {
1322 .s_stream = ov2659_s_stream,
1325 static const struct v4l2_subdev_pad_ops ov2659_subdev_pad_ops = {
1326 .enum_mbus_code = ov2659_enum_mbus_code,
1327 .enum_frame_size = ov2659_enum_frame_sizes,
1328 .get_fmt = ov2659_get_fmt,
1329 .set_fmt = ov2659_set_fmt,
1332 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1333 static const struct v4l2_subdev_ops ov2659_subdev_ops = {
1334 .core = &ov2659_subdev_core_ops,
1335 .video = &ov2659_subdev_video_ops,
1336 .pad = &ov2659_subdev_pad_ops,
1339 static const struct v4l2_subdev_internal_ops ov2659_subdev_internal_ops = {
1340 .open = ov2659_open,
1344 static int ov2659_detect(struct v4l2_subdev *sd)
1346 struct i2c_client *client = v4l2_get_subdevdata(sd);
1351 dev_dbg(&client->dev, "%s:\n", __func__);
1353 ret = ov2659_write(client, REG_SOFTWARE_RESET, 0x01);
1355 dev_err(&client->dev, "Sensor soft reset failed\n");
1358 usleep_range(1000, 2000);
1360 /* Check sensor revision */
1361 ret = ov2659_read(client, REG_SC_CHIP_ID_H, &pid);
1363 ret = ov2659_read(client, REG_SC_CHIP_ID_L, &ver);
1368 id = OV265X_ID(pid, ver);
1369 if (id != OV2659_ID) {
1370 dev_err(&client->dev,
1371 "Sensor detection failed (%04X, %d)\n",
1375 dev_info(&client->dev, "Found OV%04X sensor\n", id);
1382 static struct ov2659_platform_data *
1383 ov2659_get_pdata(struct i2c_client *client)
1385 struct ov2659_platform_data *pdata;
1386 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
1387 struct device_node *endpoint;
1390 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
1391 return client->dev.platform_data;
1393 endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1397 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(endpoint),
1404 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1408 if (!bus_cfg.nr_of_link_frequencies) {
1409 dev_err(&client->dev,
1410 "link-frequencies property not found or too many\n");
1415 pdata->link_frequency = bus_cfg.link_frequencies[0];
1418 v4l2_fwnode_endpoint_free(&bus_cfg);
1419 of_node_put(endpoint);
1423 static int ov2659_probe(struct i2c_client *client)
1425 const struct ov2659_platform_data *pdata = ov2659_get_pdata(client);
1426 struct v4l2_subdev *sd;
1427 struct ov2659 *ov2659;
1432 dev_err(&client->dev, "platform data not specified\n");
1436 ov2659 = devm_kzalloc(&client->dev, sizeof(*ov2659), GFP_KERNEL);
1440 ov2659->pdata = pdata;
1441 ov2659->client = client;
1443 clk = devm_clk_get(&client->dev, "xvclk");
1445 return PTR_ERR(clk);
1447 ov2659->xvclk_frequency = clk_get_rate(clk);
1448 if (ov2659->xvclk_frequency < 6000000 ||
1449 ov2659->xvclk_frequency > 27000000)
1452 /* Optional gpio don't fail if not present */
1453 ov2659->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1455 if (IS_ERR(ov2659->pwdn_gpio))
1456 return PTR_ERR(ov2659->pwdn_gpio);
1458 /* Optional gpio don't fail if not present */
1459 ov2659->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1461 if (IS_ERR(ov2659->resetb_gpio))
1462 return PTR_ERR(ov2659->resetb_gpio);
1464 v4l2_ctrl_handler_init(&ov2659->ctrls, 2);
1465 ov2659->link_frequency =
1466 v4l2_ctrl_new_std(&ov2659->ctrls, &ov2659_ctrl_ops,
1467 V4L2_CID_PIXEL_RATE,
1468 pdata->link_frequency / 2,
1469 pdata->link_frequency, 1,
1470 pdata->link_frequency);
1471 v4l2_ctrl_new_std_menu_items(&ov2659->ctrls, &ov2659_ctrl_ops,
1472 V4L2_CID_TEST_PATTERN,
1473 ARRAY_SIZE(ov2659_test_pattern_menu) - 1,
1474 0, 0, ov2659_test_pattern_menu);
1475 ov2659->sd.ctrl_handler = &ov2659->ctrls;
1477 if (ov2659->ctrls.error) {
1478 dev_err(&client->dev, "%s: control initialization error %d\n",
1479 __func__, ov2659->ctrls.error);
1480 return ov2659->ctrls.error;
1484 client->flags |= I2C_CLIENT_SCCB;
1485 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1486 v4l2_i2c_subdev_init(sd, client, &ov2659_subdev_ops);
1488 sd->internal_ops = &ov2659_subdev_internal_ops;
1489 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1490 V4L2_SUBDEV_FL_HAS_EVENTS;
1493 #if defined(CONFIG_MEDIA_CONTROLLER)
1494 ov2659->pad.flags = MEDIA_PAD_FL_SOURCE;
1495 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1496 ret = media_entity_pads_init(&sd->entity, 1, &ov2659->pad);
1498 v4l2_ctrl_handler_free(&ov2659->ctrls);
1503 mutex_init(&ov2659->lock);
1505 ov2659_get_default_format(&ov2659->format);
1506 ov2659->frame_size = &ov2659_framesizes[2];
1507 ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs;
1509 ov2659_power_on(&client->dev);
1511 ret = ov2659_detect(sd);
1515 /* Calculate the PLL register value needed */
1516 ov2659_pll_calc_params(ov2659);
1518 ret = v4l2_async_register_subdev(&ov2659->sd);
1522 dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
1524 pm_runtime_set_active(&client->dev);
1525 pm_runtime_enable(&client->dev);
1526 pm_runtime_idle(&client->dev);
1531 v4l2_ctrl_handler_free(&ov2659->ctrls);
1532 ov2659_power_off(&client->dev);
1533 media_entity_cleanup(&sd->entity);
1534 mutex_destroy(&ov2659->lock);
1538 static int ov2659_remove(struct i2c_client *client)
1540 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1541 struct ov2659 *ov2659 = to_ov2659(sd);
1543 v4l2_ctrl_handler_free(&ov2659->ctrls);
1544 v4l2_async_unregister_subdev(sd);
1545 media_entity_cleanup(&sd->entity);
1546 mutex_destroy(&ov2659->lock);
1548 pm_runtime_disable(&client->dev);
1549 if (!pm_runtime_status_suspended(&client->dev))
1550 ov2659_power_off(&client->dev);
1551 pm_runtime_set_suspended(&client->dev);
1556 static const struct dev_pm_ops ov2659_pm_ops = {
1557 SET_RUNTIME_PM_OPS(ov2659_power_off, ov2659_power_on, NULL)
1560 static const struct i2c_device_id ov2659_id[] = {
1564 MODULE_DEVICE_TABLE(i2c, ov2659_id);
1566 #if IS_ENABLED(CONFIG_OF)
1567 static const struct of_device_id ov2659_of_match[] = {
1568 { .compatible = "ovti,ov2659", },
1571 MODULE_DEVICE_TABLE(of, ov2659_of_match);
1574 static struct i2c_driver ov2659_i2c_driver = {
1576 .name = DRIVER_NAME,
1577 .pm = &ov2659_pm_ops,
1578 .of_match_table = of_match_ptr(ov2659_of_match),
1580 .probe_new = ov2659_probe,
1581 .remove = ov2659_remove,
1582 .id_table = ov2659_id,
1585 module_i2c_driver(ov2659_i2c_driver);
1587 MODULE_AUTHOR("Benoit Parrot <bparrot@ti.com>");
1588 MODULE_DESCRIPTION("OV2659 CMOS Image Sensor driver");
1589 MODULE_LICENSE("GPL v2");