2 * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
4 * Based on original driver by Krzysztof Ha?asa:
5 * Copyright (C) 2015 Industrial Research Institute for Automation
6 * and Measurements PIAP
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License
10 * as published by the Free Software Foundation.
15 * 1. Under stress-testing, it has been observed that the PCIe link
16 * goes down, without reason. Therefore, the driver takes special care
17 * to allow device hot-unplugging.
19 * 2. TW686X devices are capable of setting a few different DMA modes,
20 * including: scatter-gather, field and frame modes. However,
21 * under stress testings it has been found that the machine can
22 * freeze completely if DMA registers are programmed while streaming
24 * This driver tries to access hardware registers as infrequently
26 * i. allocating fixed DMA buffers and memcpy'ing into
28 * ii. using a timer to mitigate the rate of DMA reset operations,
29 * on DMA channels error.
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci_ids.h>
38 #include <linux/slab.h>
39 #include <linux/timer.h>
42 #include "tw686x-regs.h"
45 * This module parameter allows to control the DMA_TIMER_INTERVAL value.
46 * The DMA_TIMER_INTERVAL register controls the minimum DMA interrupt
47 * time span (iow, the maximum DMA interrupt rate) thus allowing for
50 * The chip datasheet does not mention a time unit for this value, so
51 * users wanting fine-grain control over the interrupt rate should
52 * determine the desired value through testing.
54 static u32 dma_interval = 0x00098968;
55 module_param(dma_interval, int, 0444);
56 MODULE_PARM_DESC(dma_interval, "Minimum time span for DMA interrupting host");
58 void tw686x_disable_channel(struct tw686x_dev *dev, unsigned int channel)
60 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
61 u32 dma_cmd = reg_read(dev, DMA_CMD);
63 dma_en &= ~BIT(channel);
64 dma_cmd &= ~BIT(channel);
66 /* Must remove it from pending too */
67 dev->pending_dma_en &= ~BIT(channel);
68 dev->pending_dma_cmd &= ~BIT(channel);
70 /* Stop DMA if no channels are enabled */
73 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en);
74 reg_write(dev, DMA_CMD, dma_cmd);
77 void tw686x_enable_channel(struct tw686x_dev *dev, unsigned int channel)
79 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
80 u32 dma_cmd = reg_read(dev, DMA_CMD);
82 dev->pending_dma_en |= dma_en | BIT(channel);
83 dev->pending_dma_cmd |= dma_cmd | DMA_CMD_ENABLE | BIT(channel);
87 * The purpose of this awful hack is to avoid enabling the DMA
88 * channels "too fast" which makes some TW686x devices very
89 * angry and freeze the CPU (see note 1).
91 static void tw686x_dma_delay(unsigned long data)
93 struct tw686x_dev *dev = (struct tw686x_dev *)data;
96 spin_lock_irqsave(&dev->lock, flags);
98 reg_write(dev, DMA_CHANNEL_ENABLE, dev->pending_dma_en);
99 reg_write(dev, DMA_CMD, dev->pending_dma_cmd);
100 dev->pending_dma_en = 0;
101 dev->pending_dma_cmd = 0;
103 spin_unlock_irqrestore(&dev->lock, flags);
106 static void tw686x_reset_channels(struct tw686x_dev *dev, unsigned int ch_mask)
110 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
111 dma_cmd = reg_read(dev, DMA_CMD);
114 * Save pending register status, the timer will
117 dev->pending_dma_en |= dma_en;
118 dev->pending_dma_cmd |= dma_cmd;
120 /* Disable the reset channels */
121 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en & ~ch_mask);
123 if ((dma_en & ~ch_mask) == 0) {
124 dev_dbg(&dev->pci_dev->dev, "reset: stopping DMA\n");
125 dma_cmd &= ~DMA_CMD_ENABLE;
127 reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask);
130 static irqreturn_t tw686x_irq(int irq, void *dev_id)
132 struct tw686x_dev *dev = (struct tw686x_dev *)dev_id;
133 unsigned int video_requests, audio_requests, reset_ch;
134 u32 fifo_status, fifo_signal, fifo_ov, fifo_bad, fifo_errors;
135 u32 int_status, dma_en, video_en, pb_status;
138 int_status = reg_read(dev, INT_STATUS); /* cleared on read */
139 fifo_status = reg_read(dev, VIDEO_FIFO_STATUS);
141 /* INT_STATUS does not include FIFO_STATUS errors! */
142 if (!int_status && !TW686X_FIFO_ERROR(fifo_status))
145 if (int_status & INT_STATUS_DMA_TOUT) {
146 dev_dbg(&dev->pci_dev->dev,
147 "DMA timeout. Resetting DMA for all channels\n");
152 spin_lock_irqsave(&dev->lock, flags);
153 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE);
154 spin_unlock_irqrestore(&dev->lock, flags);
156 video_en = dma_en & 0xff;
157 fifo_signal = ~(fifo_status & 0xff) & video_en;
158 fifo_ov = fifo_status >> 24;
159 fifo_bad = fifo_status >> 16;
161 /* Mask of channels with signal and FIFO errors */
162 fifo_errors = fifo_signal & (fifo_ov | fifo_bad);
165 pb_status = reg_read(dev, PB_STATUS);
167 /* Coalesce video frame/error events */
168 video_requests = (int_status & video_en) | fifo_errors;
169 audio_requests = (int_status & dma_en) >> 8;
172 tw686x_video_irq(dev, video_requests, pb_status,
173 fifo_status, &reset_ch);
175 tw686x_audio_irq(dev, audio_requests, pb_status);
179 spin_lock_irqsave(&dev->lock, flags);
180 tw686x_reset_channels(dev, reset_ch);
181 spin_unlock_irqrestore(&dev->lock, flags);
182 mod_timer(&dev->dma_delay_timer,
183 jiffies + msecs_to_jiffies(100));
189 static void tw686x_dev_release(struct v4l2_device *v4l2_dev)
191 struct tw686x_dev *dev = container_of(v4l2_dev, struct tw686x_dev,
195 for (ch = 0; ch < max_channels(dev); ch++)
196 v4l2_ctrl_handler_free(&dev->video_channels[ch].ctrl_handler);
198 v4l2_device_unregister(&dev->v4l2_dev);
200 kfree(dev->audio_channels);
201 kfree(dev->video_channels);
205 static int tw686x_probe(struct pci_dev *pci_dev,
206 const struct pci_device_id *pci_id)
208 struct tw686x_dev *dev;
211 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
214 dev->type = pci_id->driver_data;
215 sprintf(dev->name, "tw%04X", pci_dev->device);
217 dev->video_channels = kcalloc(max_channels(dev),
218 sizeof(*dev->video_channels), GFP_KERNEL);
219 if (!dev->video_channels) {
224 dev->audio_channels = kcalloc(max_channels(dev),
225 sizeof(*dev->audio_channels), GFP_KERNEL);
226 if (!dev->audio_channels) {
231 pr_info("%s: PCI %s, IRQ %d, MMIO 0x%lx\n", dev->name,
232 pci_name(pci_dev), pci_dev->irq,
233 (unsigned long)pci_resource_start(pci_dev, 0));
235 dev->pci_dev = pci_dev;
236 if (pci_enable_device(pci_dev)) {
241 pci_set_master(pci_dev);
242 err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
244 dev_err(&pci_dev->dev, "32-bit PCI DMA not supported\n");
249 err = pci_request_regions(pci_dev, dev->name);
251 dev_err(&pci_dev->dev, "unable to request PCI region\n");
255 dev->mmio = pci_ioremap_bar(pci_dev, 0);
257 dev_err(&pci_dev->dev, "unable to remap PCI region\n");
262 /* Reset all subsystems */
263 reg_write(dev, SYS_SOFT_RST, 0x0f);
266 reg_write(dev, SRST[0], 0x3f);
267 if (max_channels(dev) > 4)
268 reg_write(dev, SRST[1], 0x3f);
270 /* Disable the DMA engine */
271 reg_write(dev, DMA_CMD, 0);
272 reg_write(dev, DMA_CHANNEL_ENABLE, 0);
274 /* Enable DMA FIFO overflow and pointer check */
275 reg_write(dev, DMA_CONFIG, 0xffffff04);
276 reg_write(dev, DMA_CHANNEL_TIMEOUT, 0x140c8584);
277 reg_write(dev, DMA_TIMER_INTERVAL, dma_interval);
279 spin_lock_init(&dev->lock);
281 err = request_irq(pci_dev->irq, tw686x_irq, IRQF_SHARED,
284 dev_err(&pci_dev->dev, "unable to request interrupt\n");
288 setup_timer(&dev->dma_delay_timer,
289 tw686x_dma_delay, (unsigned long) dev);
292 * This must be set right before initializing v4l2_dev.
293 * It's used to release resources after the last handle
296 dev->v4l2_dev.release = tw686x_dev_release;
297 err = tw686x_video_init(dev);
299 dev_err(&pci_dev->dev, "can't register video\n");
303 err = tw686x_audio_init(dev);
305 dev_warn(&pci_dev->dev, "can't register audio\n");
307 pci_set_drvdata(pci_dev, dev);
311 free_irq(pci_dev->irq, dev);
313 pci_iounmap(pci_dev, dev->mmio);
315 pci_release_regions(pci_dev);
317 pci_disable_device(pci_dev);
319 kfree(dev->audio_channels);
321 kfree(dev->video_channels);
327 static void tw686x_remove(struct pci_dev *pci_dev)
329 struct tw686x_dev *dev = pci_get_drvdata(pci_dev);
332 /* This guarantees the IRQ handler is no longer running,
333 * which means we can kiss good-bye some resources.
335 free_irq(pci_dev->irq, dev);
337 tw686x_video_free(dev);
338 tw686x_audio_free(dev);
339 del_timer_sync(&dev->dma_delay_timer);
341 pci_iounmap(pci_dev, dev->mmio);
342 pci_release_regions(pci_dev);
343 pci_disable_device(pci_dev);
346 * Setting pci_dev to NULL allows to detect hardware is no longer
347 * available and will be used by vb2_ops. This is required because
348 * the device sometimes hot-unplugs itself as the result of a PCIe
350 * The lock is really important here.
352 spin_lock_irqsave(&dev->lock, flags);
354 spin_unlock_irqrestore(&dev->lock, flags);
357 * This calls tw686x_dev_release if it's the last reference.
358 * Otherwise, release is postponed until there are no users left.
360 v4l2_device_put(&dev->v4l2_dev);
364 * On TW6864 and TW6868, all channels share the pair of video DMA SG tables,
365 * with 10-bit start_idx and end_idx determining start and end of frame buffer
366 * for particular channel.
367 * TW6868 with all its 8 channels would be problematic (only 127 SG entries per
368 * channel) but we support only 4 channels on this chip anyway (the first
369 * 4 channels are driven with internal video decoder, the other 4 would require
370 * an external TW286x part).
372 * On TW6865 and TW6869, each channel has its own DMA SG table, with indexes
373 * starting with 0. Both chips have complete sets of internal video decoders
374 * (respectively 4 or 8-channel).
376 * All chips have separate SG tables for two video frames.
379 /* driver_data is number of A/V channels */
380 static const struct pci_device_id tw686x_pci_tbl[] = {
382 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6864),
386 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6865), /* not tested */
387 .driver_data = 4 | TYPE_SECOND_GEN
390 * TW6868 supports 8 A/V channels with an external TW2865 chip;
391 * not supported by the driver.
394 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6868), /* not tested */
398 PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, 0x6869),
399 .driver_data = 8 | TYPE_SECOND_GEN},
402 MODULE_DEVICE_TABLE(pci, tw686x_pci_tbl);
404 static struct pci_driver tw686x_pci_driver = {
406 .id_table = tw686x_pci_tbl,
407 .probe = tw686x_probe,
408 .remove = tw686x_remove,
410 module_pci_driver(tw686x_pci_driver);
412 MODULE_DESCRIPTION("Driver for video frame grabber cards based on Intersil/Techwell TW686[4589]");
413 MODULE_AUTHOR("Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>");
414 MODULE_AUTHOR("Krzysztof Ha?asa <khalasa@piap.pl>");
415 MODULE_LICENSE("GPL v2");