2 * Coda multi-standard codec IP - BIT processor functions
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
7 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/clk.h>
16 #include <linux/irqreturn.h>
17 #include <linux/kernel.h>
18 #include <linux/log2.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/videodev2.h>
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-fh.h>
27 #include <media/v4l2-mem2mem.h>
28 #include <media/videobuf2-v4l2.h>
29 #include <media/videobuf2-dma-contig.h>
30 #include <media/videobuf2-vmalloc.h>
34 #define CREATE_TRACE_POINTS
37 #define CODA_PARA_BUF_SIZE (10 * 1024)
38 #define CODA7_PS_BUF_SIZE 0x28000
39 #define CODA9_PS_SAVE_SIZE (512 * 1024)
41 #define CODA_DEFAULT_GAMMA 4096
42 #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
44 static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
46 static inline int coda_is_initialized(struct coda_dev *dev)
48 return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
51 static inline unsigned long coda_isbusy(struct coda_dev *dev)
53 return coda_read(dev, CODA_REG_BIT_BUSY);
56 static int coda_wait_timeout(struct coda_dev *dev)
58 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
60 while (coda_isbusy(dev)) {
61 if (time_after(jiffies, timeout))
67 static void coda_command_async(struct coda_ctx *ctx, int cmd)
69 struct coda_dev *dev = ctx->dev;
71 if (dev->devtype->product == CODA_960 ||
72 dev->devtype->product == CODA_7541) {
73 /* Restore context related registers to CODA */
74 coda_write(dev, ctx->bit_stream_param,
75 CODA_REG_BIT_BIT_STREAM_PARAM);
76 coda_write(dev, ctx->frm_dis_flg,
77 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
78 coda_write(dev, ctx->frame_mem_ctrl,
79 CODA_REG_BIT_FRAME_MEM_CTRL);
80 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
83 if (dev->devtype->product == CODA_960) {
84 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
85 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
88 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
90 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
91 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
92 coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
94 trace_coda_bit_run(ctx, cmd);
96 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
99 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
101 struct coda_dev *dev = ctx->dev;
104 coda_command_async(ctx, cmd);
105 ret = coda_wait_timeout(dev);
106 trace_coda_bit_done(ctx);
111 int coda_hw_reset(struct coda_ctx *ctx)
113 struct coda_dev *dev = ctx->dev;
114 unsigned long timeout;
121 idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
123 if (dev->devtype->product == CODA_960) {
124 timeout = jiffies + msecs_to_jiffies(100);
125 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
126 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
127 if (time_after(jiffies, timeout))
133 ret = reset_control_reset(dev->rstc);
137 if (dev->devtype->product == CODA_960)
138 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
139 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
140 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
141 ret = coda_wait_timeout(dev);
142 coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
147 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
149 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
150 struct coda_dev *dev = ctx->dev;
153 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
154 kfifo->out = (kfifo->in & ~kfifo->mask) |
155 (rd_ptr - ctx->bitstream.paddr);
156 if (kfifo->out > kfifo->in)
157 kfifo->out -= kfifo->mask + 1;
160 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
162 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
163 struct coda_dev *dev = ctx->dev;
166 rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
167 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
168 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
169 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
172 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
174 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
175 struct coda_dev *dev = ctx->dev;
178 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
179 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
182 static int coda_bitstream_pad(struct coda_ctx *ctx, u32 size)
190 buf = kmalloc(size, GFP_KERNEL);
194 coda_h264_filler_nal(size, buf);
195 n = kfifo_in(&ctx->bitstream_fifo, buf, size);
198 return (n < size) ? -ENOSPC : 0;
201 static int coda_bitstream_queue(struct coda_ctx *ctx,
202 struct vb2_v4l2_buffer *src_buf)
204 u32 src_size = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
207 n = kfifo_in(&ctx->bitstream_fifo,
208 vb2_plane_vaddr(&src_buf->vb2_buf, 0), src_size);
212 src_buf->sequence = ctx->qsequence++;
217 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
218 struct vb2_v4l2_buffer *src_buf)
220 unsigned long payload = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
223 if (coda_get_bitstream_payload(ctx) + payload + 512 >=
227 if (vb2_plane_vaddr(&src_buf->vb2_buf, 0) == NULL) {
228 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
232 /* Add zero padding before the first H.264 buffer, if it is too small */
233 if (ctx->qsequence == 0 && payload < 512 &&
234 ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
235 coda_bitstream_pad(ctx, 512 - payload);
237 ret = coda_bitstream_queue(ctx, src_buf);
239 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
242 /* Sync read pointer to device */
243 if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
244 coda_kfifo_sync_to_device_write(ctx);
251 void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list)
253 struct vb2_v4l2_buffer *src_buf;
254 struct coda_buffer_meta *meta;
258 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
261 while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
263 * Only queue a single JPEG into the bitstream buffer, except
264 * to increase payload over 512 bytes or if in hold state.
266 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
267 (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
270 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
272 /* Drop frames that do not start/end with a SOI/EOI markers */
273 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
274 !coda_jpeg_check_buffer(ctx, &src_buf->vb2_buf)) {
275 v4l2_err(&ctx->dev->v4l2_dev,
276 "dropping invalid JPEG frame %d\n",
278 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
280 struct v4l2_m2m_buffer *m2m_buf;
282 m2m_buf = container_of(src_buf,
283 struct v4l2_m2m_buffer,
285 list_add_tail(&m2m_buf->list, buffer_list);
287 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
292 /* Dump empty buffers */
293 if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) {
294 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
295 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
299 /* Buffer start position */
300 start = ctx->bitstream_fifo.kfifo.in &
301 ctx->bitstream_fifo.kfifo.mask;
303 if (coda_bitstream_try_queue(ctx, src_buf)) {
305 * Source buffer is queued in the bitstream ringbuffer;
306 * queue the timestamp and mark source buffer as done
308 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
310 meta = kmalloc(sizeof(*meta), GFP_KERNEL);
312 meta->sequence = src_buf->sequence;
313 meta->timecode = src_buf->timecode;
314 meta->timestamp = src_buf->vb2_buf.timestamp;
316 meta->end = ctx->bitstream_fifo.kfifo.in &
317 ctx->bitstream_fifo.kfifo.mask;
318 spin_lock_irqsave(&ctx->buffer_meta_lock,
320 list_add_tail(&meta->list,
321 &ctx->buffer_meta_list);
323 spin_unlock_irqrestore(&ctx->buffer_meta_lock,
326 trace_coda_bit_queue(ctx, src_buf, meta);
330 struct v4l2_m2m_buffer *m2m_buf;
332 m2m_buf = container_of(src_buf,
333 struct v4l2_m2m_buffer,
335 list_add_tail(&m2m_buf->list, buffer_list);
337 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
345 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
347 struct coda_dev *dev = ctx->dev;
349 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
351 /* If this context is currently running, update the hardware flag */
352 if ((dev->devtype->product == CODA_960) &&
354 (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
355 coda_write(dev, ctx->bit_stream_param,
356 CODA_REG_BIT_BIT_STREAM_PARAM);
360 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
362 struct coda_dev *dev = ctx->dev;
363 u32 *p = ctx->parabuf.vaddr;
365 if (dev->devtype->product == CODA_DX6)
368 p[index ^ 1] = value;
371 static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
372 struct coda_aux_buf *buf, size_t size,
375 return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
379 static void coda_free_framebuffers(struct coda_ctx *ctx)
383 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
384 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
387 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
388 struct coda_q_data *q_data, u32 fourcc)
390 struct coda_dev *dev = ctx->dev;
396 if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
397 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
398 width = round_up(q_data->width, 16);
399 height = round_up(q_data->height, 16);
401 width = round_up(q_data->width, 8);
402 height = q_data->height;
404 ysize = width * height;
406 /* Allocate frame buffers */
407 for (i = 0; i < ctx->num_internal_frames; i++) {
411 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
412 size = round_up(ysize, 4096) + ysize / 2;
414 size = ysize + ysize / 2;
415 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
416 dev->devtype->product != CODA_DX6)
418 name = kasprintf(GFP_KERNEL, "fb%d", i);
419 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
423 coda_free_framebuffers(ctx);
428 /* Register frame buffers in the parameter buffer */
429 for (i = 0; i < ctx->num_internal_frames; i++) {
430 u32 y, cb, cr, mvcol;
432 /* Start addresses of Y, Cb, Cr planes */
433 y = ctx->internal_frames[i].paddr;
435 cr = y + ysize + ysize/4;
436 mvcol = y + ysize + ysize/4 + ysize/4;
437 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
438 cb = round_up(cb, 4096);
439 mvcol = cb + ysize/2;
441 /* Packed 20-bit MSB of base addresses */
442 /* YYYYYCCC, CCyyyyyc, cccc.... */
443 y = (y & 0xfffff000) | cb >> 20;
444 cb = (cb & 0x000ff000) << 12;
446 coda_parabuf_write(ctx, i * 3 + 0, y);
447 coda_parabuf_write(ctx, i * 3 + 1, cb);
448 coda_parabuf_write(ctx, i * 3 + 2, cr);
450 /* mvcol buffer for h.264 */
451 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
452 dev->devtype->product != CODA_DX6)
453 coda_parabuf_write(ctx, 96 + i, mvcol);
456 /* mvcol buffer for mpeg4 */
457 if ((dev->devtype->product != CODA_DX6) &&
458 (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
459 coda_parabuf_write(ctx, 97, ctx->internal_frames[0].paddr +
460 ysize + ysize/4 + ysize/4);
465 static void coda_free_context_buffers(struct coda_ctx *ctx)
467 struct coda_dev *dev = ctx->dev;
469 coda_free_aux_buf(dev, &ctx->slicebuf);
470 coda_free_aux_buf(dev, &ctx->psbuf);
471 if (dev->devtype->product != CODA_DX6)
472 coda_free_aux_buf(dev, &ctx->workbuf);
473 coda_free_aux_buf(dev, &ctx->parabuf);
476 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
477 struct coda_q_data *q_data)
479 struct coda_dev *dev = ctx->dev;
483 if (!ctx->parabuf.vaddr) {
484 ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
485 CODA_PARA_BUF_SIZE, "parabuf");
490 if (dev->devtype->product == CODA_DX6)
493 if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
494 /* worst case slice size */
495 size = (DIV_ROUND_UP(q_data->width, 16) *
496 DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
497 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
503 if (!ctx->psbuf.vaddr && dev->devtype->product == CODA_7541) {
504 ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
505 CODA7_PS_BUF_SIZE, "psbuf");
510 if (!ctx->workbuf.vaddr) {
511 size = dev->devtype->workbuf_size;
512 if (dev->devtype->product == CODA_960 &&
513 q_data->fourcc == V4L2_PIX_FMT_H264)
514 size += CODA9_PS_SAVE_SIZE;
515 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
524 coda_free_context_buffers(ctx);
528 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf,
529 int header_code, u8 *header, int *size)
531 struct vb2_buffer *vb = &buf->vb2_buf;
532 struct coda_dev *dev = ctx->dev;
537 if (dev->devtype->product == CODA_960)
538 memset(vb2_plane_vaddr(vb, 0), 0, 64);
540 coda_write(dev, vb2_dma_contig_plane_dma_addr(vb, 0),
541 CODA_CMD_ENC_HEADER_BB_START);
542 bufsize = vb2_plane_size(vb, 0);
543 if (dev->devtype->product == CODA_960)
545 coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
546 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
547 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
549 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
553 if (dev->devtype->product == CODA_960) {
554 for (i = 63; i > 0; i--)
555 if (((char *)vb2_plane_vaddr(vb, 0))[i] != 0)
559 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
560 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
562 memcpy(header, vb2_plane_vaddr(vb, 0), *size);
567 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
571 size = round_up(size, 1024);
572 if (size > iram->remaining)
574 iram->remaining -= size;
576 ret = iram->next_paddr;
577 iram->next_paddr += size;
582 static void coda_setup_iram(struct coda_ctx *ctx)
584 struct coda_iram_info *iram_info = &ctx->iram_info;
585 struct coda_dev *dev = ctx->dev;
592 memset(iram_info, 0, sizeof(*iram_info));
593 iram_info->next_paddr = dev->iram.paddr;
594 iram_info->remaining = dev->iram.size;
596 if (!dev->iram.vaddr)
599 switch (dev->devtype->product) {
601 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
602 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
603 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
606 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
607 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
608 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
610 default: /* CODA_DX6 */
614 if (ctx->inst_type == CODA_INST_ENCODER) {
615 struct coda_q_data *q_data_src;
617 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
618 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
619 w128 = mb_width * 128;
622 /* Prioritize in case IRAM is too small for everything */
623 if (dev->devtype->product == CODA_7541) {
624 iram_info->search_ram_size = round_up(mb_width * 16 *
626 iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
627 iram_info->search_ram_size);
628 if (!iram_info->search_ram_paddr) {
629 pr_err("IRAM is smaller than the search ram size\n");
632 iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
636 /* Only H.264BP and H.263P3 are considered */
637 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
638 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
639 if (!iram_info->buf_dbk_c_use)
641 iram_info->axi_sram_use |= dbk_bits;
643 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
644 if (!iram_info->buf_bit_use)
646 iram_info->axi_sram_use |= bit_bits;
648 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
649 if (!iram_info->buf_ip_ac_dc_use)
651 iram_info->axi_sram_use |= ip_bits;
653 /* OVL and BTP disabled for encoder */
654 } else if (ctx->inst_type == CODA_INST_DECODER) {
655 struct coda_q_data *q_data_dst;
657 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
658 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
659 w128 = mb_width * 128;
661 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
662 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
663 if (!iram_info->buf_dbk_c_use)
665 iram_info->axi_sram_use |= dbk_bits;
667 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
668 if (!iram_info->buf_bit_use)
670 iram_info->axi_sram_use |= bit_bits;
672 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
673 if (!iram_info->buf_ip_ac_dc_use)
675 iram_info->axi_sram_use |= ip_bits;
677 /* OVL and BTP unused as there is no VC1 support yet */
681 if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
682 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
683 "IRAM smaller than needed\n");
685 if (dev->devtype->product == CODA_7541) {
686 /* TODO - Enabling these causes picture errors on CODA7541 */
687 if (ctx->inst_type == CODA_INST_DECODER) {
689 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
690 CODA7_USE_IP_ENABLE);
693 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
694 CODA7_USE_HOST_DBK_ENABLE |
695 CODA7_USE_IP_ENABLE |
696 CODA7_USE_DBK_ENABLE);
701 static u32 coda_supported_firmwares[] = {
702 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
703 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
704 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
707 static bool coda_firmware_supported(u32 vernum)
711 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
712 if (vernum == coda_supported_firmwares[i])
717 int coda_check_firmware(struct coda_dev *dev)
719 u16 product, major, minor, release;
723 ret = clk_prepare_enable(dev->clk_per);
727 ret = clk_prepare_enable(dev->clk_ahb);
731 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
732 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
733 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
734 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
735 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
736 if (coda_wait_timeout(dev)) {
737 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
742 if (dev->devtype->product == CODA_960) {
743 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
744 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
748 /* Check we are compatible with the loaded firmware */
749 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
750 product = CODA_FIRMWARE_PRODUCT(data);
751 major = CODA_FIRMWARE_MAJOR(data);
752 minor = CODA_FIRMWARE_MINOR(data);
753 release = CODA_FIRMWARE_RELEASE(data);
755 clk_disable_unprepare(dev->clk_per);
756 clk_disable_unprepare(dev->clk_ahb);
758 if (product != dev->devtype->product) {
759 v4l2_err(&dev->v4l2_dev,
760 "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
761 coda_product_name(dev->devtype->product),
762 coda_product_name(product), major, minor, release);
766 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
767 coda_product_name(product));
769 if (coda_firmware_supported(data)) {
770 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
771 major, minor, release);
773 v4l2_warn(&dev->v4l2_dev,
774 "Unsupported firmware version: %u.%u.%u\n",
775 major, minor, release);
781 clk_disable_unprepare(dev->clk_ahb);
783 clk_disable_unprepare(dev->clk_per);
788 static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
790 u32 cache_size, cache_config;
792 if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
793 /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
794 cache_size = 0x20262024;
795 cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
797 /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
798 cache_size = 0x02440243;
799 cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
801 coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
802 if (fourcc == V4L2_PIX_FMT_NV12 || fourcc == V4L2_PIX_FMT_YUYV) {
803 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
804 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
805 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
807 cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
808 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
809 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
811 coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
815 * Encoder context operations
818 static int coda_encoder_reqbufs(struct coda_ctx *ctx,
819 struct v4l2_requestbuffers *rb)
821 struct coda_q_data *q_data_src;
824 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
828 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
829 ret = coda_alloc_context_buffers(ctx, q_data_src);
833 coda_free_context_buffers(ctx);
839 static int coda_start_encoding(struct coda_ctx *ctx)
841 struct coda_dev *dev = ctx->dev;
842 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
843 struct coda_q_data *q_data_src, *q_data_dst;
844 u32 bitstream_buf, bitstream_size;
845 struct vb2_v4l2_buffer *buf;
846 int gamma, ret, value;
851 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
852 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
853 dst_fourcc = q_data_dst->fourcc;
855 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
856 bitstream_buf = vb2_dma_contig_plane_dma_addr(&buf->vb2_buf, 0);
857 bitstream_size = q_data_dst->sizeimage;
859 if (!coda_is_initialized(dev)) {
860 v4l2_err(v4l2_dev, "coda is not initialized.\n");
864 if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
865 if (!ctx->params.jpeg_qmat_tab[0])
866 ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
867 if (!ctx->params.jpeg_qmat_tab[1])
868 ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
869 coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
872 mutex_lock(&dev->coda_mutex);
874 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
875 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
876 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
877 switch (dev->devtype->product) {
879 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
880 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
883 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
886 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
887 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
891 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
892 CODA9_FRAME_TILED2LINEAR);
893 if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
894 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
895 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
896 ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
897 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
899 if (dev->devtype->product == CODA_DX6) {
900 /* Configure the coda */
901 coda_write(dev, dev->iram.paddr,
902 CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
905 /* Could set rotation here if needed */
907 switch (dev->devtype->product) {
909 value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
910 << CODADX6_PICWIDTH_OFFSET;
911 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
912 << CODA_PICHEIGHT_OFFSET;
915 if (dst_fourcc == V4L2_PIX_FMT_H264) {
916 value = (round_up(q_data_src->width, 16) &
917 CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
918 value |= (round_up(q_data_src->height, 16) &
919 CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
924 value = (q_data_src->width & CODA7_PICWIDTH_MASK)
925 << CODA7_PICWIDTH_OFFSET;
926 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
927 << CODA_PICHEIGHT_OFFSET;
929 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
930 if (dst_fourcc == V4L2_PIX_FMT_JPEG)
931 ctx->params.framerate = 0;
932 coda_write(dev, ctx->params.framerate,
933 CODA_CMD_ENC_SEQ_SRC_F_RATE);
935 ctx->params.codec_mode = ctx->codec->mode;
936 switch (dst_fourcc) {
937 case V4L2_PIX_FMT_MPEG4:
938 if (dev->devtype->product == CODA_960)
939 coda_write(dev, CODA9_STD_MPEG4,
940 CODA_CMD_ENC_SEQ_COD_STD);
942 coda_write(dev, CODA_STD_MPEG4,
943 CODA_CMD_ENC_SEQ_COD_STD);
944 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
946 case V4L2_PIX_FMT_H264:
947 if (dev->devtype->product == CODA_960)
948 coda_write(dev, CODA9_STD_H264,
949 CODA_CMD_ENC_SEQ_COD_STD);
951 coda_write(dev, CODA_STD_H264,
952 CODA_CMD_ENC_SEQ_COD_STD);
953 if (ctx->params.h264_deblk_enabled) {
954 value = ((ctx->params.h264_deblk_alpha &
955 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
956 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
957 ((ctx->params.h264_deblk_beta &
958 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
959 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
961 value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
963 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
965 case V4L2_PIX_FMT_JPEG:
966 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
967 coda_write(dev, ctx->params.jpeg_restart_interval,
968 CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
969 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
970 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
971 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
973 coda_jpeg_write_tables(ctx);
977 "dst format (0x%08x) invalid.\n", dst_fourcc);
983 * slice mode and GOP size registers are used for thumb size/offset
986 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
987 switch (ctx->params.slice_mode) {
988 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
991 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
992 value = (ctx->params.slice_max_mb &
993 CODA_SLICING_SIZE_MASK)
994 << CODA_SLICING_SIZE_OFFSET;
995 value |= (1 & CODA_SLICING_UNIT_MASK)
996 << CODA_SLICING_UNIT_OFFSET;
997 value |= 1 & CODA_SLICING_MODE_MASK;
999 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
1000 value = (ctx->params.slice_max_bits &
1001 CODA_SLICING_SIZE_MASK)
1002 << CODA_SLICING_SIZE_OFFSET;
1003 value |= (0 & CODA_SLICING_UNIT_MASK)
1004 << CODA_SLICING_UNIT_OFFSET;
1005 value |= 1 & CODA_SLICING_MODE_MASK;
1008 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
1009 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
1010 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
1013 if (ctx->params.bitrate) {
1014 /* Rate control enabled */
1015 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
1016 << CODA_RATECONTROL_BITRATE_OFFSET;
1017 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
1018 value |= (ctx->params.vbv_delay &
1019 CODA_RATECONTROL_INITIALDELAY_MASK)
1020 << CODA_RATECONTROL_INITIALDELAY_OFFSET;
1021 if (dev->devtype->product == CODA_960)
1022 value |= BIT(31); /* disable autoskip */
1026 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
1028 coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
1029 coda_write(dev, ctx->params.intra_refresh,
1030 CODA_CMD_ENC_SEQ_INTRA_REFRESH);
1032 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
1033 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
1037 if (dev->devtype->product == CODA_960)
1038 gamma = CODA9_DEFAULT_GAMMA;
1040 gamma = CODA_DEFAULT_GAMMA;
1042 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
1043 CODA_CMD_ENC_SEQ_RC_GAMMA);
1046 if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
1048 ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
1049 ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
1050 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
1052 if (dev->devtype->product == CODA_960) {
1053 if (ctx->params.h264_max_qp)
1054 value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
1055 if (CODA_DEFAULT_GAMMA > 0)
1056 value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
1058 if (CODA_DEFAULT_GAMMA > 0) {
1059 if (dev->devtype->product == CODA_DX6)
1060 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
1062 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
1064 if (ctx->params.h264_min_qp)
1065 value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
1066 if (ctx->params.h264_max_qp)
1067 value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
1069 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1071 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
1073 coda_setup_iram(ctx);
1075 if (dst_fourcc == V4L2_PIX_FMT_H264) {
1076 switch (dev->devtype->product) {
1078 value = FMO_SLICE_SAVE_BUF_SIZE << 7;
1079 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1082 coda_write(dev, ctx->iram_info.search_ram_paddr,
1083 CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1084 coda_write(dev, ctx->iram_info.search_ram_size,
1085 CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1088 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
1089 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
1093 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1095 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1099 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
1100 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
1104 ctx->initialized = 1;
1106 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
1107 if (dev->devtype->product == CODA_960)
1108 ctx->num_internal_frames = 4;
1110 ctx->num_internal_frames = 2;
1111 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
1113 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
1117 stride = q_data_src->bytesperline;
1119 ctx->num_internal_frames = 0;
1123 coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
1124 coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
1126 if (dev->devtype->product == CODA_7541) {
1127 coda_write(dev, q_data_src->bytesperline,
1128 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1130 if (dev->devtype->product != CODA_DX6) {
1131 coda_write(dev, ctx->iram_info.buf_bit_use,
1132 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1133 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1134 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1135 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1136 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1137 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1138 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1139 coda_write(dev, ctx->iram_info.buf_ovl_use,
1140 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1141 if (dev->devtype->product == CODA_960) {
1142 coda_write(dev, ctx->iram_info.buf_btp_use,
1143 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1145 coda9_set_frame_cache(ctx, q_data_src->fourcc);
1148 coda_write(dev, ctx->internal_frames[2].paddr,
1149 CODA9_CMD_SET_FRAME_SUBSAMP_A);
1150 coda_write(dev, ctx->internal_frames[3].paddr,
1151 CODA9_CMD_SET_FRAME_SUBSAMP_B);
1155 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
1157 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1161 /* Save stream headers */
1162 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1163 switch (dst_fourcc) {
1164 case V4L2_PIX_FMT_H264:
1166 * Get SPS in the first frame and copy it to an
1167 * intermediate buffer.
1169 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
1170 &ctx->vpu_header[0][0],
1171 &ctx->vpu_header_size[0]);
1176 * Get PPS in the first frame and copy it to an
1177 * intermediate buffer.
1179 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
1180 &ctx->vpu_header[1][0],
1181 &ctx->vpu_header_size[1]);
1186 * Length of H.264 headers is variable and thus it might not be
1187 * aligned for the coda to append the encoded frame. In that is
1188 * the case a filler NAL must be added to header 2.
1190 ctx->vpu_header_size[2] = coda_h264_padding(
1191 (ctx->vpu_header_size[0] +
1192 ctx->vpu_header_size[1]),
1193 ctx->vpu_header[2]);
1195 case V4L2_PIX_FMT_MPEG4:
1197 * Get VOS in the first frame and copy it to an
1198 * intermediate buffer
1200 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1201 &ctx->vpu_header[0][0],
1202 &ctx->vpu_header_size[0]);
1206 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1207 &ctx->vpu_header[1][0],
1208 &ctx->vpu_header_size[1]);
1212 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1213 &ctx->vpu_header[2][0],
1214 &ctx->vpu_header_size[2]);
1219 /* No more formats need to save headers at the moment */
1224 mutex_unlock(&dev->coda_mutex);
1228 static int coda_prepare_encode(struct coda_ctx *ctx)
1230 struct coda_q_data *q_data_src, *q_data_dst;
1231 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1232 struct coda_dev *dev = ctx->dev;
1234 int quant_param = 0;
1235 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1240 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1241 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1242 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1243 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1244 dst_fourcc = q_data_dst->fourcc;
1246 src_buf->sequence = ctx->osequence;
1247 dst_buf->sequence = ctx->osequence;
1250 force_ipicture = ctx->params.force_ipicture;
1252 ctx->params.force_ipicture = false;
1253 else if ((src_buf->sequence % ctx->params.gop_size) == 0)
1257 * Workaround coda firmware BUG that only marks the first
1258 * frame as IDR. This is a problem for some decoders that can't
1259 * recover when a frame is lost.
1261 if (!force_ipicture) {
1262 src_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1263 src_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1265 src_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1266 src_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1269 if (dev->devtype->product == CODA_960)
1270 coda_set_gdi_regs(ctx);
1273 * Copy headers in front of the first frame and forced I frames for
1274 * H.264 only. In MPEG4 they are already copied by the CODA.
1276 if (src_buf->sequence == 0 || force_ipicture) {
1277 pic_stream_buffer_addr =
1278 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0) +
1279 ctx->vpu_header_size[0] +
1280 ctx->vpu_header_size[1] +
1281 ctx->vpu_header_size[2];
1282 pic_stream_buffer_size = q_data_dst->sizeimage -
1283 ctx->vpu_header_size[0] -
1284 ctx->vpu_header_size[1] -
1285 ctx->vpu_header_size[2];
1286 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0),
1287 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1288 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1289 + ctx->vpu_header_size[0], &ctx->vpu_header[1][0],
1290 ctx->vpu_header_size[1]);
1291 memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
1292 + ctx->vpu_header_size[0] + ctx->vpu_header_size[1],
1293 &ctx->vpu_header[2][0], ctx->vpu_header_size[2]);
1295 pic_stream_buffer_addr =
1296 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
1297 pic_stream_buffer_size = q_data_dst->sizeimage;
1300 if (force_ipicture) {
1301 switch (dst_fourcc) {
1302 case V4L2_PIX_FMT_H264:
1303 quant_param = ctx->params.h264_intra_qp;
1305 case V4L2_PIX_FMT_MPEG4:
1306 quant_param = ctx->params.mpeg4_intra_qp;
1308 case V4L2_PIX_FMT_JPEG:
1312 v4l2_warn(&ctx->dev->v4l2_dev,
1313 "cannot set intra qp, fmt not supported\n");
1317 switch (dst_fourcc) {
1318 case V4L2_PIX_FMT_H264:
1319 quant_param = ctx->params.h264_inter_qp;
1321 case V4L2_PIX_FMT_MPEG4:
1322 quant_param = ctx->params.mpeg4_inter_qp;
1325 v4l2_warn(&ctx->dev->v4l2_dev,
1326 "cannot set inter qp, fmt not supported\n");
1332 if (ctx->params.rot_mode)
1333 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1334 coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1335 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1337 if (dev->devtype->product == CODA_960) {
1338 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1339 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1340 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1342 reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
1344 reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
1346 coda_write_base(ctx, q_data_src, src_buf, reg);
1348 coda_write(dev, force_ipicture << 1 & 0x2,
1349 CODA_CMD_ENC_PIC_OPTION);
1351 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1352 coda_write(dev, pic_stream_buffer_size / 1024,
1353 CODA_CMD_ENC_PIC_BB_SIZE);
1355 if (!ctx->streamon_out) {
1356 /* After streamoff on the output side, set stream end flag */
1357 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1358 coda_write(dev, ctx->bit_stream_param,
1359 CODA_REG_BIT_BIT_STREAM_PARAM);
1362 if (dev->devtype->product != CODA_DX6)
1363 coda_write(dev, ctx->iram_info.axi_sram_use,
1364 CODA7_REG_BIT_AXI_SRAM_USE);
1366 trace_coda_enc_pic_run(ctx, src_buf);
1368 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1373 static void coda_finish_encode(struct coda_ctx *ctx)
1375 struct vb2_v4l2_buffer *src_buf, *dst_buf;
1376 struct coda_dev *dev = ctx->dev;
1377 u32 wr_ptr, start_ptr;
1379 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1380 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1382 trace_coda_enc_pic_done(ctx, dst_buf);
1384 /* Get results from the coda */
1385 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1386 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1388 /* Calculate bytesused field */
1389 if (dst_buf->sequence == 0 ||
1390 src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
1391 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr +
1392 ctx->vpu_header_size[0] +
1393 ctx->vpu_header_size[1] +
1394 ctx->vpu_header_size[2]);
1396 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr);
1399 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1400 wr_ptr - start_ptr);
1402 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1403 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1405 if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1406 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
1407 dst_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
1409 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
1410 dst_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1413 dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp;
1414 dst_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1416 src_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1417 dst_buf->timecode = src_buf->timecode;
1419 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1421 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1422 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
1425 if (ctx->gopcounter < 0)
1426 ctx->gopcounter = ctx->params.gop_size - 1;
1428 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1429 "job finished: encoding frame (%d) (%s)\n",
1431 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
1432 "KEYFRAME" : "PFRAME");
1435 static void coda_seq_end_work(struct work_struct *work)
1437 struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1438 struct coda_dev *dev = ctx->dev;
1440 mutex_lock(&ctx->buffer_mutex);
1441 mutex_lock(&dev->coda_mutex);
1443 if (ctx->initialized == 0)
1446 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1447 "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
1449 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1450 v4l2_err(&dev->v4l2_dev,
1451 "CODA_COMMAND_SEQ_END failed\n");
1455 * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
1456 * from the output stream after the h.264 decoder has run. Resetting the
1457 * hardware after the decoder has finished seems to help.
1459 if (dev->devtype->product == CODA_960)
1462 kfifo_init(&ctx->bitstream_fifo,
1463 ctx->bitstream.vaddr, ctx->bitstream.size);
1465 coda_free_framebuffers(ctx);
1467 ctx->initialized = 0;
1470 mutex_unlock(&dev->coda_mutex);
1471 mutex_unlock(&ctx->buffer_mutex);
1474 static void coda_bit_release(struct coda_ctx *ctx)
1476 mutex_lock(&ctx->buffer_mutex);
1477 coda_free_framebuffers(ctx);
1478 coda_free_context_buffers(ctx);
1479 coda_free_bitstream_buffer(ctx);
1480 mutex_unlock(&ctx->buffer_mutex);
1483 const struct coda_context_ops coda_bit_encode_ops = {
1484 .queue_init = coda_encoder_queue_init,
1485 .reqbufs = coda_encoder_reqbufs,
1486 .start_streaming = coda_start_encoding,
1487 .prepare_run = coda_prepare_encode,
1488 .finish_run = coda_finish_encode,
1489 .seq_end_work = coda_seq_end_work,
1490 .release = coda_bit_release,
1494 * Decoder context operations
1497 static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
1498 struct coda_q_data *q_data)
1500 if (ctx->bitstream.vaddr)
1503 ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
1504 ctx->bitstream.vaddr = dma_alloc_wc(&ctx->dev->plat_dev->dev,
1505 ctx->bitstream.size,
1506 &ctx->bitstream.paddr, GFP_KERNEL);
1507 if (!ctx->bitstream.vaddr) {
1508 v4l2_err(&ctx->dev->v4l2_dev,
1509 "failed to allocate bitstream ringbuffer");
1512 kfifo_init(&ctx->bitstream_fifo,
1513 ctx->bitstream.vaddr, ctx->bitstream.size);
1518 static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
1520 if (ctx->bitstream.vaddr == NULL)
1523 dma_free_wc(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
1524 ctx->bitstream.vaddr, ctx->bitstream.paddr);
1525 ctx->bitstream.vaddr = NULL;
1526 kfifo_init(&ctx->bitstream_fifo, NULL, 0);
1529 static int coda_decoder_reqbufs(struct coda_ctx *ctx,
1530 struct v4l2_requestbuffers *rb)
1532 struct coda_q_data *q_data_src;
1535 if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
1539 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1540 ret = coda_alloc_context_buffers(ctx, q_data_src);
1543 ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
1545 coda_free_context_buffers(ctx);
1549 coda_free_bitstream_buffer(ctx);
1550 coda_free_context_buffers(ctx);
1556 static bool coda_reorder_enable(struct coda_ctx *ctx)
1558 const char * const *profile_names;
1559 const char * const *level_names;
1560 struct coda_dev *dev = ctx->dev;
1563 if (dev->devtype->product != CODA_7541 &&
1564 dev->devtype->product != CODA_960)
1567 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1570 if (ctx->codec->src_fourcc != V4L2_PIX_FMT_H264)
1573 profile = coda_h264_profile(ctx->params.h264_profile_idc);
1575 v4l2_warn(&dev->v4l2_dev, "Invalid H264 Profile: %d\n",
1576 ctx->params.h264_profile_idc);
1580 level = coda_h264_level(ctx->params.h264_level_idc);
1582 v4l2_warn(&dev->v4l2_dev, "Invalid H264 Level: %d\n",
1583 ctx->params.h264_level_idc);
1587 profile_names = v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_PROFILE);
1588 level_names = v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL);
1590 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "H264 Profile/Level: %s L%s\n",
1591 profile_names[profile], level_names[level]);
1593 /* Baseline profile does not support reordering */
1594 return profile > V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
1597 static int __coda_start_decoding(struct coda_ctx *ctx)
1599 struct coda_q_data *q_data_src, *q_data_dst;
1600 u32 bitstream_buf, bitstream_size;
1601 struct coda_dev *dev = ctx->dev;
1603 u32 src_fourcc, dst_fourcc;
1607 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1608 "Video Data Order Adapter: %s\n",
1609 ctx->use_vdoa ? "Enabled" : "Disabled");
1611 /* Start decoding */
1612 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1613 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1614 bitstream_buf = ctx->bitstream.paddr;
1615 bitstream_size = ctx->bitstream.size;
1616 src_fourcc = q_data_src->fourcc;
1617 dst_fourcc = q_data_dst->fourcc;
1619 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1621 /* Update coda bitstream read and write pointers from kfifo */
1622 coda_kfifo_sync_to_device_full(ctx);
1624 ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
1625 CODA9_FRAME_TILED2LINEAR);
1626 if (dst_fourcc == V4L2_PIX_FMT_NV12 || dst_fourcc == V4L2_PIX_FMT_YUYV)
1627 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
1628 if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
1629 ctx->frame_mem_ctrl |= (0x3 << 9) |
1630 ((ctx->use_vdoa) ? 0 : CODA9_FRAME_TILED2LINEAR);
1631 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
1633 ctx->display_idx = -1;
1634 ctx->frm_dis_flg = 0;
1635 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1637 coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1638 CODA_REG_BIT_BIT_STREAM_PARAM);
1640 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1641 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1643 if (coda_reorder_enable(ctx))
1644 val |= CODA_REORDER_ENABLE;
1645 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1646 val |= CODA_NO_INT_ENABLE;
1647 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1649 ctx->params.codec_mode = ctx->codec->mode;
1650 if (dev->devtype->product == CODA_960 &&
1651 src_fourcc == V4L2_PIX_FMT_MPEG4)
1652 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1654 ctx->params.codec_mode_aux = 0;
1655 if (src_fourcc == V4L2_PIX_FMT_H264) {
1656 if (dev->devtype->product == CODA_7541) {
1657 coda_write(dev, ctx->psbuf.paddr,
1658 CODA_CMD_DEC_SEQ_PS_BB_START);
1659 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1660 CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1662 if (dev->devtype->product == CODA_960) {
1663 coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1664 coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1667 if (dev->devtype->product != CODA_960)
1668 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1670 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1671 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1672 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1675 ctx->initialized = 1;
1677 /* Update kfifo out pointer from coda bitstream read pointer */
1678 coda_kfifo_sync_from_device(ctx);
1680 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1682 if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1683 v4l2_err(&dev->v4l2_dev,
1684 "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1685 coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1689 val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1690 if (dev->devtype->product == CODA_DX6) {
1691 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1692 height = val & CODADX6_PICHEIGHT_MASK;
1694 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1695 height = val & CODA7_PICHEIGHT_MASK;
1698 if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
1699 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1700 width, height, q_data_dst->bytesperline,
1701 q_data_dst->height);
1705 width = round_up(width, 16);
1706 height = round_up(height, 16);
1708 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1709 __func__, ctx->idx, width, height);
1711 ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1713 * If the VDOA is used, the decoder needs one additional frame,
1714 * because the frames are freed when the next frame is decoded.
1715 * Otherwise there are visible errors in the decoded frames (green
1716 * regions in displayed frames) and a broken order of frames (earlier
1717 * frames are sporadically displayed after later frames).
1720 ctx->num_internal_frames += 1;
1721 if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1722 v4l2_err(&dev->v4l2_dev,
1723 "not enough framebuffers to decode (%d < %d)\n",
1724 CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1728 if (src_fourcc == V4L2_PIX_FMT_H264) {
1732 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1733 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1735 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1736 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1737 q_data_dst->rect.width = width - q_data_dst->rect.left -
1738 (left_right & 0x3ff);
1739 q_data_dst->rect.height = height - q_data_dst->rect.top -
1740 (top_bottom & 0x3ff);
1743 ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1745 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1749 /* Tell the decoder how many frame buffers we allocated. */
1750 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1751 coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1753 if (dev->devtype->product != CODA_DX6) {
1754 /* Set secondary AXI IRAM */
1755 coda_setup_iram(ctx);
1757 coda_write(dev, ctx->iram_info.buf_bit_use,
1758 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1759 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1760 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1761 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1762 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1763 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1764 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1765 coda_write(dev, ctx->iram_info.buf_ovl_use,
1766 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1767 if (dev->devtype->product == CODA_960) {
1768 coda_write(dev, ctx->iram_info.buf_btp_use,
1769 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1771 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1772 coda9_set_frame_cache(ctx, dst_fourcc);
1776 if (src_fourcc == V4L2_PIX_FMT_H264) {
1777 coda_write(dev, ctx->slicebuf.paddr,
1778 CODA_CMD_SET_FRAME_SLICE_BB_START);
1779 coda_write(dev, ctx->slicebuf.size / 1024,
1780 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1783 if (dev->devtype->product == CODA_7541) {
1784 int max_mb_x = 1920 / 16;
1785 int max_mb_y = 1088 / 16;
1786 int max_mb_num = max_mb_x * max_mb_y;
1788 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1789 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1790 } else if (dev->devtype->product == CODA_960) {
1791 int max_mb_x = 1920 / 16;
1792 int max_mb_y = 1088 / 16;
1793 int max_mb_num = max_mb_x * max_mb_y;
1795 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1796 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1799 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1800 v4l2_err(&ctx->dev->v4l2_dev,
1801 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1808 static int coda_start_decoding(struct coda_ctx *ctx)
1810 struct coda_dev *dev = ctx->dev;
1813 mutex_lock(&dev->coda_mutex);
1814 ret = __coda_start_decoding(ctx);
1815 mutex_unlock(&dev->coda_mutex);
1820 static int coda_prepare_decode(struct coda_ctx *ctx)
1822 struct vb2_v4l2_buffer *dst_buf;
1823 struct coda_dev *dev = ctx->dev;
1824 struct coda_q_data *q_data_dst;
1825 struct coda_buffer_meta *meta;
1826 unsigned long flags;
1828 u32 reg_addr, reg_stride;
1830 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1831 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1833 /* Try to copy source buffer contents into the bitstream ringbuffer */
1834 mutex_lock(&ctx->bitstream_mutex);
1835 coda_fill_bitstream(ctx, NULL);
1836 mutex_unlock(&ctx->bitstream_mutex);
1838 if (coda_get_bitstream_payload(ctx) < 512 &&
1839 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1840 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1841 "bitstream payload: %d, skipping\n",
1842 coda_get_bitstream_payload(ctx));
1843 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1847 /* Run coda_start_decoding (again) if not yet initialized */
1848 if (!ctx->initialized) {
1849 int ret = __coda_start_decoding(ctx);
1852 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1853 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1856 ctx->initialized = 1;
1860 if (dev->devtype->product == CODA_960)
1861 coda_set_gdi_regs(ctx);
1863 if (ctx->use_vdoa &&
1864 ctx->display_idx >= 0 &&
1865 ctx->display_idx < ctx->num_internal_frames) {
1866 vdoa_device_run(ctx->vdoa,
1867 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0),
1868 ctx->internal_frames[ctx->display_idx].paddr);
1870 if (dev->devtype->product == CODA_960) {
1872 * The CODA960 seems to have an internal list of
1873 * buffers with 64 entries that includes the
1874 * registered frame buffers as well as the rotator
1877 * ROT_INDEX needs to be < 0x40, but >
1878 * ctx->num_internal_frames.
1881 CODA_MAX_FRAMEBUFFERS + dst_buf->vb2_buf.index,
1882 CODA9_CMD_DEC_PIC_ROT_INDEX);
1884 reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
1885 reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
1887 reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
1888 reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
1890 coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
1891 coda_write(dev, q_data_dst->bytesperline, reg_stride);
1893 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1896 coda_write(dev, rot_mode, CODA_CMD_DEC_PIC_ROT_MODE);
1898 switch (dev->devtype->product) {
1902 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1905 /* 'hardcode to use interrupt disable mode'? */
1906 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
1910 coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1912 coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1913 coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1915 if (dev->devtype->product != CODA_DX6)
1916 coda_write(dev, ctx->iram_info.axi_sram_use,
1917 CODA7_REG_BIT_AXI_SRAM_USE);
1919 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
1920 meta = list_first_entry_or_null(&ctx->buffer_meta_list,
1921 struct coda_buffer_meta, list);
1923 if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
1925 /* If this is the last buffer in the bitstream, add padding */
1926 if (meta->end == (ctx->bitstream_fifo.kfifo.in &
1927 ctx->bitstream_fifo.kfifo.mask)) {
1928 static unsigned char buf[512];
1931 /* Pad to multiple of 256 and then add 256 more */
1932 pad = ((0 - meta->end) & 0xff) + 256;
1934 memset(buf, 0xff, sizeof(buf));
1936 kfifo_in(&ctx->bitstream_fifo, buf, pad);
1939 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
1941 coda_kfifo_sync_to_device_full(ctx);
1943 /* Clear decode success flag */
1944 coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
1946 trace_coda_dec_pic_run(ctx, meta);
1948 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1953 static void coda_finish_decode(struct coda_ctx *ctx)
1955 struct coda_dev *dev = ctx->dev;
1956 struct coda_q_data *q_data_src;
1957 struct coda_q_data *q_data_dst;
1958 struct vb2_v4l2_buffer *dst_buf;
1959 struct coda_buffer_meta *meta;
1960 unsigned long payload;
1961 unsigned long flags;
1971 /* Update kfifo out pointer from coda bitstream read pointer */
1972 coda_kfifo_sync_from_device(ctx);
1975 * in stream-end mode, the read pointer can overshoot the write pointer
1976 * by up to 512 bytes
1978 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1979 if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
1980 kfifo_init(&ctx->bitstream_fifo,
1981 ctx->bitstream.vaddr, ctx->bitstream.size);
1984 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1985 src_fourcc = q_data_src->fourcc;
1987 val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
1989 pr_err("DEC_PIC_SUCCESS = %d\n", val);
1991 success = val & 0x1;
1993 v4l2_err(&dev->v4l2_dev, "decode failed\n");
1995 if (src_fourcc == V4L2_PIX_FMT_H264) {
1997 v4l2_err(&dev->v4l2_dev,
1998 "insufficient PS buffer space (%d bytes)\n",
2001 v4l2_err(&dev->v4l2_dev,
2002 "insufficient slice buffer space (%d bytes)\n",
2003 ctx->slicebuf.size);
2006 val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
2007 width = (val >> 16) & 0xffff;
2008 height = val & 0xffff;
2010 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
2012 /* frame crop information */
2013 if (src_fourcc == V4L2_PIX_FMT_H264) {
2017 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
2018 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
2020 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
2021 /* Keep current crop information */
2023 struct v4l2_rect *rect = &q_data_dst->rect;
2025 rect->left = left_right >> 16 & 0xffff;
2026 rect->top = top_bottom >> 16 & 0xffff;
2027 rect->width = width - rect->left -
2028 (left_right & 0xffff);
2029 rect->height = height - rect->top -
2030 (top_bottom & 0xffff);
2036 err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
2038 v4l2_err(&dev->v4l2_dev,
2039 "errors in %d macroblocks\n", err_mb);
2041 if (dev->devtype->product == CODA_7541) {
2042 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
2044 /* not enough bitstream data */
2045 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2046 "prescan failed: %d\n", val);
2052 /* Wait until the VDOA finished writing the previous display frame */
2053 if (ctx->use_vdoa &&
2054 ctx->display_idx >= 0 &&
2055 ctx->display_idx < ctx->num_internal_frames) {
2056 err_vdoa = vdoa_wait_for_completion(ctx->vdoa);
2059 ctx->frm_dis_flg = coda_read(dev,
2060 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
2062 /* The previous display frame was copied out and can be overwritten */
2063 if (ctx->display_idx >= 0 &&
2064 ctx->display_idx < ctx->num_internal_frames) {
2065 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
2066 coda_write(dev, ctx->frm_dis_flg,
2067 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
2071 * The index of the last decoded frame, not necessarily in
2072 * display order, and the index of the next display frame.
2073 * The latter could have been decoded in a previous run.
2075 decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
2076 display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
2078 if (decoded_idx == -1) {
2079 /* no frame was decoded, but we might have a display frame */
2080 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
2081 ctx->sequence_offset++;
2082 else if (ctx->display_idx < 0)
2084 } else if (decoded_idx == -2) {
2085 /* no frame was decoded, we still return remaining buffers */
2086 } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
2087 v4l2_err(&dev->v4l2_dev,
2088 "decoded frame index out of range: %d\n", decoded_idx);
2090 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
2091 val -= ctx->sequence_offset;
2092 spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
2093 if (!list_empty(&ctx->buffer_meta_list)) {
2094 meta = list_first_entry(&ctx->buffer_meta_list,
2095 struct coda_buffer_meta, list);
2096 list_del(&meta->list);
2098 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
2100 * Clamp counters to 16 bits for comparison, as the HW
2101 * counter rolls over at this point for h.264. This
2102 * may be different for other formats, but using 16 bits
2103 * should be enough to detect most errors and saves us
2104 * from doing different things based on the format.
2106 if ((val & 0xffff) != (meta->sequence & 0xffff)) {
2107 v4l2_err(&dev->v4l2_dev,
2108 "sequence number mismatch (%d(%d) != %d)\n",
2109 val, ctx->sequence_offset,
2112 ctx->frame_metas[decoded_idx] = *meta;
2115 spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
2116 v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
2117 memset(&ctx->frame_metas[decoded_idx], 0,
2118 sizeof(struct coda_buffer_meta));
2119 ctx->frame_metas[decoded_idx].sequence = val;
2120 ctx->sequence_offset++;
2123 trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
2125 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
2127 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
2129 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
2131 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
2133 ctx->frame_errors[decoded_idx] = err_mb;
2136 if (display_idx == -1) {
2138 * no more frames to be decoded, but there could still
2139 * be rotator output to dequeue
2142 } else if (display_idx == -3) {
2143 /* possibly prescan failure */
2144 } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
2145 v4l2_err(&dev->v4l2_dev,
2146 "presentation frame index out of range: %d\n",
2150 /* If a frame was copied out, return it */
2151 if (ctx->display_idx >= 0 &&
2152 ctx->display_idx < ctx->num_internal_frames) {
2153 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2154 dst_buf->sequence = ctx->osequence++;
2156 dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
2157 V4L2_BUF_FLAG_PFRAME |
2158 V4L2_BUF_FLAG_BFRAME);
2159 dst_buf->flags |= ctx->frame_types[ctx->display_idx];
2160 meta = &ctx->frame_metas[ctx->display_idx];
2161 dst_buf->timecode = meta->timecode;
2162 dst_buf->vb2_buf.timestamp = meta->timestamp;
2164 trace_coda_dec_rot_done(ctx, dst_buf, meta);
2166 switch (q_data_dst->fourcc) {
2167 case V4L2_PIX_FMT_YUYV:
2168 payload = width * height * 2;
2170 case V4L2_PIX_FMT_YUV420:
2171 case V4L2_PIX_FMT_YVU420:
2172 case V4L2_PIX_FMT_NV12:
2174 payload = width * height * 3 / 2;
2176 case V4L2_PIX_FMT_YUV422P:
2177 payload = width * height * 2;
2180 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload);
2182 if (ctx->frame_errors[ctx->display_idx] || err_vdoa)
2183 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
2185 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
2187 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2188 "job finished: decoding frame (%d) (%s)\n",
2190 (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
2191 "KEYFRAME" : "PFRAME");
2193 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2194 "job finished: no frame decoded\n");
2197 /* The rotator will copy the current display frame next time */
2198 ctx->display_idx = display_idx;
2201 static void coda_error_decode(struct coda_ctx *ctx)
2203 struct vb2_v4l2_buffer *dst_buf;
2206 * For now this only handles the case where we would deadlock with
2207 * userspace, i.e. userspace issued DEC_CMD_STOP and waits for EOS,
2208 * but after a failed decode run we would hold the context and wait for
2209 * userspace to queue more buffers.
2211 if (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))
2214 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2215 dst_buf->sequence = ctx->qsequence - 1;
2217 coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
2220 const struct coda_context_ops coda_bit_decode_ops = {
2221 .queue_init = coda_decoder_queue_init,
2222 .reqbufs = coda_decoder_reqbufs,
2223 .start_streaming = coda_start_decoding,
2224 .prepare_run = coda_prepare_decode,
2225 .finish_run = coda_finish_decode,
2226 .error_run = coda_error_decode,
2227 .seq_end_work = coda_seq_end_work,
2228 .release = coda_bit_release,
2231 irqreturn_t coda_irq_handler(int irq, void *data)
2233 struct coda_dev *dev = data;
2234 struct coda_ctx *ctx;
2236 /* read status register to attend the IRQ */
2237 coda_read(dev, CODA_REG_BIT_INT_STATUS);
2238 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
2239 CODA_REG_BIT_INT_CLEAR);
2241 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
2243 v4l2_err(&dev->v4l2_dev,
2244 "Instance released before the end of transaction\n");
2245 mutex_unlock(&dev->coda_mutex);
2249 trace_coda_bit_done(ctx);
2251 if (ctx->aborting) {
2252 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2253 "task has been aborted\n");
2256 if (coda_isbusy(ctx->dev)) {
2257 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2258 "coda is still busy!!!!\n");
2262 complete(&ctx->completion);