drivers/media/platform/imx-pxp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * i.MX Pixel Pipeline (PXP) mem-to-mem scaler/CSC/rotator driver
   4  *
   5  * Copyright (c) 2018 Pengutronix, Philipp Zabel
   6  *
   7  * based on vim2m
   8  *
   9  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  10  * Pawel Osciak, <pawel@osciak.com>
  11  * Marek Szyprowski, <m.szyprowski@samsung.com>
  12  */
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/sched.h>
  22 #include <linux/slab.h>
  23
  24 #include <linux/platform_device.h>
  25 #include <media/v4l2-mem2mem.h>
  26 #include <media/v4l2-device.h>
  27 #include <media/v4l2-ioctl.h>
  28 #include <media/v4l2-ctrls.h>
  29 #include <media/v4l2-event.h>
  30 #include <media/videobuf2-dma-contig.h>
  31
  32 #include "imx-pxp.h"
  33
  34 static unsigned int debug;
  35 module_param(debug, uint, 0644);
  36 MODULE_PARM_DESC(debug, "activates debug info");
  37
  38 #define MIN_W 8
  39 #define MIN_H 8
  40 #define MAX_W 4096
  41 #define MAX_H 4096
  42 #define ALIGN_W 3 /* 8x8 pixel blocks */
  43 #define ALIGN_H 3
  44
  45 /* Flags that indicate a format can be used for capture/output */
  46 #define MEM2MEM_CAPTURE (1 << 0)
  47 #define MEM2MEM_OUTPUT  (1 << 1)
  48
  49 #define MEM2MEM_NAME            "pxp"
  50
  51 /* Flags that indicate processing mode */
  52 #define MEM2MEM_HFLIP   (1 << 0)
  53 #define MEM2MEM_VFLIP   (1 << 1)
  54
  55 #define dprintk(dev, fmt, arg...) \
  56         v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
  57
  58 struct pxp_fmt {
  59         u32     fourcc;
  60         int     depth;
  61         /* Types the format can be used for */
  62         u32     types;
  63 };
  64
  65 static struct pxp_fmt formats[] = {
  66         {
  67                 .fourcc = V4L2_PIX_FMT_XBGR32,
  68                 .depth  = 32,
  69                 /* Both capture and output format */
  70                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  71         }, {
  72                 .fourcc = V4L2_PIX_FMT_ABGR32,
  73                 .depth  = 32,
  74                 /* Capture-only format */
  75                 .types  = MEM2MEM_CAPTURE,
  76         }, {
  77                 .fourcc = V4L2_PIX_FMT_BGR24,
  78                 .depth  = 24,
  79                 .types  = MEM2MEM_CAPTURE,
  80         }, {
  81                 .fourcc = V4L2_PIX_FMT_RGB565,
  82                 .depth  = 16,
  83                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  84         }, {
  85                 .fourcc = V4L2_PIX_FMT_RGB555,
  86                 .depth  = 16,
  87                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  88         }, {
  89                 .fourcc = V4L2_PIX_FMT_RGB444,
  90                 .depth  = 16,
  91                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  92         }, {
  93                 .fourcc = V4L2_PIX_FMT_YUV32,
  94                 .depth  = 32,
  95                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
  96         }, {
  97                 .fourcc = V4L2_PIX_FMT_UYVY,
  98                 .depth  = 16,
  99                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
 100         }, {
 101                 .fourcc = V4L2_PIX_FMT_YUYV,
 102                 .depth  = 16,
 103                 /* Output-only format */
 104                 .types  = MEM2MEM_OUTPUT,
 105         }, {
 106                 .fourcc = V4L2_PIX_FMT_VYUY,
 107                 .depth  = 16,
 108                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
 109         }, {
 110                 .fourcc = V4L2_PIX_FMT_YVYU,
 111                 .depth  = 16,
 112                 .types  = MEM2MEM_OUTPUT,
 113         }, {
 114                 .fourcc = V4L2_PIX_FMT_GREY,
 115                 .depth  = 8,
 116                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
 117         }, {
 118                 .fourcc = V4L2_PIX_FMT_Y4,
 119                 .depth  = 4,
 120                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
 121         }, {
 122                 .fourcc = V4L2_PIX_FMT_NV16,
 123                 .depth  = 16,
 124                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
 125         }, {
 126                 .fourcc = V4L2_PIX_FMT_NV12,
 127                 .depth  = 12,
 128                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
 129         }, {
 130                 .fourcc = V4L2_PIX_FMT_NV21,
 131                 .depth  = 12,
 132                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
 133         }, {
 134                 .fourcc = V4L2_PIX_FMT_NV61,
 135                 .depth  = 16,
 136                 .types  = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
 137         }, {
 138                 .fourcc = V4L2_PIX_FMT_YUV422P,
 139                 .depth  = 16,
 140                 .types  = MEM2MEM_OUTPUT,
 141         }, {
 142                 .fourcc = V4L2_PIX_FMT_YUV420,
 143                 .depth  = 12,
 144                 .types  = MEM2MEM_OUTPUT,
 145         },
 146 };
 147
 148 #define NUM_FORMATS ARRAY_SIZE(formats)
 149
 150 /* Per-queue, driver-specific private data */
 151 struct pxp_q_data {
 152         unsigned int            width;
 153         unsigned int            height;
 154         unsigned int            bytesperline;
 155         unsigned int            sizeimage;
 156         unsigned int            sequence;
 157         struct pxp_fmt          *fmt;
 158         enum v4l2_ycbcr_encoding ycbcr_enc;
 159         enum v4l2_quantization  quant;
 160 };
 161
 162 enum {
 163         V4L2_M2M_SRC = 0,
 164         V4L2_M2M_DST = 1,
 165 };
 166
 167 static struct pxp_fmt *find_format(struct v4l2_format *f)
 168 {
 169         struct pxp_fmt *fmt;
 170         unsigned int k;
 171
 172         for (k = 0; k < NUM_FORMATS; k++) {
 173                 fmt = &formats[k];
 174                 if (fmt->fourcc == f->fmt.pix.pixelformat)
 175                         break;
 176         }
 177
 178         if (k == NUM_FORMATS)
 179                 return NULL;
 180
 181         return &formats[k];
 182 }
 183
 184 struct pxp_dev {
 185         struct v4l2_device      v4l2_dev;
 186         struct video_device     vfd;
 187
 188         struct clk              *clk;
 189         void __iomem            *mmio;
 190
 191         atomic_t                num_inst;
 192         struct mutex            dev_mutex;
 193         spinlock_t              irqlock;
 194
 195         struct v4l2_m2m_dev     *m2m_dev;
 196 };
 197
 198 struct pxp_ctx {
 199         struct v4l2_fh          fh;
 200         struct pxp_dev  *dev;
 201
 202         struct v4l2_ctrl_handler hdl;
 203
 204         /* Abort requested by m2m */
 205         int                     aborting;
 206
 207         /* Processing mode */
 208         int                     mode;
 209         u8                      alpha_component;
 210
 211         enum v4l2_colorspace    colorspace;
 212         enum v4l2_xfer_func     xfer_func;
 213
 214         /* Source and destination queue data */
 215         struct pxp_q_data   q_data[2];
 216 };
 217
 218 static inline struct pxp_ctx *file2ctx(struct file *file)
 219 {
 220         return container_of(file->private_data, struct pxp_ctx, fh);
 221 }
 222
 223 static struct pxp_q_data *get_q_data(struct pxp_ctx *ctx,
 224                                          enum v4l2_buf_type type)
 225 {
 226         if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
 227                 return &ctx->q_data[V4L2_M2M_SRC];
 228         else
 229                 return &ctx->q_data[V4L2_M2M_DST];
 230 }
 231
 232 static u32 pxp_v4l2_pix_fmt_to_ps_format(u32 v4l2_pix_fmt)
 233 {
 234         switch (v4l2_pix_fmt) {
 235         case V4L2_PIX_FMT_XBGR32:  return BV_PXP_PS_CTRL_FORMAT__RGB888;
 236         case V4L2_PIX_FMT_RGB555:  return BV_PXP_PS_CTRL_FORMAT__RGB555;
 237         case V4L2_PIX_FMT_RGB444:  return BV_PXP_PS_CTRL_FORMAT__RGB444;
 238         case V4L2_PIX_FMT_RGB565:  return BV_PXP_PS_CTRL_FORMAT__RGB565;
 239         case V4L2_PIX_FMT_YUV32:   return BV_PXP_PS_CTRL_FORMAT__YUV1P444;
 240         case V4L2_PIX_FMT_UYVY:    return BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
 241         case V4L2_PIX_FMT_YUYV:    return BM_PXP_PS_CTRL_WB_SWAP |
 242                                           BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
 243         case V4L2_PIX_FMT_VYUY:    return BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
 244         case V4L2_PIX_FMT_YVYU:    return BM_PXP_PS_CTRL_WB_SWAP |
 245                                           BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
 246         case V4L2_PIX_FMT_GREY:    return BV_PXP_PS_CTRL_FORMAT__Y8;
 247         default:
 248         case V4L2_PIX_FMT_Y4:      return BV_PXP_PS_CTRL_FORMAT__Y4;
 249         case V4L2_PIX_FMT_NV16:    return BV_PXP_PS_CTRL_FORMAT__YUV2P422;
 250         case V4L2_PIX_FMT_NV12:    return BV_PXP_PS_CTRL_FORMAT__YUV2P420;
 251         case V4L2_PIX_FMT_NV21:    return BV_PXP_PS_CTRL_FORMAT__YVU2P420;
 252         case V4L2_PIX_FMT_NV61:    return BV_PXP_PS_CTRL_FORMAT__YVU2P422;
 253         case V4L2_PIX_FMT_YUV422P: return BV_PXP_PS_CTRL_FORMAT__YUV422;
 254         case V4L2_PIX_FMT_YUV420:  return BV_PXP_PS_CTRL_FORMAT__YUV420;
 255         }
 256 }
 257
 258 static u32 pxp_v4l2_pix_fmt_to_out_format(u32 v4l2_pix_fmt)
 259 {
 260         switch (v4l2_pix_fmt) {
 261         case V4L2_PIX_FMT_XBGR32:   return BV_PXP_OUT_CTRL_FORMAT__RGB888;
 262         case V4L2_PIX_FMT_ABGR32:   return BV_PXP_OUT_CTRL_FORMAT__ARGB8888;
 263         case V4L2_PIX_FMT_BGR24:    return BV_PXP_OUT_CTRL_FORMAT__RGB888P;
 264         /* Missing V4L2 pixel formats for ARGB1555 and ARGB4444 */
 265         case V4L2_PIX_FMT_RGB555:   return BV_PXP_OUT_CTRL_FORMAT__RGB555;
 266         case V4L2_PIX_FMT_RGB444:   return BV_PXP_OUT_CTRL_FORMAT__RGB444;
 267         case V4L2_PIX_FMT_RGB565:   return BV_PXP_OUT_CTRL_FORMAT__RGB565;
 268         case V4L2_PIX_FMT_YUV32:    return BV_PXP_OUT_CTRL_FORMAT__YUV1P444;
 269         case V4L2_PIX_FMT_UYVY:     return BV_PXP_OUT_CTRL_FORMAT__UYVY1P422;
 270         case V4L2_PIX_FMT_VYUY:     return BV_PXP_OUT_CTRL_FORMAT__VYUY1P422;
 271         case V4L2_PIX_FMT_GREY:     return BV_PXP_OUT_CTRL_FORMAT__Y8;
 272         default:
 273         case V4L2_PIX_FMT_Y4:       return BV_PXP_OUT_CTRL_FORMAT__Y4;
 274         case V4L2_PIX_FMT_NV16:     return BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
 275         case V4L2_PIX_FMT_NV12:     return BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
 276         case V4L2_PIX_FMT_NV61:     return BV_PXP_OUT_CTRL_FORMAT__YVU2P422;
 277         case V4L2_PIX_FMT_NV21:     return BV_PXP_OUT_CTRL_FORMAT__YVU2P420;
 278         }
 279 }
 280
 281 static bool pxp_v4l2_pix_fmt_is_yuv(u32 v4l2_pix_fmt)
 282 {
 283         switch (v4l2_pix_fmt) {
 284         case V4L2_PIX_FMT_YUV32:
 285         case V4L2_PIX_FMT_UYVY:
 286         case V4L2_PIX_FMT_YUYV:
 287         case V4L2_PIX_FMT_VYUY:
 288         case V4L2_PIX_FMT_YVYU:
 289         case V4L2_PIX_FMT_NV16:
 290         case V4L2_PIX_FMT_NV12:
 291         case V4L2_PIX_FMT_NV61:
 292         case V4L2_PIX_FMT_NV21:
 293         case V4L2_PIX_FMT_YUV420:
 294         case V4L2_PIX_FMT_YUV422P:
 295         case V4L2_PIX_FMT_GREY:
 296         case V4L2_PIX_FMT_Y4:
 297                 return true;
 298         default:
 299                 return false;
 300         }
 301 }
 302
 303 static void pxp_setup_csc(struct pxp_ctx *ctx)
 304 {
 305         struct pxp_dev *dev = ctx->dev;
 306         enum v4l2_ycbcr_encoding ycbcr_enc;
 307         enum v4l2_quantization quantization;
 308
 309         if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
 310             !pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
 311                 /*
 312                  * CSC1 YUV/YCbCr to RGB conversion is implemented as follows:
 313                  *
 314                  * |R|   |C0 0  C1|   |Y  + Yoffset |
 315                  * |G| = |C0 C3 C2| * |Cb + UVoffset|
 316                  * |B|   |C0 C4 0 |   |Cr + UVoffset|
 317                  *
 318                  * Results are clamped to 0..255.
 319                  *
 320                  * BT.601 limited range:
 321                  *
 322                  * |R|   |1.1644  0.0000  1.5960|   |Y  - 16 |
 323                  * |G| = |1.1644 -0.3917 -0.8129| * |Cb - 128|
 324                  * |B|   |1.1644  2.0172  0.0000|   |Cr - 128|
 325                  */
 326                 static const u32 csc1_coef_bt601_lim[3] = {
 327                         BM_PXP_CSC1_COEF0_YCBCR_MODE |
 328                         BF_PXP_CSC1_COEF0_C0(0x12a) |   /*  1.1641 (-0.03 %) */
 329                         BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
 330                         BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
 331                         BF_PXP_CSC1_COEF1_C1(0x198) |   /*  1.5938 (-0.23 %) */
 332                         BF_PXP_CSC1_COEF1_C4(0x204),    /*  2.0156 (-0.16 %) */
 333                         BF_PXP_CSC1_COEF2_C2(0x730) |   /* -0.8125 (+0.04 %) */
 334                         BF_PXP_CSC1_COEF2_C3(0x79c),    /* -0.3906 (+0.11 %) */
 335                 };
 336                 /*
 337                  * BT.601 full range:
 338                  *
 339                  * |R|   |1.0000  0.0000  1.4020|   |Y  + 0  |
 340                  * |G| = |1.0000 -0.3441 -0.7141| * |Cb - 128|
 341                  * |B|   |1.0000  1.7720  0.0000|   |Cr - 128|
 342                  */
 343                 static const u32 csc1_coef_bt601_full[3] = {
 344                         BM_PXP_CSC1_COEF0_YCBCR_MODE |
 345                         BF_PXP_CSC1_COEF0_C0(0x100) |   /*  1.0000 (+0.00 %) */
 346                         BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
 347                         BF_PXP_CSC1_COEF0_Y_OFFSET(0),
 348                         BF_PXP_CSC1_COEF1_C1(0x166) |   /*  1.3984 (-0.36 %) */
 349                         BF_PXP_CSC1_COEF1_C4(0x1c5),    /*  1.7695 (-0.25 %) */
 350                         BF_PXP_CSC1_COEF2_C2(0x74a) |   /* -0.7109 (+0.32 %) */
 351                         BF_PXP_CSC1_COEF2_C3(0x7a8),    /* -0.3438 (+0.04 %) */
 352                 };
 353                 /*
 354                  * Rec.709 limited range:
 355                  *
 356                  * |R|   |1.1644  0.0000  1.7927|   |Y  - 16 |
 357                  * |G| = |1.1644 -0.2132 -0.5329| * |Cb - 128|
 358                  * |B|   |1.1644  2.1124  0.0000|   |Cr - 128|
 359                  */
 360                 static const u32 csc1_coef_rec709_lim[3] = {
 361                         BM_PXP_CSC1_COEF0_YCBCR_MODE |
 362                         BF_PXP_CSC1_COEF0_C0(0x12a) |   /*  1.1641 (-0.03 %) */
 363                         BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
 364                         BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
 365                         BF_PXP_CSC1_COEF1_C1(0x1ca) |   /*  1.7891 (-0.37 %) */
 366                         BF_PXP_CSC1_COEF1_C4(0x21c),    /*  2.1094 (-0.30 %) */
 367                         BF_PXP_CSC1_COEF2_C2(0x778) |   /* -0.5312 (+0.16 %) */
 368                         BF_PXP_CSC1_COEF2_C3(0x7ca),    /* -0.2109 (+0.23 %) */
 369                 };
 370                 /*
 371                  * Rec.709 full range:
 372                  *
 373                  * |R|   |1.0000  0.0000  1.5748|   |Y  + 0  |
 374                  * |G| = |1.0000 -0.1873 -0.4681| * |Cb - 128|
 375                  * |B|   |1.0000  1.8556  0.0000|   |Cr - 128|
 376                  */
 377                 static const u32 csc1_coef_rec709_full[3] = {
 378                         BM_PXP_CSC1_COEF0_YCBCR_MODE |
 379                         BF_PXP_CSC1_COEF0_C0(0x100) |   /*  1.0000 (+0.00 %) */
 380                         BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
 381                         BF_PXP_CSC1_COEF0_Y_OFFSET(0),
 382                         BF_PXP_CSC1_COEF1_C1(0x193) |   /*  1.5742 (-0.06 %) */
 383                         BF_PXP_CSC1_COEF1_C4(0x1db),    /*  1.8555 (-0.01 %) */
 384                         BF_PXP_CSC1_COEF2_C2(0x789) |   /* -0.4648 (+0.33 %) */
 385                         BF_PXP_CSC1_COEF2_C3(0x7d1),    /* -0.1836 (+0.37 %) */
 386                 };
 387                 /*
 388                  * BT.2020 limited range:
 389                  *
 390                  * |R|   |1.1644  0.0000  1.6787|   |Y  - 16 |
 391                  * |G| = |1.1644 -0.1874 -0.6505| * |Cb - 128|
 392                  * |B|   |1.1644  2.1418  0.0000|   |Cr - 128|
 393                  */
 394                 static const u32 csc1_coef_bt2020_lim[3] = {
 395                         BM_PXP_CSC1_COEF0_YCBCR_MODE |
 396                         BF_PXP_CSC1_COEF0_C0(0x12a) |   /*  1.1641 (-0.03 %) */
 397                         BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
 398                         BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
 399                         BF_PXP_CSC1_COEF1_C1(0x1ad) |   /*  1.6758 (-0.29 %) */
 400                         BF_PXP_CSC1_COEF1_C4(0x224),    /*  2.1406 (-0.11 %) */
 401                         BF_PXP_CSC1_COEF2_C2(0x75a) |   /* -0.6484 (+0.20 %) */
 402                         BF_PXP_CSC1_COEF2_C3(0x7d1),    /* -0.1836 (+0.38 %) */
 403                 };
 404                 /*
 405                  * BT.2020 full range:
 406                  *
 407                  * |R|   |1.0000  0.0000  1.4746|   |Y  + 0  |
 408                  * |G| = |1.0000 -0.1646 -0.5714| * |Cb - 128|
 409                  * |B|   |1.0000  1.8814  0.0000|   |Cr - 128|
 410                  */
 411                 static const u32 csc1_coef_bt2020_full[3] = {
 412                         BM_PXP_CSC1_COEF0_YCBCR_MODE |
 413                         BF_PXP_CSC1_COEF0_C0(0x100) |   /*  1.0000 (+0.00 %) */
 414                         BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
 415                         BF_PXP_CSC1_COEF0_Y_OFFSET(0),
 416                         BF_PXP_CSC1_COEF1_C1(0x179) |   /*  1.4727 (-0.19 %) */
 417                         BF_PXP_CSC1_COEF1_C4(0x1e1),    /*  1.8789 (-0.25 %) */
 418                         BF_PXP_CSC1_COEF2_C2(0x76e) |   /* -0.5703 (+0.11 %) */
 419                         BF_PXP_CSC1_COEF2_C3(0x7d6),    /* -0.1641 (+0.05 %) */
 420                 };
 421                 /*
 422                  * SMPTE 240m limited range:
 423                  *
 424                  * |R|   |1.1644  0.0000  1.7937|   |Y  - 16 |
 425                  * |G| = |1.1644 -0.2565 -0.5427| * |Cb - 128|
 426                  * |B|   |1.1644  2.0798  0.0000|   |Cr - 128|
 427                  */
 428                 static const u32 csc1_coef_smpte240m_lim[3] = {
 429                         BM_PXP_CSC1_COEF0_YCBCR_MODE |
 430                         BF_PXP_CSC1_COEF0_C0(0x12a) |   /*  1.1641 (-0.03 %) */
 431                         BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
 432                         BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
 433                         BF_PXP_CSC1_COEF1_C1(0x1cb) |   /*  1.7930 (-0.07 %) */
 434                         BF_PXP_CSC1_COEF1_C4(0x214),    /*  2.0781 (-0.17 %) */
 435                         BF_PXP_CSC1_COEF2_C2(0x776) |   /* -0.5391 (+0.36 %) */
 436                         BF_PXP_CSC1_COEF2_C3(0x7bf),    /* -0.2539 (+0.26 %) */
 437                 };
 438                 /*
 439                  * SMPTE 240m full range:
 440                  *
 441                  * |R|   |1.0000  0.0000  1.5756|   |Y  + 0  |
 442                  * |G| = |1.0000 -0.2253 -0.4767| * |Cb - 128|
 443                  * |B|   |1.0000  1.8270  0.0000|   |Cr - 128|
 444                  */
 445                 static const u32 csc1_coef_smpte240m_full[3] = {
 446                         BM_PXP_CSC1_COEF0_YCBCR_MODE |
 447                         BF_PXP_CSC1_COEF0_C0(0x100) |   /*  1.0000 (+0.00 %) */
 448                         BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
 449                         BF_PXP_CSC1_COEF0_Y_OFFSET(0),
 450                         BF_PXP_CSC1_COEF1_C1(0x193) |   /*  1.5742 (-0.14 %) */
 451                         BF_PXP_CSC1_COEF1_C4(0x1d3),    /*  1.8242 (-0.28 %) */
 452                         BF_PXP_CSC1_COEF2_C2(0x786) |   /* -0.4766 (+0.01 %) */
 453                         BF_PXP_CSC1_COEF2_C3(0x7c7),    /* -0.2227 (+0.26 %) */
 454                 };
 455                 const u32 *csc1_coef;
 456
 457                 ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
 458                 quantization = ctx->q_data[V4L2_M2M_SRC].quant;
 459
 460                 if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
 461                         if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
 462                                 csc1_coef = csc1_coef_bt601_full;
 463                         else
 464                                 csc1_coef = csc1_coef_bt601_lim;
 465                 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
 466                         if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
 467                                 csc1_coef = csc1_coef_rec709_full;
 468                         else
 469                                 csc1_coef = csc1_coef_rec709_lim;
 470                 } else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
 471                         if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
 472                                 csc1_coef = csc1_coef_bt2020_full;
 473                         else
 474                                 csc1_coef = csc1_coef_bt2020_lim;
 475                 } else {
 476                         if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
 477                                 csc1_coef = csc1_coef_smpte240m_full;
 478                         else
 479                                 csc1_coef = csc1_coef_smpte240m_lim;
 480                 }
 481
 482                 writel(csc1_coef[0], dev->mmio + HW_PXP_CSC1_COEF0);
 483                 writel(csc1_coef[1], dev->mmio + HW_PXP_CSC1_COEF1);
 484                 writel(csc1_coef[2], dev->mmio + HW_PXP_CSC1_COEF2);
 485         } else {
 486                 writel(BM_PXP_CSC1_COEF0_BYPASS, dev->mmio + HW_PXP_CSC1_COEF0);
 487         }
 488
 489         if (!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
 490             pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
 491                 /*
 492                  * CSC2 RGB to YUV/YCbCr conversion is implemented as follows:
 493                  *
 494                  * |Y |   |A1 A2 A3|   |R|   |D1|
 495                  * |Cb| = |B1 B2 B3| * |G| + |D2|
 496                  * |Cr|   |C1 C2 C3|   |B|   |D3|
 497                  *
 498                  * Results are clamped to 0..255.
 499                  *
 500                  * BT.601 limited range:
 501                  *
 502                  * |Y |   | 0.2568  0.5041  0.0979|   |R|   |16 |
 503                  * |Cb| = |-0.1482 -0.2910  0.4392| * |G| + |128|
 504                  * |Cr|   | 0.4392  0.4392 -0.3678|   |B|   |128|
 505                  */
 506                 static const u32 csc2_coef_bt601_lim[6] = {
 507                         BF_PXP_CSC2_COEF0_A2(0x081) |   /*  0.5039 (-0.02 %) */
 508                         BF_PXP_CSC2_COEF0_A1(0x041),    /*  0.2539 (-0.29 %) */
 509                         BF_PXP_CSC2_COEF1_B1(0x7db) |   /* -0.1445 (+0.37 %) */
 510                         BF_PXP_CSC2_COEF1_A3(0x019),    /*  0.0977 (-0.02 %) */
 511                         BF_PXP_CSC2_COEF2_B3(0x070) |   /*  0.4375 (-0.17 %) */
 512                         BF_PXP_CSC2_COEF2_B2(0x7b6),    /* -0.2891 (+0.20 %) */
 513                         BF_PXP_CSC2_COEF3_C2(0x7a2) |   /* -0.3672 (+0.06 %) */
 514                         BF_PXP_CSC2_COEF3_C1(0x070),    /*  0.4375 (-0.17 %) */
 515                         BF_PXP_CSC2_COEF4_D1(16) |
 516                         BF_PXP_CSC2_COEF4_C3(0x7ee),    /* -0.0703 (+0.11 %) */
 517                         BF_PXP_CSC2_COEF5_D3(128) |
 518                         BF_PXP_CSC2_COEF5_D2(128),
 519                 };
 520                 /*
 521                  * BT.601 full range:
 522                  *
 523                  * |Y |   | 0.2990  0.5870  0.1140|   |R|   |0  |
 524                  * |Cb| = |-0.1687 -0.3313  0.5000| * |G| + |128|
 525                  * |Cr|   | 0.5000  0.5000 -0.4187|   |B|   |128|
 526                  */
 527                 static const u32 csc2_coef_bt601_full[6] = {
 528                         BF_PXP_CSC2_COEF0_A2(0x096) |   /*  0.5859 (-0.11 %) */
 529                         BF_PXP_CSC2_COEF0_A1(0x04c),    /*  0.2969 (-0.21 %) */
 530                         BF_PXP_CSC2_COEF1_B1(0x7d5) |   /* -0.1680 (+0.07 %) */
 531                         BF_PXP_CSC2_COEF1_A3(0x01d),    /*  0.1133 (-0.07 %) */
 532                         BF_PXP_CSC2_COEF2_B3(0x080) |   /*  0.5000 (+0.00 %) */
 533                         BF_PXP_CSC2_COEF2_B2(0x7ac),    /* -0.3281 (+0.32 %) */
 534                         BF_PXP_CSC2_COEF3_C2(0x795) |   /* -0.4180 (+0.07 %) */
 535                         BF_PXP_CSC2_COEF3_C1(0x080),    /*  0.5000 (+0.00 %) */
 536                         BF_PXP_CSC2_COEF4_D1(0) |
 537                         BF_PXP_CSC2_COEF4_C3(0x7ec),    /* -0.0781 (+0.32 %) */
 538                         BF_PXP_CSC2_COEF5_D3(128) |
 539                         BF_PXP_CSC2_COEF5_D2(128),
 540                 };
 541                 /*
 542                  * Rec.709 limited range:
 543                  *
 544                  * |Y |   | 0.1826  0.6142  0.0620|   |R|   |16 |
 545                  * |Cb| = |-0.1007 -0.3385  0.4392| * |G| + |128|
 546                  * |Cr|   | 0.4392  0.4392 -0.3990|   |B|   |128|
 547                  */
 548                 static const u32 csc2_coef_rec709_lim[6] = {
 549                         BF_PXP_CSC2_COEF0_A2(0x09d) |   /*  0.6133 (-0.09 %) */
 550                         BF_PXP_CSC2_COEF0_A1(0x02e),    /*  0.1797 (-0.29 %) */
 551                         BF_PXP_CSC2_COEF1_B1(0x7e7) |   /* -0.0977 (+0.30 %) */
 552                         BF_PXP_CSC2_COEF1_A3(0x00f),    /*  0.0586 (-0.34 %) */
 553                         BF_PXP_CSC2_COEF2_B3(0x070) |   /*  0.4375 (-0.17 %) */
 554                         BF_PXP_CSC2_COEF2_B2(0x7aa),    /* -0.3359 (+0.26 %) */
 555                         BF_PXP_CSC2_COEF3_C2(0x79a) |   /* -0.3984 (+0.05 %) */
 556                         BF_PXP_CSC2_COEF3_C1(0x070),    /*  0.4375 (-0.17 %) */
 557                         BF_PXP_CSC2_COEF4_D1(16) |
 558                         BF_PXP_CSC2_COEF4_C3(0x7f6),    /* -0.0391 (+0.12 %) */
 559                         BF_PXP_CSC2_COEF5_D3(128) |
 560                         BF_PXP_CSC2_COEF5_D2(128),
 561                 };
 562                 /*
 563                  * Rec.709 full range:
 564                  *
 565                  * |Y |   | 0.2126  0.7152  0.0722|   |R|   |0  |
 566                  * |Cb| = |-0.1146 -0.3854  0.5000| * |G| + |128|
 567                  * |Cr|   | 0.5000  0.5000 -0.4542|   |B|   |128|
 568                  */
 569                 static const u32 csc2_coef_rec709_full[6] = {
 570                         BF_PXP_CSC2_COEF0_A2(0x0b7) |   /*  0.7148 (-0.04 %) */
 571                         BF_PXP_CSC2_COEF0_A1(0x036),    /*  0.2109 (-0.17 %) */
 572                         BF_PXP_CSC2_COEF1_B1(0x7e3) |   /* -0.1133 (+0.13 %) */
 573                         BF_PXP_CSC2_COEF1_A3(0x012),    /*  0.0703 (-0.19 %) */
 574                         BF_PXP_CSC2_COEF2_B3(0x080) |   /*  0.5000 (+0.00 %) */
 575                         BF_PXP_CSC2_COEF2_B2(0x79e),    /* -0.3828 (+0.26 %) */
 576                         BF_PXP_CSC2_COEF3_C2(0x78c) |   /* -0.4531 (+0.11 %) */
 577                         BF_PXP_CSC2_COEF3_C1(0x080),    /*  0.5000 (+0.00 %) */
 578                         BF_PXP_CSC2_COEF4_D1(0) |
 579                         BF_PXP_CSC2_COEF4_C3(0x7f5),    /* -0.0430 (+0.28 %) */
 580                         BF_PXP_CSC2_COEF5_D3(128) |
 581                         BF_PXP_CSC2_COEF5_D2(128),
 582                 };
 583                 /*
 584                  * BT.2020 limited range:
 585                  *
 586                  * |Y |   | 0.2256  0.5823  0.0509|   |R|   |16 |
 587                  * |Cb| = |-0.1226 -0.3166  0.4392| * |G| + |128|
 588                  * |Cr|   | 0.4392  0.4392 -0.4039|   |B|   |128|
 589                  */
 590                 static const u32 csc2_coef_bt2020_lim[6] = {
 591                         BF_PXP_CSC2_COEF0_A2(0x095) |   /*  0.5820 (-0.03 %) */
 592                         BF_PXP_CSC2_COEF0_A1(0x039),    /*  0.2227 (-0.30 %) */
 593                         BF_PXP_CSC2_COEF1_B1(0x7e1) |   /* -0.1211 (+0.15 %) */
 594                         BF_PXP_CSC2_COEF1_A3(0x00d),    /*  0.0508 (-0.01 %) */
 595                         BF_PXP_CSC2_COEF2_B3(0x070) |   /*  0.4375 (-0.17 %) */
 596                         BF_PXP_CSC2_COEF2_B2(0x7af),    /* -0.3164 (+0.02 %) */
 597                         BF_PXP_CSC2_COEF3_C2(0x799) |   /* -0.4023 (+0.16 %) */
 598                         BF_PXP_CSC2_COEF3_C1(0x070),    /*  0.4375 (-0.17 %) */
 599                         BF_PXP_CSC2_COEF4_D1(16) |
 600                         BF_PXP_CSC2_COEF4_C3(0x7f7),    /* -0.0352 (+0.02 %) */
 601                         BF_PXP_CSC2_COEF5_D3(128) |
 602                         BF_PXP_CSC2_COEF5_D2(128),
 603                 };
 604                 /*
 605                  * BT.2020 full range:
 606                  *
 607                  * |Y |   | 0.2627  0.6780  0.0593|   |R|   |0  |
 608                  * |Cb| = |-0.1396 -0.3604  0.5000| * |G| + |128|
 609                  * |Cr|   | 0.5000  0.5000 -0.4598|   |B|   |128|
 610                  */
 611                 static const u32 csc2_coef_bt2020_full[6] = {
 612                         BF_PXP_CSC2_COEF0_A2(0x0ad) |   /*  0.6758 (-0.22 %) */
 613                         BF_PXP_CSC2_COEF0_A1(0x043),    /*  0.2617 (-0.10 %) */
 614                         BF_PXP_CSC2_COEF1_B1(0x7dd) |   /* -0.1367 (+0.29 %) */
 615                         BF_PXP_CSC2_COEF1_A3(0x00f),    /*  0.0586 (-0.07 %) */
 616                         BF_PXP_CSC2_COEF2_B3(0x080) |   /*  0.5000 (+0.00 %) */
 617                         BF_PXP_CSC2_COEF2_B2(0x7a4),    /* -0.3594 (+0.10 %) */
 618                         BF_PXP_CSC2_COEF3_C2(0x78b) |   /* -0.4570 (+0.28 %) */
 619                         BF_PXP_CSC2_COEF3_C1(0x080),    /*  0.5000 (+0.00 %) */
 620                         BF_PXP_CSC2_COEF4_D1(0) |
 621                         BF_PXP_CSC2_COEF4_C3(0x7f6),    /* -0.0391 (+0.11 %) */
 622                         BF_PXP_CSC2_COEF5_D3(128) |
 623                         BF_PXP_CSC2_COEF5_D2(128),
 624                 };
 625                 /*
 626                  * SMPTE 240m limited range:
 627                  *
 628                  * |Y |   | 0.1821  0.6020  0.0747|   |R|   |16 |
 629                  * |Cb| = |-0.1019 -0.3373  0.4392| * |G| + |128|
 630                  * |Cr|   | 0.4392  0.4392 -0.3909|   |B|   |128|
 631                  */
 632                 static const u32 csc2_coef_smpte240m_lim[6] = {
 633                         BF_PXP_CSC2_COEF0_A2(0x09a) |   /*  0.6016 (-0.05 %) */
 634                         BF_PXP_CSC2_COEF0_A1(0x02e),    /*  0.1797 (-0.24 %) */
 635                         BF_PXP_CSC2_COEF1_B1(0x7e6) |   /* -0.1016 (+0.03 %) */
 636                         BF_PXP_CSC2_COEF1_A3(0x013),    /*  0.0742 (-0.05 %) */
 637                         BF_PXP_CSC2_COEF2_B3(0x070) |   /*  0.4375 (-0.17 %) */
 638                         BF_PXP_CSC2_COEF2_B2(0x7aa),    /* -0.3359 (+0.14 %) */
 639                         BF_PXP_CSC2_COEF3_C2(0x79c) |   /* -0.3906 (+0.03 %) */
 640                         BF_PXP_CSC2_COEF3_C1(0x070),    /*  0.4375 (-0.17 %) */
 641                         BF_PXP_CSC2_COEF4_D1(16) |
 642                         BF_PXP_CSC2_COEF4_C3(0x7f4),    /* -0.0469 (+0.14 %) */
 643                         BF_PXP_CSC2_COEF5_D3(128) |
 644                         BF_PXP_CSC2_COEF5_D2(128),
 645                 };
 646                 /*
 647                  * SMPTE 240m full range:
 648                  *
 649                  * |Y |   | 0.2120  0.7010  0.0870|   |R|   |0  |
 650                  * |Cb| = |-0.1160 -0.3840  0.5000| * |G| + |128|
 651                  * |Cr|   | 0.5000  0.5000 -0.4450|   |B|   |128|
 652                  */
 653                 static const u32 csc2_coef_smpte240m_full[6] = {
 654                         BF_PXP_CSC2_COEF0_A2(0x0b3) |   /*  0.6992 (-0.18 %) */
 655                         BF_PXP_CSC2_COEF0_A1(0x036),    /*  0.2109 (-0.11 %) */
 656                         BF_PXP_CSC2_COEF1_B1(0x7e3) |   /* -0.1133 (+0.27 %) */
 657                         BF_PXP_CSC2_COEF1_A3(0x016),    /*  0.0859 (-0.11 %) */
 658                         BF_PXP_CSC2_COEF2_B3(0x080) |   /*  0.5000 (+0.00 %) */
 659                         BF_PXP_CSC2_COEF2_B2(0x79e),    /* -0.3828 (+0.12 %) */
 660                         BF_PXP_CSC2_COEF3_C2(0x78f) |   /* -0.4414 (+0.36 %) */
 661                         BF_PXP_CSC2_COEF3_C1(0x080),    /*  0.5000 (+0.00 %) */
 662                         BF_PXP_CSC2_COEF4_D1(0) |
 663                         BF_PXP_CSC2_COEF4_C3(0x7f2),    /* -0.0547 (+0.03 %) */
 664                         BF_PXP_CSC2_COEF5_D3(128) |
 665                         BF_PXP_CSC2_COEF5_D2(128),
 666                 };
 667                 const u32 *csc2_coef;
 668                 u32 csc2_ctrl;
 669
 670                 ycbcr_enc = ctx->q_data[V4L2_M2M_DST].ycbcr_enc;
 671                 quantization = ctx->q_data[V4L2_M2M_DST].quant;
 672
 673                 if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
 674                         if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
 675                                 csc2_coef = csc2_coef_bt601_full;
 676                         else
 677                                 csc2_coef = csc2_coef_bt601_lim;
 678                 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
 679                         if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
 680                                 csc2_coef = csc2_coef_rec709_full;
 681                         else
 682                                 csc2_coef = csc2_coef_rec709_lim;
 683                 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
 684                         if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
 685                                 csc2_coef = csc2_coef_bt2020_full;
 686                         else
 687                                 csc2_coef = csc2_coef_bt2020_lim;
 688                 } else {
 689                         if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
 690                                 csc2_coef = csc2_coef_smpte240m_full;
 691                         else
 692                                 csc2_coef = csc2_coef_smpte240m_lim;
 693                 }
 694                 if (quantization == V4L2_QUANTIZATION_FULL_RANGE) {
 695                         csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV <<
 696                                     BP_PXP_CSC2_CTRL_CSC_MODE;
 697                 } else {
 698                         csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr <<
 699                                     BP_PXP_CSC2_CTRL_CSC_MODE;
 700                 }
 701
 702                 writel(csc2_ctrl, dev->mmio + HW_PXP_CSC2_CTRL);
 703                 writel(csc2_coef[0], dev->mmio + HW_PXP_CSC2_COEF0);
 704                 writel(csc2_coef[1], dev->mmio + HW_PXP_CSC2_COEF1);
 705                 writel(csc2_coef[2], dev->mmio + HW_PXP_CSC2_COEF2);
 706                 writel(csc2_coef[3], dev->mmio + HW_PXP_CSC2_COEF3);
 707                 writel(csc2_coef[4], dev->mmio + HW_PXP_CSC2_COEF4);
 708                 writel(csc2_coef[5], dev->mmio + HW_PXP_CSC2_COEF5);
 709         } else {
 710                 writel(BM_PXP_CSC2_CTRL_BYPASS, dev->mmio + HW_PXP_CSC2_CTRL);
 711         }
 712 }
 713
 714 static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
 715                      struct vb2_v4l2_buffer *out_vb)
 716 {
 717         struct pxp_dev *dev = ctx->dev;
 718         struct pxp_q_data *q_data;
 719         u32 src_width, src_height, src_stride, src_fourcc;
 720         u32 dst_width, dst_height, dst_stride, dst_fourcc;
 721         dma_addr_t p_in, p_out;
 722         u32 ctrl, out_ctrl, out_buf, out_buf2, out_pitch, out_lrc, out_ps_ulc;
 723         u32 out_ps_lrc;
 724         u32 ps_ctrl, ps_buf, ps_ubuf, ps_vbuf, ps_pitch, ps_scale, ps_offset;
 725         u32 as_ulc, as_lrc;
 726         u32 y_size;
 727         u32 decx, decy, xscale, yscale;
 728
 729         q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 730
 731         src_width = ctx->q_data[V4L2_M2M_SRC].width;
 732         dst_width = ctx->q_data[V4L2_M2M_DST].width;
 733         src_height = ctx->q_data[V4L2_M2M_SRC].height;
 734         dst_height = ctx->q_data[V4L2_M2M_DST].height;
 735         src_stride = ctx->q_data[V4L2_M2M_SRC].bytesperline;
 736         dst_stride = ctx->q_data[V4L2_M2M_DST].bytesperline;
 737         src_fourcc = ctx->q_data[V4L2_M2M_SRC].fmt->fourcc;
 738         dst_fourcc = ctx->q_data[V4L2_M2M_DST].fmt->fourcc;
 739
 740         p_in = vb2_dma_contig_plane_dma_addr(&in_vb->vb2_buf, 0);
 741         p_out = vb2_dma_contig_plane_dma_addr(&out_vb->vb2_buf, 0);
 742
 743         if (!p_in || !p_out) {
 744                 v4l2_err(&dev->v4l2_dev,
 745                          "Acquiring DMA addresses of buffers failed\n");
 746                 return -EFAULT;
 747         }
 748
 749         out_vb->sequence =
 750                 get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++;
 751         in_vb->sequence = q_data->sequence++;
 752         out_vb->vb2_buf.timestamp = in_vb->vb2_buf.timestamp;
 753
 754         if (in_vb->flags & V4L2_BUF_FLAG_TIMECODE)
 755                 out_vb->timecode = in_vb->timecode;
 756         out_vb->field = in_vb->field;
 757         out_vb->flags = in_vb->flags &
 758                 (V4L2_BUF_FLAG_TIMECODE |
 759                  V4L2_BUF_FLAG_KEYFRAME |
 760                  V4L2_BUF_FLAG_PFRAME |
 761                  V4L2_BUF_FLAG_BFRAME |
 762                  V4L2_BUF_FLAG_TSTAMP_SRC_MASK);
 763
 764         /* Rotation disabled, 8x8 block size */
 765         ctrl = BF_PXP_CTRL_VFLIP0(!!(ctx->mode & MEM2MEM_VFLIP)) |
 766                BF_PXP_CTRL_HFLIP0(!!(ctx->mode & MEM2MEM_HFLIP));
 767         /* Always write alpha value as V4L2_CID_ALPHA_COMPONENT */
 768         out_ctrl = BF_PXP_OUT_CTRL_ALPHA(ctx->alpha_component) |
 769                    BF_PXP_OUT_CTRL_ALPHA_OUTPUT(1) |
 770                    pxp_v4l2_pix_fmt_to_out_format(dst_fourcc);
 771         out_buf = p_out;
 772         switch (dst_fourcc) {
 773         case V4L2_PIX_FMT_NV12:
 774         case V4L2_PIX_FMT_NV21:
 775         case V4L2_PIX_FMT_NV16:
 776         case V4L2_PIX_FMT_NV61:
 777                 out_buf2 = out_buf + dst_stride * dst_height;
 778                 break;
 779         default:
 780                 out_buf2 = 0;
 781         }
 782
 783         out_pitch = BF_PXP_OUT_PITCH_PITCH(dst_stride);
 784         out_lrc = BF_PXP_OUT_LRC_X(dst_width - 1) |
 785                   BF_PXP_OUT_LRC_Y(dst_height - 1);
 786         /* PS covers whole output */
 787         out_ps_ulc = BF_PXP_OUT_PS_ULC_X(0) | BF_PXP_OUT_PS_ULC_Y(0);
 788         out_ps_lrc = BF_PXP_OUT_PS_LRC_X(dst_width - 1) |
 789                      BF_PXP_OUT_PS_LRC_Y(dst_height - 1);
 790         /* no AS */
 791         as_ulc = BF_PXP_OUT_AS_ULC_X(1) | BF_PXP_OUT_AS_ULC_Y(1);
 792         as_lrc = BF_PXP_OUT_AS_LRC_X(0) | BF_PXP_OUT_AS_LRC_Y(0);
 793
 794         decx = (src_width <= dst_width) ? 0 : ilog2(src_width / dst_width);
 795         decy = (src_height <= dst_height) ? 0 : ilog2(src_height / dst_height);
 796         ps_ctrl = BF_PXP_PS_CTRL_DECX(decx) | BF_PXP_PS_CTRL_DECY(decy) |
 797                   pxp_v4l2_pix_fmt_to_ps_format(src_fourcc);
 798         ps_buf = p_in;
 799         y_size = src_stride * src_height;
 800         switch (src_fourcc) {
 801         case V4L2_PIX_FMT_YUV420:
 802                 ps_ubuf = ps_buf + y_size;
 803                 ps_vbuf = ps_ubuf + y_size / 4;
 804                 break;
 805         case V4L2_PIX_FMT_YUV422P:
 806                 ps_ubuf = ps_buf + y_size;
 807                 ps_vbuf = ps_ubuf + y_size / 2;
 808                 break;
 809         case V4L2_PIX_FMT_NV12:
 810         case V4L2_PIX_FMT_NV21:
 811         case V4L2_PIX_FMT_NV16:
 812         case V4L2_PIX_FMT_NV61:
 813                 ps_ubuf = ps_buf + y_size;
 814                 ps_vbuf = 0;
 815                 break;
 816         case V4L2_PIX_FMT_GREY:
 817         case V4L2_PIX_FMT_Y4:
 818                 ps_ubuf = 0;
 819                 /* In grayscale mode, ps_vbuf contents are reused as CbCr */
 820                 ps_vbuf = 0x8080;
 821                 break;
 822         default:
 823                 ps_ubuf = 0;
 824                 ps_vbuf = 0;
 825                 break;
 826         }
 827         ps_pitch = BF_PXP_PS_PITCH_PITCH(src_stride);
 828         if (decx) {
 829                 xscale = (src_width >> decx) * 0x1000 / dst_width;
 830         } else {
 831                 switch (src_fourcc) {
 832                 case V4L2_PIX_FMT_UYVY:
 833                 case V4L2_PIX_FMT_YUYV:
 834                 case V4L2_PIX_FMT_VYUY:
 835                 case V4L2_PIX_FMT_YVYU:
 836                 case V4L2_PIX_FMT_NV16:
 837                 case V4L2_PIX_FMT_NV12:
 838                 case V4L2_PIX_FMT_NV21:
 839                 case V4L2_PIX_FMT_NV61:
 840                 case V4L2_PIX_FMT_YUV422P:
 841                 case V4L2_PIX_FMT_YUV420:
 842                         /*
 843                          * This avoids sampling past the right edge for
 844                          * horizontally chroma subsampled formats.
 845                          */
 846                         xscale = (src_width - 2) * 0x1000 / (dst_width - 1);
 847                         break;
 848                 default:
 849                         xscale = (src_width - 1) * 0x1000 / (dst_width - 1);
 850                         break;
 851                 }
 852         }
 853         if (decy)
 854                 yscale = (src_height >> decy) * 0x1000 / dst_height;
 855         else
 856                 yscale = (src_height - 1) * 0x1000 / (dst_height - 1);
 857         ps_scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
 858                    BF_PXP_PS_SCALE_XSCALE(xscale);
 859         ps_offset = BF_PXP_PS_OFFSET_YOFFSET(0) | BF_PXP_PS_OFFSET_XOFFSET(0);
 860
 861         writel(ctrl, dev->mmio + HW_PXP_CTRL);
 862         /* skip STAT */
 863         writel(out_ctrl, dev->mmio + HW_PXP_OUT_CTRL);
 864         writel(out_buf, dev->mmio + HW_PXP_OUT_BUF);
 865         writel(out_buf2, dev->mmio + HW_PXP_OUT_BUF2);
 866         writel(out_pitch, dev->mmio + HW_PXP_OUT_PITCH);
 867         writel(out_lrc, dev->mmio + HW_PXP_OUT_LRC);
 868         writel(out_ps_ulc, dev->mmio + HW_PXP_OUT_PS_ULC);
 869         writel(out_ps_lrc, dev->mmio + HW_PXP_OUT_PS_LRC);
 870         writel(as_ulc, dev->mmio + HW_PXP_OUT_AS_ULC);
 871         writel(as_lrc, dev->mmio + HW_PXP_OUT_AS_LRC);
 872         writel(ps_ctrl, dev->mmio + HW_PXP_PS_CTRL);
 873         writel(ps_buf, dev->mmio + HW_PXP_PS_BUF);
 874         writel(ps_ubuf, dev->mmio + HW_PXP_PS_UBUF);
 875         writel(ps_vbuf, dev->mmio + HW_PXP_PS_VBUF);
 876         writel(ps_pitch, dev->mmio + HW_PXP_PS_PITCH);
 877         writel(0x00ffffff, dev->mmio + HW_PXP_PS_BACKGROUND_0);
 878         writel(ps_scale, dev->mmio + HW_PXP_PS_SCALE);
 879         writel(ps_offset, dev->mmio + HW_PXP_PS_OFFSET);
 880         /* disable processed surface color keying */
 881         writel(0x00ffffff, dev->mmio + HW_PXP_PS_CLRKEYLOW_0);
 882         writel(0x00000000, dev->mmio + HW_PXP_PS_CLRKEYHIGH_0);
 883
 884         /* disable alpha surface color keying */
 885         writel(0x00ffffff, dev->mmio + HW_PXP_AS_CLRKEYLOW_0);
 886         writel(0x00000000, dev->mmio + HW_PXP_AS_CLRKEYHIGH_0);
 887
 888         /* setup CSC */
 889         pxp_setup_csc(ctx);
 890
 891         /* bypass LUT */
 892         writel(BM_PXP_LUT_CTRL_BYPASS, dev->mmio + HW_PXP_LUT_CTRL);
 893
 894         writel(BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)|
 895                BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)|
 896                BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)|
 897                BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)|
 898                BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)|
 899                BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)|
 900                BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)|
 901                BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)|
 902                BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)|
 903                BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)|
 904                BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)|
 905                BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)|
 906                BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)|
 907                BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)|
 908                BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)|
 909                BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0),
 910                dev->mmio + HW_PXP_DATA_PATH_CTRL0);
 911         writel(BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1) |
 912                BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1),
 913                dev->mmio + HW_PXP_DATA_PATH_CTRL1);
 914
 915         writel(0xffff, dev->mmio + HW_PXP_IRQ_MASK);
 916
 917         /* ungate, enable PS/AS/OUT and PXP operation */
 918         writel(BM_PXP_CTRL_IRQ_ENABLE, dev->mmio + HW_PXP_CTRL_SET);
 919         writel(BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_ENABLE_CSC2 |
 920                BM_PXP_CTRL_ENABLE_LUT | BM_PXP_CTRL_ENABLE_ROTATE0 |
 921                BM_PXP_CTRL_ENABLE_PS_AS_OUT, dev->mmio + HW_PXP_CTRL_SET);
 922
 923         return 0;
 924 }
 925
 926 static void pxp_job_finish(struct pxp_dev *dev)
 927 {
 928         struct pxp_ctx *curr_ctx;
 929         struct vb2_v4l2_buffer *src_vb, *dst_vb;
 930         unsigned long flags;
 931
 932         curr_ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
 933
 934         if (curr_ctx == NULL) {
 935                 pr_err("Instance released before the end of transaction\n");
 936                 return;
 937         }
 938
 939         src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
 940         dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
 941
 942         spin_lock_irqsave(&dev->irqlock, flags);
 943         v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
 944         v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
 945         spin_unlock_irqrestore(&dev->irqlock, flags);
 946
 947         dprintk(curr_ctx->dev, "Finishing transaction\n");
 948         v4l2_m2m_job_finish(dev->m2m_dev, curr_ctx->fh.m2m_ctx);
 949 }
 950
 951 /*
 952  * mem2mem callbacks
 953  */
 954 static void pxp_device_run(void *priv)
 955 {
 956         struct pxp_ctx *ctx = priv;
 957         struct vb2_v4l2_buffer *src_buf, *dst_buf;
 958
 959         src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
 960         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
 961
 962         pxp_start(ctx, src_buf, dst_buf);
 963 }
 964
 965 static int pxp_job_ready(void *priv)
 966 {
 967         struct pxp_ctx *ctx = priv;
 968
 969         if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < 1 ||
 970             v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < 1) {
 971                 dprintk(ctx->dev, "Not enough buffers available\n");
 972                 return 0;
 973         }
 974
 975         return 1;
 976 }
 977
 978 static void pxp_job_abort(void *priv)
 979 {
 980         struct pxp_ctx *ctx = priv;
 981
 982         /* Will cancel the transaction in the next interrupt handler */
 983         ctx->aborting = 1;
 984 }
 985
 986 /*
 987  * interrupt handler
 988  */
 989 static irqreturn_t pxp_irq_handler(int irq, void *dev_id)
 990 {
 991         struct pxp_dev *dev = dev_id;
 992         u32 stat;
 993
 994         stat = readl(dev->mmio + HW_PXP_STAT);
 995
 996         if (stat & BM_PXP_STAT_IRQ0) {
 997                 /* we expect x = 0, y = height, irq0 = 1 */
 998                 if (stat & ~(BM_PXP_STAT_BLOCKX | BM_PXP_STAT_BLOCKY |
 999                              BM_PXP_STAT_IRQ0))
1000                         dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
1001                 writel(BM_PXP_STAT_IRQ0, dev->mmio + HW_PXP_STAT_CLR);
1002
1003                 pxp_job_finish(dev);
1004         } else {
1005                 u32 irq = readl(dev->mmio + HW_PXP_IRQ);
1006
1007                 dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
1008                 dprintk(dev, "%s: irq = 0x%08x\n", __func__, irq);
1009
1010                 writel(irq, dev->mmio + HW_PXP_IRQ_CLR);
1011         }
1012
1013         return IRQ_HANDLED;
1014 }
1015
1016 /*
1017  * video ioctls
1018  */
1019 static int pxp_querycap(struct file *file, void *priv,
1020                            struct v4l2_capability *cap)
1021 {
1022         strlcpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
1023         strlcpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
1024         snprintf(cap->bus_info, sizeof(cap->bus_info),
1025                         "platform:%s", MEM2MEM_NAME);
1026         return 0;
1027 }
1028
1029 static int pxp_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1030 {
1031         int i, num;
1032         struct pxp_fmt *fmt;
1033
1034         num = 0;
1035
1036         for (i = 0; i < NUM_FORMATS; ++i) {
1037                 if (formats[i].types & type) {
1038                         /* index-th format of type type found ? */
1039                         if (num == f->index)
1040                                 break;
1041                         /*
1042                          * Correct type but haven't reached our index yet,
1043                          * just increment per-type index
1044                          */
1045                         ++num;
1046                 }
1047         }
1048
1049         if (i < NUM_FORMATS) {
1050                 /* Format found */
1051                 fmt = &formats[i];
1052                 f->pixelformat = fmt->fourcc;
1053                 return 0;
1054         }
1055
1056         /* Format not found */
1057         return -EINVAL;
1058 }
1059
1060 static int pxp_enum_fmt_vid_cap(struct file *file, void *priv,
1061                                 struct v4l2_fmtdesc *f)
1062 {
1063         return pxp_enum_fmt(f, MEM2MEM_CAPTURE);
1064 }
1065
1066 static int pxp_enum_fmt_vid_out(struct file *file, void *priv,
1067                                 struct v4l2_fmtdesc *f)
1068 {
1069         return pxp_enum_fmt(f, MEM2MEM_OUTPUT);
1070 }
1071
1072 static int pxp_g_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
1073 {
1074         struct vb2_queue *vq;
1075         struct pxp_q_data *q_data;
1076
1077         vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1078         if (!vq)
1079                 return -EINVAL;
1080
1081         q_data = get_q_data(ctx, f->type);
1082
1083         f->fmt.pix.width        = q_data->width;
1084         f->fmt.pix.height       = q_data->height;
1085         f->fmt.pix.field        = V4L2_FIELD_NONE;
1086         f->fmt.pix.pixelformat  = q_data->fmt->fourcc;
1087         f->fmt.pix.bytesperline = q_data->bytesperline;
1088         f->fmt.pix.sizeimage    = q_data->sizeimage;
1089         f->fmt.pix.colorspace   = ctx->colorspace;
1090         f->fmt.pix.xfer_func    = ctx->xfer_func;
1091         f->fmt.pix.ycbcr_enc    = q_data->ycbcr_enc;
1092         f->fmt.pix.quantization = q_data->quant;
1093
1094         return 0;
1095 }
1096
1097 static int pxp_g_fmt_vid_out(struct file *file, void *priv,
1098                                 struct v4l2_format *f)
1099 {
1100         return pxp_g_fmt(file2ctx(file), f);
1101 }
1102
1103 static int pxp_g_fmt_vid_cap(struct file *file, void *priv,
1104                                 struct v4l2_format *f)
1105 {
1106         return pxp_g_fmt(file2ctx(file), f);
1107 }
1108
1109 static inline u32 pxp_bytesperline(struct pxp_fmt *fmt, u32 width)
1110 {
1111         switch (fmt->fourcc) {
1112         case V4L2_PIX_FMT_YUV420:
1113         case V4L2_PIX_FMT_NV12:
1114         case V4L2_PIX_FMT_NV21:
1115         case V4L2_PIX_FMT_YUV422P:
1116         case V4L2_PIX_FMT_NV16:
1117         case V4L2_PIX_FMT_NV61:
1118                 return width;
1119         default:
1120                 return (width * fmt->depth) >> 3;
1121         }
1122 }
1123
1124 static inline u32 pxp_sizeimage(struct pxp_fmt *fmt, u32 width, u32 height)
1125 {
1126         return (fmt->depth * width * height) >> 3;
1127 }
1128
1129 static int pxp_try_fmt(struct v4l2_format *f, struct pxp_fmt *fmt)
1130 {
1131         v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, ALIGN_W,
1132                               &f->fmt.pix.height, MIN_H, MAX_H, ALIGN_H, 0);
1133
1134         f->fmt.pix.bytesperline = pxp_bytesperline(fmt, f->fmt.pix.width);
1135         f->fmt.pix.sizeimage = pxp_sizeimage(fmt, f->fmt.pix.width,
1136                                              f->fmt.pix.height);
1137         f->fmt.pix.field = V4L2_FIELD_NONE;
1138
1139         return 0;
1140 }
1141
1142 static void
1143 pxp_fixup_colorimetry_cap(struct pxp_ctx *ctx, u32 dst_fourcc,
1144                           enum v4l2_ycbcr_encoding *ycbcr_enc,
1145                           enum v4l2_quantization *quantization)
1146 {
1147         bool dst_is_yuv = pxp_v4l2_pix_fmt_is_yuv(dst_fourcc);
1148
1149         if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) ==
1150             dst_is_yuv) {
1151                 /*
1152                  * There is no support for conversion between different YCbCr
1153                  * encodings or between RGB limited and full range.
1154                  */
1155                 *ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
1156                 *quantization = ctx->q_data[V4L2_M2M_SRC].quant;
1157         } else {
1158                 *ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(ctx->colorspace);
1159                 *quantization = V4L2_MAP_QUANTIZATION_DEFAULT(!dst_is_yuv,
1160                                                               ctx->colorspace,
1161                                                               *ycbcr_enc);
1162         }
1163 }
1164
1165 static int pxp_try_fmt_vid_cap(struct file *file, void *priv,
1166                                struct v4l2_format *f)
1167 {
1168         struct pxp_fmt *fmt;
1169         struct pxp_ctx *ctx = file2ctx(file);
1170
1171         fmt = find_format(f);
1172         if (!fmt) {
1173                 f->fmt.pix.pixelformat = formats[0].fourcc;
1174                 fmt = find_format(f);
1175         }
1176         if (!(fmt->types & MEM2MEM_CAPTURE)) {
1177                 v4l2_err(&ctx->dev->v4l2_dev,
1178                          "Fourcc format (0x%08x) invalid.\n",
1179                          f->fmt.pix.pixelformat);
1180                 return -EINVAL;
1181         }
1182
1183         f->fmt.pix.colorspace = ctx->colorspace;
1184         f->fmt.pix.xfer_func = ctx->xfer_func;
1185
1186         pxp_fixup_colorimetry_cap(ctx, fmt->fourcc,
1187                                   &f->fmt.pix.ycbcr_enc,
1188                                   &f->fmt.pix.quantization);
1189
1190         return pxp_try_fmt(f, fmt);
1191 }
1192
1193 static int pxp_try_fmt_vid_out(struct file *file, void *priv,
1194                                struct v4l2_format *f)
1195 {
1196         struct pxp_fmt *fmt;
1197         struct pxp_ctx *ctx = file2ctx(file);
1198
1199         fmt = find_format(f);
1200         if (!fmt) {
1201                 f->fmt.pix.pixelformat = formats[0].fourcc;
1202                 fmt = find_format(f);
1203         }
1204         if (!(fmt->types & MEM2MEM_OUTPUT)) {
1205                 v4l2_err(&ctx->dev->v4l2_dev,
1206                          "Fourcc format (0x%08x) invalid.\n",
1207                          f->fmt.pix.pixelformat);
1208                 return -EINVAL;
1209         }
1210
1211         if (!f->fmt.pix.colorspace)
1212                 f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
1213
1214         return pxp_try_fmt(f, fmt);
1215 }
1216
1217 static int pxp_s_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
1218 {
1219         struct pxp_q_data *q_data;
1220         struct vb2_queue *vq;
1221
1222         vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1223         if (!vq)
1224                 return -EINVAL;
1225
1226         q_data = get_q_data(ctx, f->type);
1227         if (!q_data)
1228                 return -EINVAL;
1229
1230         if (vb2_is_busy(vq)) {
1231                 v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
1232                 return -EBUSY;
1233         }
1234
1235         q_data->fmt             = find_format(f);
1236         q_data->width           = f->fmt.pix.width;
1237         q_data->height          = f->fmt.pix.height;
1238         q_data->bytesperline    = f->fmt.pix.bytesperline;
1239         q_data->sizeimage       = f->fmt.pix.sizeimage;
1240
1241         dprintk(ctx->dev,
1242                 "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
1243                 f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
1244
1245         return 0;
1246 }
1247
1248 static int pxp_s_fmt_vid_cap(struct file *file, void *priv,
1249                              struct v4l2_format *f)
1250 {
1251         struct pxp_ctx *ctx = file2ctx(file);
1252         int ret;
1253
1254         ret = pxp_try_fmt_vid_cap(file, priv, f);
1255         if (ret)
1256                 return ret;
1257
1258         ret = pxp_s_fmt(file2ctx(file), f);
1259         if (ret)
1260                 return ret;
1261
1262         ctx->q_data[V4L2_M2M_DST].ycbcr_enc = f->fmt.pix.ycbcr_enc;
1263         ctx->q_data[V4L2_M2M_DST].quant = f->fmt.pix.quantization;
1264
1265         return 0;
1266 }
1267
1268 static int pxp_s_fmt_vid_out(struct file *file, void *priv,
1269                              struct v4l2_format *f)
1270 {
1271         struct pxp_ctx *ctx = file2ctx(file);
1272         int ret;
1273
1274         ret = pxp_try_fmt_vid_out(file, priv, f);
1275         if (ret)
1276                 return ret;
1277
1278         ret = pxp_s_fmt(file2ctx(file), f);
1279         if (ret)
1280                 return ret;
1281
1282         ctx->colorspace = f->fmt.pix.colorspace;
1283         ctx->xfer_func = f->fmt.pix.xfer_func;
1284         ctx->q_data[V4L2_M2M_SRC].ycbcr_enc = f->fmt.pix.ycbcr_enc;
1285         ctx->q_data[V4L2_M2M_SRC].quant = f->fmt.pix.quantization;
1286
1287         pxp_fixup_colorimetry_cap(ctx, ctx->q_data[V4L2_M2M_DST].fmt->fourcc,
1288                                   &ctx->q_data[V4L2_M2M_DST].ycbcr_enc,
1289                                   &ctx->q_data[V4L2_M2M_DST].quant);
1290
1291         return 0;
1292 }
1293
1294 static int pxp_s_ctrl(struct v4l2_ctrl *ctrl)
1295 {
1296         struct pxp_ctx *ctx =
1297                 container_of(ctrl->handler, struct pxp_ctx, hdl);
1298
1299         switch (ctrl->id) {
1300         case V4L2_CID_HFLIP:
1301                 if (ctrl->val)
1302                         ctx->mode |= MEM2MEM_HFLIP;
1303                 else
1304                         ctx->mode &= ~MEM2MEM_HFLIP;
1305                 break;
1306
1307         case V4L2_CID_VFLIP:
1308                 if (ctrl->val)
1309                         ctx->mode |= MEM2MEM_VFLIP;
1310                 else
1311                         ctx->mode &= ~MEM2MEM_VFLIP;
1312                 break;
1313
1314         case V4L2_CID_ALPHA_COMPONENT:
1315                 ctx->alpha_component = ctrl->val;
1316                 break;
1317
1318         default:
1319                 v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
1320                 return -EINVAL;
1321         }
1322
1323         return 0;
1324 }
1325
1326 static const struct v4l2_ctrl_ops pxp_ctrl_ops = {
1327         .s_ctrl = pxp_s_ctrl,
1328 };
1329
1330 static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
1331         .vidioc_querycap        = pxp_querycap,
1332
1333         .vidioc_enum_fmt_vid_cap = pxp_enum_fmt_vid_cap,
1334         .vidioc_g_fmt_vid_cap   = pxp_g_fmt_vid_cap,
1335         .vidioc_try_fmt_vid_cap = pxp_try_fmt_vid_cap,
1336         .vidioc_s_fmt_vid_cap   = pxp_s_fmt_vid_cap,
1337
1338         .vidioc_enum_fmt_vid_out = pxp_enum_fmt_vid_out,
1339         .vidioc_g_fmt_vid_out   = pxp_g_fmt_vid_out,
1340         .vidioc_try_fmt_vid_out = pxp_try_fmt_vid_out,
1341         .vidioc_s_fmt_vid_out   = pxp_s_fmt_vid_out,
1342
1343         .vidioc_reqbufs         = v4l2_m2m_ioctl_reqbufs,
1344         .vidioc_querybuf        = v4l2_m2m_ioctl_querybuf,
1345         .vidioc_qbuf            = v4l2_m2m_ioctl_qbuf,
1346         .vidioc_dqbuf           = v4l2_m2m_ioctl_dqbuf,
1347         .vidioc_prepare_buf     = v4l2_m2m_ioctl_prepare_buf,
1348         .vidioc_create_bufs     = v4l2_m2m_ioctl_create_bufs,
1349         .vidioc_expbuf          = v4l2_m2m_ioctl_expbuf,
1350
1351         .vidioc_streamon        = v4l2_m2m_ioctl_streamon,
1352         .vidioc_streamoff       = v4l2_m2m_ioctl_streamoff,
1353
1354         .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1355         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1356 };
1357
1358 /*
1359  * Queue operations
1360  */
1361 static int pxp_queue_setup(struct vb2_queue *vq,
1362                            unsigned int *nbuffers, unsigned int *nplanes,
1363                            unsigned int sizes[], struct device *alloc_devs[])
1364 {
1365         struct pxp_ctx *ctx = vb2_get_drv_priv(vq);
1366         struct pxp_q_data *q_data;
1367         unsigned int size, count = *nbuffers;
1368
1369         q_data = get_q_data(ctx, vq->type);
1370
1371         size = q_data->sizeimage;
1372
1373         *nbuffers = count;
1374
1375         if (*nplanes)
1376                 return sizes[0] < size ? -EINVAL : 0;
1377
1378         *nplanes = 1;
1379         sizes[0] = size;
1380
1381         dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
1382
1383         return 0;
1384 }
1385
1386 static int pxp_buf_prepare(struct vb2_buffer *vb)
1387 {
1388         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1389         struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1390         struct pxp_dev *dev = ctx->dev;
1391         struct pxp_q_data *q_data;
1392
1393         dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
1394
1395         q_data = get_q_data(ctx, vb->vb2_queue->type);
1396         if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
1397                 if (vbuf->field == V4L2_FIELD_ANY)
1398                         vbuf->field = V4L2_FIELD_NONE;
1399                 if (vbuf->field != V4L2_FIELD_NONE) {
1400                         dprintk(dev, "%s field isn't supported\n", __func__);
1401                         return -EINVAL;
1402                 }
1403         }
1404
1405         if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
1406                 dprintk(dev, "%s data will not fit into plane (%lu < %lu)\n",
1407                         __func__, vb2_plane_size(vb, 0),
1408                         (long)q_data->sizeimage);
1409                 return -EINVAL;
1410         }
1411
1412         vb2_set_plane_payload(vb, 0, q_data->sizeimage);
1413
1414         return 0;
1415 }
1416
1417 static void pxp_buf_queue(struct vb2_buffer *vb)
1418 {
1419         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1420         struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1421
1422         v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
1423 }
1424
1425 static int pxp_start_streaming(struct vb2_queue *q, unsigned int count)
1426 {
1427         struct pxp_ctx *ctx = vb2_get_drv_priv(q);
1428         struct pxp_q_data *q_data = get_q_data(ctx, q->type);
1429
1430         q_data->sequence = 0;
1431         return 0;
1432 }
1433
1434 static void pxp_stop_streaming(struct vb2_queue *q)
1435 {
1436         struct pxp_ctx *ctx = vb2_get_drv_priv(q);
1437         struct vb2_v4l2_buffer *vbuf;
1438         unsigned long flags;
1439
1440         for (;;) {
1441                 if (V4L2_TYPE_IS_OUTPUT(q->type))
1442                         vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1443                 else
1444                         vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1445                 if (vbuf == NULL)
1446                         return;
1447                 spin_lock_irqsave(&ctx->dev->irqlock, flags);
1448                 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
1449                 spin_unlock_irqrestore(&ctx->dev->irqlock, flags);
1450         }
1451 }
1452
1453 static const struct vb2_ops pxp_qops = {
1454         .queue_setup     = pxp_queue_setup,
1455         .buf_prepare     = pxp_buf_prepare,
1456         .buf_queue       = pxp_buf_queue,
1457         .start_streaming = pxp_start_streaming,
1458         .stop_streaming  = pxp_stop_streaming,
1459         .wait_prepare    = vb2_ops_wait_prepare,
1460         .wait_finish     = vb2_ops_wait_finish,
1461 };
1462
1463 static int queue_init(void *priv, struct vb2_queue *src_vq,
1464                       struct vb2_queue *dst_vq)
1465 {
1466         struct pxp_ctx *ctx = priv;
1467         int ret;
1468
1469         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1470         src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1471         src_vq->drv_priv = ctx;
1472         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1473         src_vq->ops = &pxp_qops;
1474         src_vq->mem_ops = &vb2_dma_contig_memops;
1475         src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1476         src_vq->lock = &ctx->dev->dev_mutex;
1477         src_vq->dev = ctx->dev->v4l2_dev.dev;
1478
1479         ret = vb2_queue_init(src_vq);
1480         if (ret)
1481                 return ret;
1482
1483         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1484         dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1485         dst_vq->drv_priv = ctx;
1486         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1487         dst_vq->ops = &pxp_qops;
1488         dst_vq->mem_ops = &vb2_dma_contig_memops;
1489         dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1490         dst_vq->lock = &ctx->dev->dev_mutex;
1491         dst_vq->dev = ctx->dev->v4l2_dev.dev;
1492
1493         return vb2_queue_init(dst_vq);
1494 }
1495
1496 /*
1497  * File operations
1498  */
1499 static int pxp_open(struct file *file)
1500 {
1501         struct pxp_dev *dev = video_drvdata(file);
1502         struct pxp_ctx *ctx = NULL;
1503         struct v4l2_ctrl_handler *hdl;
1504         int rc = 0;
1505
1506         if (mutex_lock_interruptible(&dev->dev_mutex))
1507                 return -ERESTARTSYS;
1508         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1509         if (!ctx) {
1510                 rc = -ENOMEM;
1511                 goto open_unlock;
1512         }
1513
1514         v4l2_fh_init(&ctx->fh, video_devdata(file));
1515         file->private_data = &ctx->fh;
1516         ctx->dev = dev;
1517         hdl = &ctx->hdl;
1518         v4l2_ctrl_handler_init(hdl, 4);
1519         v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1520         v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1521         v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
1522                           0, 255, 1, 255);
1523         if (hdl->error) {
1524                 rc = hdl->error;
1525                 v4l2_ctrl_handler_free(hdl);
1526                 kfree(ctx);
1527                 goto open_unlock;
1528         }
1529         ctx->fh.ctrl_handler = hdl;
1530         v4l2_ctrl_handler_setup(hdl);
1531
1532         ctx->q_data[V4L2_M2M_SRC].fmt = &formats[0];
1533         ctx->q_data[V4L2_M2M_SRC].width = 640;
1534         ctx->q_data[V4L2_M2M_SRC].height = 480;
1535         ctx->q_data[V4L2_M2M_SRC].bytesperline =
1536                 pxp_bytesperline(&formats[0], 640);
1537         ctx->q_data[V4L2_M2M_SRC].sizeimage =
1538                 pxp_sizeimage(&formats[0], 640, 480);
1539         ctx->q_data[V4L2_M2M_DST] = ctx->q_data[V4L2_M2M_SRC];
1540         ctx->colorspace = V4L2_COLORSPACE_REC709;
1541
1542         ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
1543
1544         if (IS_ERR(ctx->fh.m2m_ctx)) {
1545                 rc = PTR_ERR(ctx->fh.m2m_ctx);
1546
1547                 v4l2_ctrl_handler_free(hdl);
1548                 v4l2_fh_exit(&ctx->fh);
1549                 kfree(ctx);
1550                 goto open_unlock;
1551         }
1552
1553         v4l2_fh_add(&ctx->fh);
1554         atomic_inc(&dev->num_inst);
1555
1556         dprintk(dev, "Created instance: %p, m2m_ctx: %p\n",
1557                 ctx, ctx->fh.m2m_ctx);
1558
1559 open_unlock:
1560         mutex_unlock(&dev->dev_mutex);
1561         return rc;
1562 }
1563
1564 static int pxp_release(struct file *file)
1565 {
1566         struct pxp_dev *dev = video_drvdata(file);
1567         struct pxp_ctx *ctx = file2ctx(file);
1568
1569         dprintk(dev, "Releasing instance %p\n", ctx);
1570
1571         v4l2_fh_del(&ctx->fh);
1572         v4l2_fh_exit(&ctx->fh);
1573         v4l2_ctrl_handler_free(&ctx->hdl);
1574         mutex_lock(&dev->dev_mutex);
1575         v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
1576         mutex_unlock(&dev->dev_mutex);
1577         kfree(ctx);
1578
1579         atomic_dec(&dev->num_inst);
1580
1581         return 0;
1582 }
1583
1584 static const struct v4l2_file_operations pxp_fops = {
1585         .owner          = THIS_MODULE,
1586         .open           = pxp_open,
1587         .release        = pxp_release,
1588         .poll           = v4l2_m2m_fop_poll,
1589         .unlocked_ioctl = video_ioctl2,
1590         .mmap           = v4l2_m2m_fop_mmap,
1591 };
1592
1593 static const struct video_device pxp_videodev = {
1594         .name           = MEM2MEM_NAME,
1595         .vfl_dir        = VFL_DIR_M2M,
1596         .fops           = &pxp_fops,
1597         .device_caps    = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
1598         .ioctl_ops      = &pxp_ioctl_ops,
1599         .minor          = -1,
1600         .release        = video_device_release_empty,
1601 };
1602
1603 static const struct v4l2_m2m_ops m2m_ops = {
1604         .device_run     = pxp_device_run,
1605         .job_ready      = pxp_job_ready,
1606         .job_abort      = pxp_job_abort,
1607 };
1608
1609 static void pxp_soft_reset(struct pxp_dev *dev)
1610 {
1611         int ret;
1612         u32 val;
1613
1614         writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
1615         writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
1616
1617         writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
1618
1619         ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val,
1620                                  val & BM_PXP_CTRL_CLKGATE, 0, 100);
1621         if (ret < 0)
1622                 pr_err("PXP reset timeout\n");
1623
1624         writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
1625         writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
1626 }
1627
1628 static int pxp_probe(struct platform_device *pdev)
1629 {
1630         struct pxp_dev *dev;
1631         struct resource *res;
1632         struct video_device *vfd;
1633         int irq;
1634         int ret;
1635
1636         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1637         if (!dev)
1638                 return -ENOMEM;
1639
1640         dev->clk = devm_clk_get(&pdev->dev, "axi");
1641         if (IS_ERR(dev->clk)) {
1642                 ret = PTR_ERR(dev->clk);
1643                 dev_err(&pdev->dev, "Failed to get clk: %d\n", ret);
1644                 return ret;
1645         }
1646
1647         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1648         dev->mmio = devm_ioremap_resource(&pdev->dev, res);
1649         if (IS_ERR(dev->mmio)) {
1650                 ret = PTR_ERR(dev->mmio);
1651                 dev_err(&pdev->dev, "Failed to map register space: %d\n", ret);
1652                 return ret;
1653         }
1654
1655         irq = platform_get_irq(pdev, 0);
1656         if (irq < 0) {
1657                 dev_err(&pdev->dev, "Failed to get irq resource: %d\n", irq);
1658                 return irq;
1659         }
1660
1661         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, pxp_irq_handler,
1662                         IRQF_ONESHOT, dev_name(&pdev->dev), dev);
1663         if (ret < 0) {
1664                 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1665                 return ret;
1666         }
1667
1668         clk_prepare_enable(dev->clk);
1669         pxp_soft_reset(dev);
1670
1671         spin_lock_init(&dev->irqlock);
1672
1673         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1674         if (ret)
1675                 goto err_clk;
1676
1677         atomic_set(&dev->num_inst, 0);
1678         mutex_init(&dev->dev_mutex);
1679
1680         dev->vfd = pxp_videodev;
1681         vfd = &dev->vfd;
1682         vfd->lock = &dev->dev_mutex;
1683         vfd->v4l2_dev = &dev->v4l2_dev;
1684
1685         video_set_drvdata(vfd, dev);
1686         snprintf(vfd->name, sizeof(vfd->name), "%s", pxp_videodev.name);
1687         v4l2_info(&dev->v4l2_dev,
1688                         "Device registered as /dev/video%d\n", vfd->num);
1689
1690         platform_set_drvdata(pdev, dev);
1691
1692         dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
1693         if (IS_ERR(dev->m2m_dev)) {
1694                 v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
1695                 ret = PTR_ERR(dev->m2m_dev);
1696                 goto err_v4l2;
1697         }
1698
1699         ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1700         if (ret) {
1701                 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1702                 goto err_m2m;
1703         }
1704
1705         return 0;
1706
1707 err_m2m:
1708         v4l2_m2m_release(dev->m2m_dev);
1709 err_v4l2:
1710         v4l2_device_unregister(&dev->v4l2_dev);
1711 err_clk:
1712         clk_disable_unprepare(dev->clk);
1713
1714         return ret;
1715 }
1716
1717 static int pxp_remove(struct platform_device *pdev)
1718 {
1719         struct pxp_dev *dev = platform_get_drvdata(pdev);
1720
1721         writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_SET);
1722         writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
1723
1724         clk_disable_unprepare(dev->clk);
1725
1726         v4l2_info(&dev->v4l2_dev, "Removing " MEM2MEM_NAME);
1727         video_unregister_device(&dev->vfd);
1728         v4l2_m2m_release(dev->m2m_dev);
1729         v4l2_device_unregister(&dev->v4l2_dev);
1730
1731         return 0;
1732 }
1733
1734 static const struct of_device_id pxp_dt_ids[] = {
1735         { .compatible = "fsl,imx6ull-pxp", .data = NULL },
1736         { },
1737 };
1738 MODULE_DEVICE_TABLE(of, pxp_dt_ids);
1739
1740 static struct platform_driver pxp_driver = {
1741         .probe          = pxp_probe,
1742         .remove         = pxp_remove,
1743         .driver         = {
1744                 .name   = MEM2MEM_NAME,
1745                 .of_match_table = of_match_ptr(pxp_dt_ids),
1746         },
1747 };
1748
1749 module_platform_driver(pxp_driver);
1750
1751 MODULE_DESCRIPTION("i.MX PXP mem2mem scaler/CSC/rotator");
1752 MODULE_AUTHOR("Philipp Zabel <kernel@pengutronix.de>");
1753 MODULE_LICENSE("GPL");