1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Renesas R-Car MIPI CSI-2 Receiver
5 * Copyright (C) 2018 Renesas Electronics Corp.
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/sys_soc.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-mc.h>
23 #include <media/v4l2-subdev.h>
27 /* Register offsets and bits */
29 /* Control Timing Select */
31 #define TREF_TREF BIT(0)
35 #define SRST_SRST BIT(0)
37 /* PHY Operation Control */
38 #define PHYCNT_REG 0x08
39 #define PHYCNT_SHUTDOWNZ BIT(17)
40 #define PHYCNT_RSTZ BIT(16)
41 #define PHYCNT_ENABLECLK BIT(4)
42 #define PHYCNT_ENABLE_3 BIT(3)
43 #define PHYCNT_ENABLE_2 BIT(2)
44 #define PHYCNT_ENABLE_1 BIT(1)
45 #define PHYCNT_ENABLE_0 BIT(0)
47 /* Checksum Control */
48 #define CHKSUM_REG 0x0c
49 #define CHKSUM_ECC_EN BIT(1)
50 #define CHKSUM_CRC_EN BIT(0)
53 * Channel Data Type Select
54 * VCDT[0-15]: Channel 1 VCDT[16-31]: Channel 2
55 * VCDT2[0-15]: Channel 3 VCDT2[16-31]: Channel 4
58 #define VCDT2_REG 0x14
59 #define VCDT_VCDTN_EN BIT(15)
60 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
61 #define VCDT_SEL_DTN_ON BIT(6)
62 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
64 /* Frame Data Type Select */
67 /* Field Detection Control */
69 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
70 #define FLD_FLD_EN4 BIT(3)
71 #define FLD_FLD_EN3 BIT(2)
72 #define FLD_FLD_EN2 BIT(1)
73 #define FLD_FLD_EN BIT(0)
75 /* Automatic Standby Control */
76 #define ASTBY_REG 0x20
78 /* Long Data Type Setting 0 */
79 #define LNGDT0_REG 0x28
81 /* Long Data Type Setting 1 */
82 #define LNGDT1_REG 0x2c
84 /* Interrupt Enable */
85 #define INTEN_REG 0x30
87 /* Interrupt Source Mask */
88 #define INTCLOSE_REG 0x34
90 /* Interrupt Status Monitor */
91 #define INTSTATE_REG 0x38
92 #define INTSTATE_INT_ULPS_START BIT(7)
93 #define INTSTATE_INT_ULPS_END BIT(6)
95 /* Interrupt Error Status Monitor */
96 #define INTERRSTATE_REG 0x3c
98 /* Short Packet Data */
99 #define SHPDAT_REG 0x40
101 /* Short Packet Count */
102 #define SHPCNT_REG 0x44
104 /* LINK Operation Control */
105 #define LINKCNT_REG 0x48
106 #define LINKCNT_MONITOR_EN BIT(31)
107 #define LINKCNT_REG_MONI_PACT_EN BIT(25)
108 #define LINKCNT_ICLK_NONSTOP BIT(24)
111 #define LSWAP_REG 0x4c
112 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
113 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
114 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
115 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
117 /* PHY Test Interface Write Register */
118 #define PHTW_REG 0x50
119 #define PHTW_DWEN BIT(24)
120 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
121 #define PHTW_CWEN BIT(8)
122 #define PHTW_TESTDIN_CODE(n) ((n & 0xff))
129 struct rcsi2_mbps_reg {
134 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
135 { .mbps = 80, .reg = 0x86 },
136 { .mbps = 90, .reg = 0x86 },
137 { .mbps = 100, .reg = 0x87 },
138 { .mbps = 110, .reg = 0x87 },
139 { .mbps = 120, .reg = 0x88 },
140 { .mbps = 130, .reg = 0x88 },
141 { .mbps = 140, .reg = 0x89 },
142 { .mbps = 150, .reg = 0x89 },
143 { .mbps = 160, .reg = 0x8a },
144 { .mbps = 170, .reg = 0x8a },
145 { .mbps = 180, .reg = 0x8b },
146 { .mbps = 190, .reg = 0x8b },
147 { .mbps = 205, .reg = 0x8c },
148 { .mbps = 220, .reg = 0x8d },
149 { .mbps = 235, .reg = 0x8e },
150 { .mbps = 250, .reg = 0x8e },
154 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
155 { .mbps = 89, .reg = 0x00 },
156 { .mbps = 99, .reg = 0x20 },
157 { .mbps = 109, .reg = 0x40 },
158 { .mbps = 129, .reg = 0x02 },
159 { .mbps = 139, .reg = 0x22 },
160 { .mbps = 149, .reg = 0x42 },
161 { .mbps = 169, .reg = 0x04 },
162 { .mbps = 179, .reg = 0x24 },
163 { .mbps = 199, .reg = 0x44 },
164 { .mbps = 219, .reg = 0x06 },
165 { .mbps = 239, .reg = 0x26 },
166 { .mbps = 249, .reg = 0x46 },
167 { .mbps = 269, .reg = 0x08 },
168 { .mbps = 299, .reg = 0x28 },
169 { .mbps = 329, .reg = 0x0a },
170 { .mbps = 359, .reg = 0x2a },
171 { .mbps = 399, .reg = 0x4a },
172 { .mbps = 449, .reg = 0x0c },
173 { .mbps = 499, .reg = 0x2c },
174 { .mbps = 549, .reg = 0x0e },
175 { .mbps = 599, .reg = 0x2e },
176 { .mbps = 649, .reg = 0x10 },
177 { .mbps = 699, .reg = 0x30 },
178 { .mbps = 749, .reg = 0x12 },
179 { .mbps = 799, .reg = 0x32 },
180 { .mbps = 849, .reg = 0x52 },
181 { .mbps = 899, .reg = 0x72 },
182 { .mbps = 949, .reg = 0x14 },
183 { .mbps = 999, .reg = 0x34 },
184 { .mbps = 1049, .reg = 0x54 },
185 { .mbps = 1099, .reg = 0x74 },
186 { .mbps = 1125, .reg = 0x16 },
190 /* PHY Test Interface Clear */
191 #define PHTC_REG 0x58
192 #define PHTC_TESTCLR BIT(0)
194 /* PHY Frequency Control */
195 #define PHYPLL_REG 0x68
196 #define PHYPLL_HSFREQRANGE(n) ((n) << 16)
198 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
199 { .mbps = 80, .reg = 0x00 },
200 { .mbps = 90, .reg = 0x10 },
201 { .mbps = 100, .reg = 0x20 },
202 { .mbps = 110, .reg = 0x30 },
203 { .mbps = 120, .reg = 0x01 },
204 { .mbps = 130, .reg = 0x11 },
205 { .mbps = 140, .reg = 0x21 },
206 { .mbps = 150, .reg = 0x31 },
207 { .mbps = 160, .reg = 0x02 },
208 { .mbps = 170, .reg = 0x12 },
209 { .mbps = 180, .reg = 0x22 },
210 { .mbps = 190, .reg = 0x32 },
211 { .mbps = 205, .reg = 0x03 },
212 { .mbps = 220, .reg = 0x13 },
213 { .mbps = 235, .reg = 0x23 },
214 { .mbps = 250, .reg = 0x33 },
215 { .mbps = 275, .reg = 0x04 },
216 { .mbps = 300, .reg = 0x14 },
217 { .mbps = 325, .reg = 0x25 },
218 { .mbps = 350, .reg = 0x35 },
219 { .mbps = 400, .reg = 0x05 },
220 { .mbps = 450, .reg = 0x16 },
221 { .mbps = 500, .reg = 0x26 },
222 { .mbps = 550, .reg = 0x37 },
223 { .mbps = 600, .reg = 0x07 },
224 { .mbps = 650, .reg = 0x18 },
225 { .mbps = 700, .reg = 0x28 },
226 { .mbps = 750, .reg = 0x39 },
227 { .mbps = 800, .reg = 0x09 },
228 { .mbps = 850, .reg = 0x19 },
229 { .mbps = 900, .reg = 0x29 },
230 { .mbps = 950, .reg = 0x3a },
231 { .mbps = 1000, .reg = 0x0a },
232 { .mbps = 1050, .reg = 0x1a },
233 { .mbps = 1100, .reg = 0x2a },
234 { .mbps = 1150, .reg = 0x3b },
235 { .mbps = 1200, .reg = 0x0b },
236 { .mbps = 1250, .reg = 0x1b },
237 { .mbps = 1300, .reg = 0x2b },
238 { .mbps = 1350, .reg = 0x3c },
239 { .mbps = 1400, .reg = 0x0c },
240 { .mbps = 1450, .reg = 0x1c },
241 { .mbps = 1500, .reg = 0x2c },
245 static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
246 { .mbps = 80, .reg = 0x00 },
247 { .mbps = 90, .reg = 0x10 },
248 { .mbps = 100, .reg = 0x20 },
249 { .mbps = 110, .reg = 0x30 },
250 { .mbps = 120, .reg = 0x01 },
251 { .mbps = 130, .reg = 0x11 },
252 { .mbps = 140, .reg = 0x21 },
253 { .mbps = 150, .reg = 0x31 },
254 { .mbps = 160, .reg = 0x02 },
255 { .mbps = 170, .reg = 0x12 },
256 { .mbps = 180, .reg = 0x22 },
257 { .mbps = 190, .reg = 0x32 },
258 { .mbps = 205, .reg = 0x03 },
259 { .mbps = 220, .reg = 0x13 },
260 { .mbps = 235, .reg = 0x23 },
261 { .mbps = 250, .reg = 0x33 },
262 { .mbps = 275, .reg = 0x04 },
263 { .mbps = 300, .reg = 0x14 },
264 { .mbps = 325, .reg = 0x05 },
265 { .mbps = 350, .reg = 0x15 },
266 { .mbps = 400, .reg = 0x25 },
267 { .mbps = 450, .reg = 0x06 },
268 { .mbps = 500, .reg = 0x16 },
269 { .mbps = 550, .reg = 0x07 },
270 { .mbps = 600, .reg = 0x17 },
271 { .mbps = 650, .reg = 0x08 },
272 { .mbps = 700, .reg = 0x18 },
273 { .mbps = 750, .reg = 0x09 },
274 { .mbps = 800, .reg = 0x19 },
275 { .mbps = 850, .reg = 0x29 },
276 { .mbps = 900, .reg = 0x39 },
277 { .mbps = 950, .reg = 0x0a },
278 { .mbps = 1000, .reg = 0x1a },
279 { .mbps = 1050, .reg = 0x2a },
280 { .mbps = 1100, .reg = 0x3a },
281 { .mbps = 1150, .reg = 0x0b },
282 { .mbps = 1200, .reg = 0x1b },
283 { .mbps = 1250, .reg = 0x2b },
284 { .mbps = 1300, .reg = 0x3b },
285 { .mbps = 1350, .reg = 0x0c },
286 { .mbps = 1400, .reg = 0x1c },
287 { .mbps = 1450, .reg = 0x2c },
288 { .mbps = 1500, .reg = 0x3c },
292 /* PHY ESC Error Monitor */
293 #define PHEERM_REG 0x74
295 /* PHY Clock Lane Monitor */
296 #define PHCLM_REG 0x78
297 #define PHCLM_STOPSTATECKL BIT(0)
299 /* PHY Data Lane Monitor */
300 #define PHDLM_REG 0x7c
302 /* CSI0CLK Frequency Configuration Preset Register */
303 #define CSI0CLKFCPR_REG 0x260
304 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
306 struct rcar_csi2_format {
308 unsigned int datatype;
312 static const struct rcar_csi2_format rcar_csi2_formats[] = {
313 { .code = MEDIA_BUS_FMT_RGB888_1X24, .datatype = 0x24, .bpp = 24 },
314 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 },
315 { .code = MEDIA_BUS_FMT_YUYV8_1X16, .datatype = 0x1e, .bpp = 16 },
316 { .code = MEDIA_BUS_FMT_UYVY8_2X8, .datatype = 0x1e, .bpp = 16 },
317 { .code = MEDIA_BUS_FMT_YUYV10_2X10, .datatype = 0x1e, .bpp = 20 },
320 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
324 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
325 if (rcar_csi2_formats[i].code == code)
326 return &rcar_csi2_formats[i];
331 enum rcar_csi2_pads {
333 RCAR_CSI2_SOURCE_VC0,
334 RCAR_CSI2_SOURCE_VC1,
335 RCAR_CSI2_SOURCE_VC2,
336 RCAR_CSI2_SOURCE_VC3,
340 struct rcar_csi2_info {
341 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
342 int (*confirm_start)(struct rcar_csi2 *priv);
343 const struct rcsi2_mbps_reg *hsfreqrange;
344 unsigned int csi0clkfreqrange;
345 unsigned int num_channels;
352 const struct rcar_csi2_info *info;
354 struct v4l2_subdev subdev;
355 struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
357 struct v4l2_async_notifier notifier;
358 struct v4l2_async_subdev asd;
359 struct v4l2_subdev *remote;
361 struct v4l2_mbus_framefmt mf;
366 unsigned short lanes;
367 unsigned char lane_swap[4];
370 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
372 return container_of(sd, struct rcar_csi2, subdev);
375 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
377 return container_of(n, struct rcar_csi2, notifier);
380 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
382 return ioread32(priv->base + reg);
385 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
387 iowrite32(data, priv->base + reg);
390 static void rcsi2_reset(struct rcar_csi2 *priv)
392 rcsi2_write(priv, SRST_REG, SRST_SRST);
393 usleep_range(100, 150);
394 rcsi2_write(priv, SRST_REG, 0);
397 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv)
399 unsigned int timeout;
401 /* Wait for the clock and data lanes to enter LP-11 state. */
402 for (timeout = 0; timeout <= 20; timeout++) {
403 const u32 lane_mask = (1 << priv->lanes) - 1;
405 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&
406 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
409 usleep_range(1000, 2000);
412 dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
417 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
419 const struct rcsi2_mbps_reg *hsfreq;
421 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++)
422 if (hsfreq->mbps >= mbps)
426 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
430 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
435 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp)
437 struct v4l2_subdev *source;
438 struct v4l2_ctrl *ctrl;
444 source = priv->remote;
446 /* Read the pixel rate control from remote. */
447 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
449 dev_err(priv->dev, "no pixel rate control in subdev %s\n",
455 * Calculate the phypll in mbps.
456 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
457 * bps = link_freq * 2
459 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
460 do_div(mbps, priv->lanes * 1000000);
465 static int rcsi2_start(struct rcar_csi2 *priv)
467 const struct rcar_csi2_format *format;
468 u32 phycnt, vcdt = 0, vcdt2 = 0;
472 dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
473 priv->mf.width, priv->mf.height,
474 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
476 /* Code is validated in set_fmt. */
477 format = rcsi2_code_to_fmt(priv->mf.code);
480 * Enable all supported CSI-2 channels with virtual channel and
481 * data type matching.
483 * NOTE: It's not possible to get individual datatype for each
484 * source virtual channel. Once this is possible in V4L2
485 * it should be used here.
487 for (i = 0; i < priv->info->num_channels; i++) {
490 vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON |
491 VCDT_SEL_DT(format->datatype);
493 /* Store in correct reg and offset. */
495 vcdt |= vcdt_part << ((i % 2) * 16);
497 vcdt2 |= vcdt_part << ((i % 2) * 16);
500 phycnt = PHYCNT_ENABLECLK;
501 phycnt |= (1 << priv->lanes) - 1;
503 mbps = rcsi2_calc_mbps(priv, format->bpp);
508 rcsi2_write(priv, TREF_REG, TREF_TREF);
510 rcsi2_write(priv, PHTC_REG, 0);
513 rcsi2_write(priv, FLD_REG, FLD_FLD_NUM(2) | FLD_FLD_EN4 |
514 FLD_FLD_EN3 | FLD_FLD_EN2 | FLD_FLD_EN);
515 rcsi2_write(priv, VCDT_REG, vcdt);
517 rcsi2_write(priv, VCDT2_REG, vcdt2);
518 /* Lanes are zero indexed. */
519 rcsi2_write(priv, LSWAP_REG,
520 LSWAP_L0SEL(priv->lane_swap[0] - 1) |
521 LSWAP_L1SEL(priv->lane_swap[1] - 1) |
522 LSWAP_L2SEL(priv->lane_swap[2] - 1) |
523 LSWAP_L3SEL(priv->lane_swap[3] - 1));
526 if (priv->info->init_phtw) {
527 ret = priv->info->init_phtw(priv, mbps);
532 if (priv->info->hsfreqrange) {
533 ret = rcsi2_set_phypll(priv, mbps);
538 if (priv->info->csi0clkfreqrange)
539 rcsi2_write(priv, CSI0CLKFCPR_REG,
540 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
542 rcsi2_write(priv, PHYCNT_REG, phycnt);
543 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
544 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
545 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
546 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
548 ret = rcsi2_wait_phy_start(priv);
553 if (priv->info->confirm_start) {
554 ret = priv->info->confirm_start(priv);
559 /* Clear Ultra Low Power interrupt. */
560 if (priv->info->clear_ulps)
561 rcsi2_write(priv, INTSTATE_REG,
562 INTSTATE_INT_ULPS_START |
563 INTSTATE_INT_ULPS_END);
567 static void rcsi2_stop(struct rcar_csi2 *priv)
569 rcsi2_write(priv, PHYCNT_REG, 0);
573 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
576 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
578 struct rcar_csi2 *priv = sd_to_csi2(sd);
579 struct v4l2_subdev *nextsd;
582 mutex_lock(&priv->lock);
589 nextsd = priv->remote;
591 if (enable && priv->stream_count == 0) {
592 pm_runtime_get_sync(priv->dev);
594 ret = rcsi2_start(priv);
596 pm_runtime_put(priv->dev);
600 ret = v4l2_subdev_call(nextsd, video, s_stream, 1);
603 pm_runtime_put(priv->dev);
606 } else if (!enable && priv->stream_count == 1) {
608 v4l2_subdev_call(nextsd, video, s_stream, 0);
609 pm_runtime_put(priv->dev);
612 priv->stream_count += enable ? 1 : -1;
614 mutex_unlock(&priv->lock);
619 static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
620 struct v4l2_subdev_pad_config *cfg,
621 struct v4l2_subdev_format *format)
623 struct rcar_csi2 *priv = sd_to_csi2(sd);
624 struct v4l2_mbus_framefmt *framefmt;
626 if (!rcsi2_code_to_fmt(format->format.code))
627 format->format.code = rcar_csi2_formats[0].code;
629 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
630 priv->mf = format->format;
632 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
633 *framefmt = format->format;
639 static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
640 struct v4l2_subdev_pad_config *cfg,
641 struct v4l2_subdev_format *format)
643 struct rcar_csi2 *priv = sd_to_csi2(sd);
645 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
646 format->format = priv->mf;
648 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
653 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
654 .s_stream = rcsi2_s_stream,
657 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
658 .set_fmt = rcsi2_set_pad_format,
659 .get_fmt = rcsi2_get_pad_format,
662 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
663 .video = &rcar_csi2_video_ops,
664 .pad = &rcar_csi2_pad_ops,
667 /* -----------------------------------------------------------------------------
668 * Async handling and registration of subdevices and links.
671 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
672 struct v4l2_subdev *subdev,
673 struct v4l2_async_subdev *asd)
675 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
678 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
679 MEDIA_PAD_FL_SOURCE);
681 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
685 priv->remote = subdev;
687 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
689 return media_create_pad_link(&subdev->entity, pad,
690 &priv->subdev.entity, 0,
691 MEDIA_LNK_FL_ENABLED |
692 MEDIA_LNK_FL_IMMUTABLE);
695 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
696 struct v4l2_subdev *subdev,
697 struct v4l2_async_subdev *asd)
699 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
703 dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
706 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
707 .bound = rcsi2_notify_bound,
708 .unbind = rcsi2_notify_unbind,
711 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
712 struct v4l2_fwnode_endpoint *vep)
716 /* Only port 0 endpoint 0 is valid. */
717 if (vep->base.port || vep->base.id)
720 if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) {
721 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
725 priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
726 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
727 dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
732 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
733 priv->lane_swap[i] = i < priv->lanes ?
734 vep->bus.mipi_csi2.data_lanes[i] : i;
736 /* Check for valid lane number. */
737 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
738 dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
746 static int rcsi2_parse_dt(struct rcar_csi2 *priv)
748 struct device_node *ep;
749 struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 };
752 ep = of_graph_get_endpoint_by_regs(priv->dev->of_node, 0, 0);
754 dev_err(priv->dev, "Not connected to subdevice\n");
758 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &v4l2_ep);
760 dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
765 ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
771 priv->asd.match.fwnode =
772 fwnode_graph_get_remote_endpoint(of_fwnode_handle(ep));
773 priv->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
777 v4l2_async_notifier_init(&priv->notifier);
779 ret = v4l2_async_notifier_add_subdev(&priv->notifier, &priv->asd);
781 fwnode_handle_put(priv->asd.match.fwnode);
785 priv->notifier.ops = &rcar_csi2_notify_ops;
787 dev_dbg(priv->dev, "Found '%pOF'\n",
788 to_of_node(priv->asd.match.fwnode));
790 ret = v4l2_async_subdev_notifier_register(&priv->subdev,
793 v4l2_async_notifier_cleanup(&priv->notifier);
798 /* -----------------------------------------------------------------------------
799 * PHTW initialization sequences.
801 * NOTE: Magic values are from the datasheet and lack documentation.
804 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
806 unsigned int timeout;
808 rcsi2_write(priv, PHTW_REG,
809 PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
810 PHTW_CWEN | PHTW_TESTDIN_CODE(code));
812 /* Wait for DWEN and CWEN to be cleared by hardware. */
813 for (timeout = 0; timeout <= 20; timeout++) {
814 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
817 usleep_range(1000, 2000);
820 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
825 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
826 const struct phtw_value *values)
828 const struct phtw_value *value;
831 for (value = values; value->data || value->code; value++) {
832 ret = rcsi2_phtw_write(priv, value->data, value->code);
840 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
841 const struct rcsi2_mbps_reg *values, u16 code)
843 const struct rcsi2_mbps_reg *value;
845 for (value = values; value->mbps; value++)
846 if (value->mbps >= mbps)
850 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
854 return rcsi2_phtw_write(priv, value->reg, code);
857 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
859 static const struct phtw_value step1[] = {
860 { .data = 0xcc, .code = 0xe2 },
861 { .data = 0x01, .code = 0xe3 },
862 { .data = 0x11, .code = 0xe4 },
863 { .data = 0x01, .code = 0xe5 },
864 { .data = 0x10, .code = 0x04 },
868 static const struct phtw_value step2[] = {
869 { .data = 0x38, .code = 0x08 },
870 { .data = 0x01, .code = 0x00 },
871 { .data = 0x4b, .code = 0xac },
872 { .data = 0x03, .code = 0x00 },
873 { .data = 0x80, .code = 0x07 },
879 ret = rcsi2_phtw_write_array(priv, step1);
884 ret = rcsi2_phtw_write(priv, 0x39, 0x05);
888 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
894 return rcsi2_phtw_write_array(priv, step2);
897 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
899 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
902 static int rcsi2_confirm_start_v3m_e3(struct rcar_csi2 *priv)
904 static const struct phtw_value step1[] = {
905 { .data = 0xed, .code = 0x34 },
906 { .data = 0xed, .code = 0x44 },
907 { .data = 0xed, .code = 0x54 },
908 { .data = 0xed, .code = 0x84 },
909 { .data = 0xed, .code = 0x94 },
913 return rcsi2_phtw_write_array(priv, step1);
916 /* -----------------------------------------------------------------------------
917 * Platform Device Driver.
920 static const struct media_entity_operations rcar_csi2_entity_ops = {
921 .link_validate = v4l2_subdev_link_validate,
924 static int rcsi2_probe_resources(struct rcar_csi2 *priv,
925 struct platform_device *pdev)
927 struct resource *res;
930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
931 priv->base = devm_ioremap_resource(&pdev->dev, res);
932 if (IS_ERR(priv->base))
933 return PTR_ERR(priv->base);
935 irq = platform_get_irq(pdev, 0);
942 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
943 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
944 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
945 .csi0clkfreqrange = 0x20,
950 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
951 .hsfreqrange = hsfreqrange_m3w_h3es1,
955 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
956 .hsfreqrange = hsfreqrange_m3w_h3es1,
960 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
961 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
962 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
963 .csi0clkfreqrange = 0x20,
968 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
969 .init_phtw = rcsi2_init_phtw_v3m_e3,
970 .confirm_start = rcsi2_confirm_start_v3m_e3,
974 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {
975 .init_phtw = rcsi2_init_phtw_v3m_e3,
976 .confirm_start = rcsi2_confirm_start_v3m_e3,
980 static const struct of_device_id rcar_csi2_of_table[] = {
982 .compatible = "renesas,r8a7795-csi2",
983 .data = &rcar_csi2_info_r8a7795,
986 .compatible = "renesas,r8a7796-csi2",
987 .data = &rcar_csi2_info_r8a7796,
990 .compatible = "renesas,r8a77965-csi2",
991 .data = &rcar_csi2_info_r8a77965,
994 .compatible = "renesas,r8a77970-csi2",
995 .data = &rcar_csi2_info_r8a77970,
998 .compatible = "renesas,r8a77990-csi2",
999 .data = &rcar_csi2_info_r8a77990,
1003 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
1005 static const struct soc_device_attribute r8a7795es1[] = {
1007 .soc_id = "r8a7795", .revision = "ES1.*",
1008 .data = &rcar_csi2_info_r8a7795es1,
1013 static int rcsi2_probe(struct platform_device *pdev)
1015 const struct soc_device_attribute *attr;
1016 struct rcar_csi2 *priv;
1020 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1024 priv->info = of_device_get_match_data(&pdev->dev);
1027 * r8a7795 ES1.x behaves differently than the ES2.0+ but doesn't
1028 * have it's own compatible string.
1030 attr = soc_device_match(r8a7795es1);
1032 priv->info = attr->data;
1034 priv->dev = &pdev->dev;
1036 mutex_init(&priv->lock);
1037 priv->stream_count = 0;
1039 ret = rcsi2_probe_resources(priv, pdev);
1041 dev_err(priv->dev, "Failed to get resources\n");
1045 platform_set_drvdata(pdev, priv);
1047 ret = rcsi2_parse_dt(priv);
1051 priv->subdev.owner = THIS_MODULE;
1052 priv->subdev.dev = &pdev->dev;
1053 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
1054 v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
1055 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
1056 KBUILD_MODNAME, dev_name(&pdev->dev));
1057 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1059 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1060 priv->subdev.entity.ops = &rcar_csi2_entity_ops;
1062 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
1063 for (i = RCAR_CSI2_SOURCE_VC0; i < NR_OF_RCAR_CSI2_PAD; i++)
1064 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
1066 ret = media_entity_pads_init(&priv->subdev.entity, NR_OF_RCAR_CSI2_PAD,
1071 pm_runtime_enable(&pdev->dev);
1073 ret = v4l2_async_register_subdev(&priv->subdev);
1077 dev_info(priv->dev, "%d lanes found\n", priv->lanes);
1082 v4l2_async_notifier_unregister(&priv->notifier);
1083 v4l2_async_notifier_cleanup(&priv->notifier);
1088 static int rcsi2_remove(struct platform_device *pdev)
1090 struct rcar_csi2 *priv = platform_get_drvdata(pdev);
1092 v4l2_async_notifier_unregister(&priv->notifier);
1093 v4l2_async_notifier_cleanup(&priv->notifier);
1094 v4l2_async_unregister_subdev(&priv->subdev);
1096 pm_runtime_disable(&pdev->dev);
1101 static struct platform_driver rcar_csi2_pdrv = {
1102 .remove = rcsi2_remove,
1103 .probe = rcsi2_probe,
1105 .name = "rcar-csi2",
1106 .of_match_table = rcar_csi2_of_table,
1110 module_platform_driver(rcar_csi2_pdrv);
1112 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
1113 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
1114 MODULE_LICENSE("GPL");