drivers/media/platform/rcar-vin/rcar-dma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Renesas R-Car VIN
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  * Copyright (C) 2011-2013 Renesas Solutions Corp.
   7  * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com>
   8  * Copyright (C) 2008 Magnus Damm
   9  *
  10  * Based on the soc-camera rcar_vin driver
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/pm_runtime.h>
  16
  17 #include <media/videobuf2-dma-contig.h>
  18
  19 #include "rcar-vin.h"
  20
  21 /* -----------------------------------------------------------------------------
  22  * HW Functions
  23  */
  24
  25 /* Register offsets for R-Car VIN */
  26 #define VNMC_REG        0x00    /* Video n Main Control Register */
  27 #define VNMS_REG        0x04    /* Video n Module Status Register */
  28 #define VNFC_REG        0x08    /* Video n Frame Capture Register */
  29 #define VNSLPRC_REG     0x0C    /* Video n Start Line Pre-Clip Register */
  30 #define VNELPRC_REG     0x10    /* Video n End Line Pre-Clip Register */
  31 #define VNSPPRC_REG     0x14    /* Video n Start Pixel Pre-Clip Register */
  32 #define VNEPPRC_REG     0x18    /* Video n End Pixel Pre-Clip Register */
  33 #define VNIS_REG        0x2C    /* Video n Image Stride Register */
  34 #define VNMB_REG(m)     (0x30 + ((m) << 2)) /* Video n Memory Base m Register */
  35 #define VNIE_REG        0x40    /* Video n Interrupt Enable Register */
  36 #define VNINTS_REG      0x44    /* Video n Interrupt Status Register */
  37 #define VNSI_REG        0x48    /* Video n Scanline Interrupt Register */
  38 #define VNMTC_REG       0x4C    /* Video n Memory Transfer Control Register */
  39 #define VNDMR_REG       0x58    /* Video n Data Mode Register */
  40 #define VNDMR2_REG      0x5C    /* Video n Data Mode Register 2 */
  41 #define VNUVAOF_REG     0x60    /* Video n UV Address Offset Register */
  42
  43 /* Register offsets specific for Gen2 */
  44 #define VNSLPOC_REG     0x1C    /* Video n Start Line Post-Clip Register */
  45 #define VNELPOC_REG     0x20    /* Video n End Line Post-Clip Register */
  46 #define VNSPPOC_REG     0x24    /* Video n Start Pixel Post-Clip Register */
  47 #define VNEPPOC_REG     0x28    /* Video n End Pixel Post-Clip Register */
  48 #define VNYS_REG        0x50    /* Video n Y Scale Register */
  49 #define VNXS_REG        0x54    /* Video n X Scale Register */
  50 #define VNC1A_REG       0x80    /* Video n Coefficient Set C1A Register */
  51 #define VNC1B_REG       0x84    /* Video n Coefficient Set C1B Register */
  52 #define VNC1C_REG       0x88    /* Video n Coefficient Set C1C Register */
  53 #define VNC2A_REG       0x90    /* Video n Coefficient Set C2A Register */
  54 #define VNC2B_REG       0x94    /* Video n Coefficient Set C2B Register */
  55 #define VNC2C_REG       0x98    /* Video n Coefficient Set C2C Register */
  56 #define VNC3A_REG       0xA0    /* Video n Coefficient Set C3A Register */
  57 #define VNC3B_REG       0xA4    /* Video n Coefficient Set C3B Register */
  58 #define VNC3C_REG       0xA8    /* Video n Coefficient Set C3C Register */
  59 #define VNC4A_REG       0xB0    /* Video n Coefficient Set C4A Register */
  60 #define VNC4B_REG       0xB4    /* Video n Coefficient Set C4B Register */
  61 #define VNC4C_REG       0xB8    /* Video n Coefficient Set C4C Register */
  62 #define VNC5A_REG       0xC0    /* Video n Coefficient Set C5A Register */
  63 #define VNC5B_REG       0xC4    /* Video n Coefficient Set C5B Register */
  64 #define VNC5C_REG       0xC8    /* Video n Coefficient Set C5C Register */
  65 #define VNC6A_REG       0xD0    /* Video n Coefficient Set C6A Register */
  66 #define VNC6B_REG       0xD4    /* Video n Coefficient Set C6B Register */
  67 #define VNC6C_REG       0xD8    /* Video n Coefficient Set C6C Register */
  68 #define VNC7A_REG       0xE0    /* Video n Coefficient Set C7A Register */
  69 #define VNC7B_REG       0xE4    /* Video n Coefficient Set C7B Register */
  70 #define VNC7C_REG       0xE8    /* Video n Coefficient Set C7C Register */
  71 #define VNC8A_REG       0xF0    /* Video n Coefficient Set C8A Register */
  72 #define VNC8B_REG       0xF4    /* Video n Coefficient Set C8B Register */
  73 #define VNC8C_REG       0xF8    /* Video n Coefficient Set C8C Register */
  74
  75 /* Register offsets specific for Gen3 */
  76 #define VNCSI_IFMD_REG          0x20 /* Video n CSI2 Interface Mode Register */
  77
  78 /* Register bit fields for R-Car VIN */
  79 /* Video n Main Control Register bits */
  80 #define VNMC_DPINE              (1 << 27) /* Gen3 specific */
  81 #define VNMC_SCLE               (1 << 26) /* Gen3 specific */
  82 #define VNMC_FOC                (1 << 21)
  83 #define VNMC_YCAL               (1 << 19)
  84 #define VNMC_INF_YUV8_BT656     (0 << 16)
  85 #define VNMC_INF_YUV8_BT601     (1 << 16)
  86 #define VNMC_INF_YUV10_BT656    (2 << 16)
  87 #define VNMC_INF_YUV10_BT601    (3 << 16)
  88 #define VNMC_INF_YUV16          (5 << 16)
  89 #define VNMC_INF_RGB888         (6 << 16)
  90 #define VNMC_VUP                (1 << 10)
  91 #define VNMC_IM_ODD             (0 << 3)
  92 #define VNMC_IM_ODD_EVEN        (1 << 3)
  93 #define VNMC_IM_EVEN            (2 << 3)
  94 #define VNMC_IM_FULL            (3 << 3)
  95 #define VNMC_BPS                (1 << 1)
  96 #define VNMC_ME                 (1 << 0)
  97
  98 /* Video n Module Status Register bits */
  99 #define VNMS_FBS_MASK           (3 << 3)
 100 #define VNMS_FBS_SHIFT          3
 101 #define VNMS_FS                 (1 << 2)
 102 #define VNMS_AV                 (1 << 1)
 103 #define VNMS_CA                 (1 << 0)
 104
 105 /* Video n Frame Capture Register bits */
 106 #define VNFC_C_FRAME            (1 << 1)
 107 #define VNFC_S_FRAME            (1 << 0)
 108
 109 /* Video n Interrupt Enable Register bits */
 110 #define VNIE_FIE                (1 << 4)
 111 #define VNIE_EFE                (1 << 1)
 112
 113 /* Video n Data Mode Register bits */
 114 #define VNDMR_A8BIT(n)          (((n) & 0xff) << 24)
 115 #define VNDMR_A8BIT_MASK        (0xff << 24)
 116 #define VNDMR_EXRGB             (1 << 8)
 117 #define VNDMR_BPSM              (1 << 4)
 118 #define VNDMR_ABIT              (1 << 2)
 119 #define VNDMR_DTMD_YCSEP        (1 << 1)
 120 #define VNDMR_DTMD_ARGB         (1 << 0)
 121 #define VNDMR_DTMD_YCSEP_420    (3 << 0)
 122
 123 /* Video n Data Mode Register 2 bits */
 124 #define VNDMR2_VPS              (1 << 30)
 125 #define VNDMR2_HPS              (1 << 29)
 126 #define VNDMR2_CES              (1 << 28)
 127 #define VNDMR2_FTEV             (1 << 17)
 128 #define VNDMR2_VLV(n)           ((n & 0xf) << 12)
 129
 130 /* Video n CSI2 Interface Mode Register (Gen3) */
 131 #define VNCSI_IFMD_DES1         (1 << 26)
 132 #define VNCSI_IFMD_DES0         (1 << 25)
 133 #define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
 134 #define VNCSI_IFMD_CSI_CHSEL_MASK 0xf
 135
 136 struct rvin_buffer {
 137         struct vb2_v4l2_buffer vb;
 138         struct list_head list;
 139 };
 140
 141 #define to_buf_list(vb2_buffer) (&container_of(vb2_buffer, \
 142                                                struct rvin_buffer, \
 143                                                vb)->list)
 144
 145 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset)
 146 {
 147         iowrite32(value, vin->base + offset);
 148 }
 149
 150 static u32 rvin_read(struct rvin_dev *vin, u32 offset)
 151 {
 152         return ioread32(vin->base + offset);
 153 }
 154
 155 /* -----------------------------------------------------------------------------
 156  * Crop and Scaling Gen2
 157  */
 158
 159 struct vin_coeff {
 160         unsigned short xs_value;
 161         u32 coeff_set[24];
 162 };
 163
 164 static const struct vin_coeff vin_coeff_set[] = {
 165         { 0x0000, {
 166                           0x00000000, 0x00000000, 0x00000000,
 167                           0x00000000, 0x00000000, 0x00000000,
 168                           0x00000000, 0x00000000, 0x00000000,
 169                           0x00000000, 0x00000000, 0x00000000,
 170                           0x00000000, 0x00000000, 0x00000000,
 171                           0x00000000, 0x00000000, 0x00000000,
 172                           0x00000000, 0x00000000, 0x00000000,
 173                           0x00000000, 0x00000000, 0x00000000 },
 174         },
 175         { 0x1000, {
 176                           0x000fa400, 0x000fa400, 0x09625902,
 177                           0x000003f8, 0x00000403, 0x3de0d9f0,
 178                           0x001fffed, 0x00000804, 0x3cc1f9c3,
 179                           0x001003de, 0x00000c01, 0x3cb34d7f,
 180                           0x002003d2, 0x00000c00, 0x3d24a92d,
 181                           0x00200bca, 0x00000bff, 0x3df600d2,
 182                           0x002013cc, 0x000007ff, 0x3ed70c7e,
 183                           0x00100fde, 0x00000000, 0x3f87c036 },
 184         },
 185         { 0x1200, {
 186                           0x002ffff1, 0x002ffff1, 0x02a0a9c8,
 187                           0x002003e7, 0x001ffffa, 0x000185bc,
 188                           0x002007dc, 0x000003ff, 0x3e52859c,
 189                           0x00200bd4, 0x00000002, 0x3d53996b,
 190                           0x00100fd0, 0x00000403, 0x3d04ad2d,
 191                           0x00000bd5, 0x00000403, 0x3d35ace7,
 192                           0x3ff003e4, 0x00000801, 0x3dc674a1,
 193                           0x3fffe800, 0x00000800, 0x3e76f461 },
 194         },
 195         { 0x1400, {
 196                           0x00100be3, 0x00100be3, 0x04d1359a,
 197                           0x00000fdb, 0x002003ed, 0x0211fd93,
 198                           0x00000fd6, 0x002003f4, 0x0002d97b,
 199                           0x000007d6, 0x002ffffb, 0x3e93b956,
 200                           0x3ff003da, 0x001003ff, 0x3db49926,
 201                           0x3fffefe9, 0x00100001, 0x3d655cee,
 202                           0x3fffd400, 0x00000003, 0x3d65f4b6,
 203                           0x000fb421, 0x00000402, 0x3dc6547e },
 204         },
 205         { 0x1600, {
 206                           0x00000bdd, 0x00000bdd, 0x06519578,
 207                           0x3ff007da, 0x00000be3, 0x03c24973,
 208                           0x3ff003d9, 0x00000be9, 0x01b30d5f,
 209                           0x3ffff7df, 0x001003f1, 0x0003c542,
 210                           0x000fdfec, 0x001003f7, 0x3ec4711d,
 211                           0x000fc400, 0x002ffffd, 0x3df504f1,
 212                           0x001fa81a, 0x002ffc00, 0x3d957cc2,
 213                           0x002f8c3c, 0x00100000, 0x3db5c891 },
 214         },
 215         { 0x1800, {
 216                           0x3ff003dc, 0x3ff003dc, 0x0791e558,
 217                           0x000ff7dd, 0x3ff007de, 0x05328554,
 218                           0x000fe7e3, 0x3ff00be2, 0x03232546,
 219                           0x000fd7ee, 0x000007e9, 0x0143bd30,
 220                           0x001fb800, 0x000007ee, 0x00044511,
 221                           0x002fa015, 0x000007f4, 0x3ef4bcee,
 222                           0x002f8832, 0x001003f9, 0x3e4514c7,
 223                           0x001f7853, 0x001003fd, 0x3de54c9f },
 224         },
 225         { 0x1a00, {
 226                           0x000fefe0, 0x000fefe0, 0x08721d3c,
 227                           0x001fdbe7, 0x000ffbde, 0x0652a139,
 228                           0x001fcbf0, 0x000003df, 0x0463292e,
 229                           0x002fb3ff, 0x3ff007e3, 0x0293a91d,
 230                           0x002f9c12, 0x3ff00be7, 0x01241905,
 231                           0x001f8c29, 0x000007ed, 0x3fe470eb,
 232                           0x000f7c46, 0x000007f2, 0x3f04b8ca,
 233                           0x3fef7865, 0x000007f6, 0x3e74e4a8 },
 234         },
 235         { 0x1c00, {
 236                           0x001fd3e9, 0x001fd3e9, 0x08f23d26,
 237                           0x002fbff3, 0x001fe3e4, 0x0712ad23,
 238                           0x002fa800, 0x000ff3e0, 0x05631d1b,
 239                           0x001f9810, 0x000ffbe1, 0x03b3890d,
 240                           0x000f8c23, 0x000003e3, 0x0233e8fa,
 241                           0x3fef843b, 0x000003e7, 0x00f430e4,
 242                           0x3fbf8456, 0x3ff00bea, 0x00046cc8,
 243                           0x3f8f8c72, 0x3ff00bef, 0x3f3490ac },
 244         },
 245         { 0x1e00, {
 246                           0x001fbbf4, 0x001fbbf4, 0x09425112,
 247                           0x001fa800, 0x002fc7ed, 0x0792b110,
 248                           0x000f980e, 0x001fdbe6, 0x0613110a,
 249                           0x3fff8c20, 0x001fe7e3, 0x04a368fd,
 250                           0x3fcf8c33, 0x000ff7e2, 0x0343b8ed,
 251                           0x3f9f8c4a, 0x000fffe3, 0x0203f8da,
 252                           0x3f5f9c61, 0x000003e6, 0x00e428c5,
 253                           0x3f1fb07b, 0x000003eb, 0x3fe440af },
 254         },
 255         { 0x2000, {
 256                           0x000fa400, 0x000fa400, 0x09625902,
 257                           0x3fff980c, 0x001fb7f5, 0x0812b0ff,
 258                           0x3fdf901c, 0x001fc7ed, 0x06b2fcfa,
 259                           0x3faf902d, 0x001fd3e8, 0x055348f1,
 260                           0x3f7f983f, 0x001fe3e5, 0x04038ce3,
 261                           0x3f3fa454, 0x001fefe3, 0x02e3c8d1,
 262                           0x3f0fb86a, 0x001ff7e4, 0x01c3e8c0,
 263                           0x3ecfd880, 0x000fffe6, 0x00c404ac },
 264         },
 265         { 0x2200, {
 266                           0x3fdf9c0b, 0x3fdf9c0b, 0x09725cf4,
 267                           0x3fbf9818, 0x3fffa400, 0x0842a8f1,
 268                           0x3f8f9827, 0x000fb3f7, 0x0702f0ec,
 269                           0x3f5fa037, 0x000fc3ef, 0x05d330e4,
 270                           0x3f2fac49, 0x001fcfea, 0x04a364d9,
 271                           0x3effc05c, 0x001fdbe7, 0x038394ca,
 272                           0x3ecfdc6f, 0x001fe7e6, 0x0273b0bb,
 273                           0x3ea00083, 0x001fefe6, 0x0183c0a9 },
 274         },
 275         { 0x2400, {
 276                           0x3f9fa014, 0x3f9fa014, 0x098260e6,
 277                           0x3f7f9c23, 0x3fcf9c0a, 0x08629ce5,
 278                           0x3f4fa431, 0x3fefa400, 0x0742d8e1,
 279                           0x3f1fb440, 0x3fffb3f8, 0x062310d9,
 280                           0x3eefc850, 0x000fbbf2, 0x050340d0,
 281                           0x3ecfe062, 0x000fcbec, 0x041364c2,
 282                           0x3ea00073, 0x001fd3ea, 0x03037cb5,
 283                           0x3e902086, 0x001fdfe8, 0x022388a5 },
 284         },
 285         { 0x2600, {
 286                           0x3f5fa81e, 0x3f5fa81e, 0x096258da,
 287                           0x3f3fac2b, 0x3f8fa412, 0x088290d8,
 288                           0x3f0fbc38, 0x3fafa408, 0x0772c8d5,
 289                           0x3eefcc47, 0x3fcfa800, 0x0672f4ce,
 290                           0x3ecfe456, 0x3fefaffa, 0x05531cc6,
 291                           0x3eb00066, 0x3fffbbf3, 0x047334bb,
 292                           0x3ea01c77, 0x000fc7ee, 0x039348ae,
 293                           0x3ea04486, 0x000fd3eb, 0x02b350a1 },
 294         },
 295         { 0x2800, {
 296                           0x3f2fb426, 0x3f2fb426, 0x094250ce,
 297                           0x3f0fc032, 0x3f4fac1b, 0x086284cd,
 298                           0x3eefd040, 0x3f7fa811, 0x0782acc9,
 299                           0x3ecfe84c, 0x3f9fa807, 0x06a2d8c4,
 300                           0x3eb0005b, 0x3fbfac00, 0x05b2f4bc,
 301                           0x3eb0186a, 0x3fdfb3fa, 0x04c308b4,
 302                           0x3eb04077, 0x3fefbbf4, 0x03f31ca8,
 303                           0x3ec06884, 0x000fbff2, 0x03031c9e },
 304         },
 305         { 0x2a00, {
 306                           0x3f0fc42d, 0x3f0fc42d, 0x090240c4,
 307                           0x3eefd439, 0x3f2fb822, 0x08526cc2,
 308                           0x3edfe845, 0x3f4fb018, 0x078294bf,
 309                           0x3ec00051, 0x3f6fac0f, 0x06b2b4bb,
 310                           0x3ec0185f, 0x3f8fac07, 0x05e2ccb4,
 311                           0x3ec0386b, 0x3fafac00, 0x0502e8ac,
 312                           0x3ed05c77, 0x3fcfb3fb, 0x0432f0a3,
 313                           0x3ef08482, 0x3fdfbbf6, 0x0372f898 },
 314         },
 315         { 0x2c00, {
 316                           0x3eefdc31, 0x3eefdc31, 0x08e238b8,
 317                           0x3edfec3d, 0x3f0fc828, 0x082258b9,
 318                           0x3ed00049, 0x3f1fc01e, 0x077278b6,
 319                           0x3ed01455, 0x3f3fb815, 0x06c294b2,
 320                           0x3ed03460, 0x3f5fb40d, 0x0602acac,
 321                           0x3ef0506c, 0x3f7fb006, 0x0542c0a4,
 322                           0x3f107476, 0x3f9fb400, 0x0472c89d,
 323                           0x3f309c80, 0x3fbfb7fc, 0x03b2cc94 },
 324         },
 325         { 0x2e00, {
 326                           0x3eefec37, 0x3eefec37, 0x088220b0,
 327                           0x3ee00041, 0x3effdc2d, 0x07f244ae,
 328                           0x3ee0144c, 0x3f0fd023, 0x07625cad,
 329                           0x3ef02c57, 0x3f1fc81a, 0x06c274a9,
 330                           0x3f004861, 0x3f3fbc13, 0x060288a6,
 331                           0x3f20686b, 0x3f5fb80c, 0x05529c9e,
 332                           0x3f408c74, 0x3f6fb805, 0x04b2ac96,
 333                           0x3f80ac7e, 0x3f8fb800, 0x0402ac8e },
 334         },
 335         { 0x3000, {
 336                           0x3ef0003a, 0x3ef0003a, 0x084210a6,
 337                           0x3ef01045, 0x3effec32, 0x07b228a7,
 338                           0x3f00284e, 0x3f0fdc29, 0x073244a4,
 339                           0x3f104058, 0x3f0fd420, 0x06a258a2,
 340                           0x3f305c62, 0x3f2fc818, 0x0612689d,
 341                           0x3f508069, 0x3f3fc011, 0x05728496,
 342                           0x3f80a072, 0x3f4fc00a, 0x04d28c90,
 343                           0x3fc0c07b, 0x3f6fbc04, 0x04429088 },
 344         },
 345         { 0x3200, {
 346                           0x3f00103e, 0x3f00103e, 0x07f1fc9e,
 347                           0x3f102447, 0x3f000035, 0x0782149d,
 348                           0x3f203c4f, 0x3f0ff02c, 0x07122c9c,
 349                           0x3f405458, 0x3f0fe424, 0x06924099,
 350                           0x3f607061, 0x3f1fd41d, 0x06024c97,
 351                           0x3f909068, 0x3f2fcc16, 0x05726490,
 352                           0x3fc0b070, 0x3f3fc80f, 0x04f26c8a,
 353                           0x0000d077, 0x3f4fc409, 0x04627484 },
 354         },
 355         { 0x3400, {
 356                           0x3f202040, 0x3f202040, 0x07a1e898,
 357                           0x3f303449, 0x3f100c38, 0x0741fc98,
 358                           0x3f504c50, 0x3f10002f, 0x06e21495,
 359                           0x3f706459, 0x3f1ff028, 0x06722492,
 360                           0x3fa08060, 0x3f1fe421, 0x05f2348f,
 361                           0x3fd09c67, 0x3f1fdc19, 0x05824c89,
 362                           0x0000bc6e, 0x3f2fd014, 0x04f25086,
 363                           0x0040dc74, 0x3f3fcc0d, 0x04825c7f },
 364         },
 365         { 0x3600, {
 366                           0x3f403042, 0x3f403042, 0x0761d890,
 367                           0x3f504848, 0x3f301c3b, 0x0701f090,
 368                           0x3f805c50, 0x3f200c33, 0x06a2008f,
 369                           0x3fa07458, 0x3f10002b, 0x06520c8d,
 370                           0x3fd0905e, 0x3f1ff424, 0x05e22089,
 371                           0x0000ac65, 0x3f1fe81d, 0x05823483,
 372                           0x0030cc6a, 0x3f2fdc18, 0x04f23c81,
 373                           0x0080e871, 0x3f2fd412, 0x0482407c },
 374         },
 375         { 0x3800, {
 376                           0x3f604043, 0x3f604043, 0x0721c88a,
 377                           0x3f80544a, 0x3f502c3c, 0x06d1d88a,
 378                           0x3fb06851, 0x3f301c35, 0x0681e889,
 379                           0x3fd08456, 0x3f30082f, 0x0611fc88,
 380                           0x00009c5d, 0x3f200027, 0x05d20884,
 381                           0x0030b863, 0x3f2ff421, 0x05621880,
 382                           0x0070d468, 0x3f2fe81b, 0x0502247c,
 383                           0x00c0ec6f, 0x3f2fe015, 0x04a22877 },
 384         },
 385         { 0x3a00, {
 386                           0x3f904c44, 0x3f904c44, 0x06e1b884,
 387                           0x3fb0604a, 0x3f70383e, 0x0691c885,
 388                           0x3fe07451, 0x3f502c36, 0x0661d483,
 389                           0x00009055, 0x3f401831, 0x0601ec81,
 390                           0x0030a85b, 0x3f300c2a, 0x05b1f480,
 391                           0x0070c061, 0x3f300024, 0x0562047a,
 392                           0x00b0d867, 0x3f3ff41e, 0x05020c77,
 393                           0x00f0f46b, 0x3f2fec19, 0x04a21474 },
 394         },
 395         { 0x3c00, {
 396                           0x3fb05c43, 0x3fb05c43, 0x06c1b07e,
 397                           0x3fe06c4b, 0x3f902c3f, 0x0681c081,
 398                           0x0000844f, 0x3f703838, 0x0631cc7d,
 399                           0x00309855, 0x3f602433, 0x05d1d47e,
 400                           0x0060b459, 0x3f50142e, 0x0581e47b,
 401                           0x00a0c85f, 0x3f400828, 0x0531f078,
 402                           0x00e0e064, 0x3f300021, 0x0501fc73,
 403                           0x00b0fc6a, 0x3f3ff41d, 0x04a20873 },
 404         },
 405         { 0x3e00, {
 406                           0x3fe06444, 0x3fe06444, 0x0681a07a,
 407                           0x00007849, 0x3fc0503f, 0x0641b07a,
 408                           0x0020904d, 0x3fa0403a, 0x05f1c07a,
 409                           0x0060a453, 0x3f803034, 0x05c1c878,
 410                           0x0090b858, 0x3f70202f, 0x0571d477,
 411                           0x00d0d05d, 0x3f501829, 0x0531e073,
 412                           0x0110e462, 0x3f500825, 0x04e1e471,
 413                           0x01510065, 0x3f40001f, 0x04a1f06d },
 414         },
 415         { 0x4000, {
 416                           0x00007044, 0x00007044, 0x06519476,
 417                           0x00208448, 0x3fe05c3f, 0x0621a476,
 418                           0x0050984d, 0x3fc04c3a, 0x05e1b075,
 419                           0x0080ac52, 0x3fa03c35, 0x05a1b875,
 420                           0x00c0c056, 0x3f803030, 0x0561c473,
 421                           0x0100d45b, 0x3f70202b, 0x0521d46f,
 422                           0x0140e860, 0x3f601427, 0x04d1d46e,
 423                           0x01810064, 0x3f500822, 0x0491dc6b },
 424         },
 425         { 0x5000, {
 426                           0x0110a442, 0x0110a442, 0x0551545e,
 427                           0x0140b045, 0x00e0983f, 0x0531585f,
 428                           0x0160c047, 0x00c08c3c, 0x0511645e,
 429                           0x0190cc4a, 0x00908039, 0x04f1685f,
 430                           0x01c0dc4c, 0x00707436, 0x04d1705e,
 431                           0x0200e850, 0x00506833, 0x04b1785b,
 432                           0x0230f453, 0x00305c30, 0x0491805a,
 433                           0x02710056, 0x0010542d, 0x04718059 },
 434         },
 435         { 0x6000, {
 436                           0x01c0bc40, 0x01c0bc40, 0x04c13052,
 437                           0x01e0c841, 0x01a0b43d, 0x04c13851,
 438                           0x0210cc44, 0x0180a83c, 0x04a13453,
 439                           0x0230d845, 0x0160a03a, 0x04913c52,
 440                           0x0260e047, 0x01409838, 0x04714052,
 441                           0x0280ec49, 0x01208c37, 0x04514c50,
 442                           0x02b0f44b, 0x01008435, 0x04414c50,
 443                           0x02d1004c, 0x00e07c33, 0x0431544f },
 444         },
 445         { 0x7000, {
 446                           0x0230c83e, 0x0230c83e, 0x04711c4c,
 447                           0x0250d03f, 0x0210c43c, 0x0471204b,
 448                           0x0270d840, 0x0200b83c, 0x0451244b,
 449                           0x0290dc42, 0x01e0b43a, 0x0441244c,
 450                           0x02b0e443, 0x01c0b038, 0x0441284b,
 451                           0x02d0ec44, 0x01b0a438, 0x0421304a,
 452                           0x02f0f445, 0x0190a036, 0x04213449,
 453                           0x0310f847, 0x01709c34, 0x04213848 },
 454         },
 455         { 0x8000, {
 456                           0x0280d03d, 0x0280d03d, 0x04310c48,
 457                           0x02a0d43e, 0x0270c83c, 0x04311047,
 458                           0x02b0dc3e, 0x0250c83a, 0x04311447,
 459                           0x02d0e040, 0x0240c03a, 0x04211446,
 460                           0x02e0e840, 0x0220bc39, 0x04111847,
 461                           0x0300e842, 0x0210b438, 0x04012445,
 462                           0x0310f043, 0x0200b037, 0x04012045,
 463                           0x0330f444, 0x01e0ac36, 0x03f12445 },
 464         },
 465         { 0xefff, {
 466                           0x0340dc3a, 0x0340dc3a, 0x03b0ec40,
 467                           0x0340e03a, 0x0330e039, 0x03c0f03e,
 468                           0x0350e03b, 0x0330dc39, 0x03c0ec3e,
 469                           0x0350e43a, 0x0320dc38, 0x03c0f43e,
 470                           0x0360e43b, 0x0320d839, 0x03b0f03e,
 471                           0x0360e83b, 0x0310d838, 0x03c0fc3b,
 472                           0x0370e83b, 0x0310d439, 0x03a0f83d,
 473                           0x0370e83c, 0x0300d438, 0x03b0fc3c },
 474         }
 475 };
 476
 477 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs)
 478 {
 479         int i;
 480         const struct vin_coeff *p_prev_set = NULL;
 481         const struct vin_coeff *p_set = NULL;
 482
 483         /* Look for suitable coefficient values */
 484         for (i = 0; i < ARRAY_SIZE(vin_coeff_set); i++) {
 485                 p_prev_set = p_set;
 486                 p_set = &vin_coeff_set[i];
 487
 488                 if (xs < p_set->xs_value)
 489                         break;
 490         }
 491
 492         /* Use previous value if its XS value is closer */
 493         if (p_prev_set &&
 494             xs - p_prev_set->xs_value < p_set->xs_value - xs)
 495                 p_set = p_prev_set;
 496
 497         /* Set coefficient registers */
 498         rvin_write(vin, p_set->coeff_set[0], VNC1A_REG);
 499         rvin_write(vin, p_set->coeff_set[1], VNC1B_REG);
 500         rvin_write(vin, p_set->coeff_set[2], VNC1C_REG);
 501
 502         rvin_write(vin, p_set->coeff_set[3], VNC2A_REG);
 503         rvin_write(vin, p_set->coeff_set[4], VNC2B_REG);
 504         rvin_write(vin, p_set->coeff_set[5], VNC2C_REG);
 505
 506         rvin_write(vin, p_set->coeff_set[6], VNC3A_REG);
 507         rvin_write(vin, p_set->coeff_set[7], VNC3B_REG);
 508         rvin_write(vin, p_set->coeff_set[8], VNC3C_REG);
 509
 510         rvin_write(vin, p_set->coeff_set[9], VNC4A_REG);
 511         rvin_write(vin, p_set->coeff_set[10], VNC4B_REG);
 512         rvin_write(vin, p_set->coeff_set[11], VNC4C_REG);
 513
 514         rvin_write(vin, p_set->coeff_set[12], VNC5A_REG);
 515         rvin_write(vin, p_set->coeff_set[13], VNC5B_REG);
 516         rvin_write(vin, p_set->coeff_set[14], VNC5C_REG);
 517
 518         rvin_write(vin, p_set->coeff_set[15], VNC6A_REG);
 519         rvin_write(vin, p_set->coeff_set[16], VNC6B_REG);
 520         rvin_write(vin, p_set->coeff_set[17], VNC6C_REG);
 521
 522         rvin_write(vin, p_set->coeff_set[18], VNC7A_REG);
 523         rvin_write(vin, p_set->coeff_set[19], VNC7B_REG);
 524         rvin_write(vin, p_set->coeff_set[20], VNC7C_REG);
 525
 526         rvin_write(vin, p_set->coeff_set[21], VNC8A_REG);
 527         rvin_write(vin, p_set->coeff_set[22], VNC8B_REG);
 528         rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);
 529 }
 530
 531 static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin)
 532 {
 533         unsigned int crop_height;
 534         u32 xs, ys;
 535
 536         /* Set scaling coefficient */
 537         crop_height = vin->crop.height;
 538         if (V4L2_FIELD_IS_INTERLACED(vin->format.field))
 539                 crop_height *= 2;
 540
 541         ys = 0;
 542         if (crop_height != vin->compose.height)
 543                 ys = (4096 * crop_height) / vin->compose.height;
 544         rvin_write(vin, ys, VNYS_REG);
 545
 546         xs = 0;
 547         if (vin->crop.width != vin->compose.width)
 548                 xs = (4096 * vin->crop.width) / vin->compose.width;
 549
 550         /* Horizontal upscaling is up to double size */
 551         if (xs > 0 && xs < 2048)
 552                 xs = 2048;
 553
 554         rvin_write(vin, xs, VNXS_REG);
 555
 556         /* Horizontal upscaling is done out by scaling down from double size */
 557         if (xs < 4096)
 558                 xs *= 2;
 559
 560         rvin_set_coeff(vin, xs);
 561
 562         /* Set Start/End Pixel/Line Post-Clip */
 563         rvin_write(vin, 0, VNSPPOC_REG);
 564         rvin_write(vin, 0, VNSLPOC_REG);
 565         rvin_write(vin, vin->format.width - 1, VNEPPOC_REG);
 566
 567         if (V4L2_FIELD_IS_INTERLACED(vin->format.field))
 568                 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG);
 569         else
 570                 rvin_write(vin, vin->format.height - 1, VNELPOC_REG);
 571
 572         vin_dbg(vin,
 573                 "Pre-Clip: %ux%u@%u:%u YS: %d XS: %d Post-Clip: %ux%u@%u:%u\n",
 574                 vin->crop.width, vin->crop.height, vin->crop.left,
 575                 vin->crop.top, ys, xs, vin->format.width, vin->format.height,
 576                 0, 0);
 577 }
 578
 579 void rvin_crop_scale_comp(struct rvin_dev *vin)
 580 {
 581         const struct rvin_video_format *fmt;
 582         u32 stride;
 583
 584         /* Set Start/End Pixel/Line Pre-Clip */
 585         rvin_write(vin, vin->crop.left, VNSPPRC_REG);
 586         rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
 587         rvin_write(vin, vin->crop.top, VNSLPRC_REG);
 588         rvin_write(vin, vin->crop.top + vin->crop.height - 1, VNELPRC_REG);
 589
 590
 591         /* TODO: Add support for the UDS scaler. */
 592         if (vin->info->model != RCAR_GEN3)
 593                 rvin_crop_scale_comp_gen2(vin);
 594
 595         fmt = rvin_format_from_pixel(vin, vin->format.pixelformat);
 596         stride = vin->format.bytesperline / fmt->bpp;
 597         rvin_write(vin, stride, VNIS_REG);
 598 }
 599
 600 /* -----------------------------------------------------------------------------
 601  * Hardware setup
 602  */
 603
 604 static int rvin_setup(struct rvin_dev *vin)
 605 {
 606         u32 vnmc, dmr, dmr2, interrupts;
 607         bool progressive = false, output_is_yuv = false, input_is_yuv = false;
 608
 609         switch (vin->format.field) {
 610         case V4L2_FIELD_TOP:
 611                 vnmc = VNMC_IM_ODD;
 612                 break;
 613         case V4L2_FIELD_BOTTOM:
 614                 vnmc = VNMC_IM_EVEN;
 615                 break;
 616         case V4L2_FIELD_INTERLACED:
 617                 /* Default to TB */
 618                 vnmc = VNMC_IM_FULL;
 619                 /* Use BT if video standard can be read and is 60 Hz format */
 620                 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60)
 621                         vnmc = VNMC_IM_FULL | VNMC_FOC;
 622                 break;
 623         case V4L2_FIELD_INTERLACED_TB:
 624                 vnmc = VNMC_IM_FULL;
 625                 break;
 626         case V4L2_FIELD_INTERLACED_BT:
 627                 vnmc = VNMC_IM_FULL | VNMC_FOC;
 628                 break;
 629         case V4L2_FIELD_NONE:
 630                 vnmc = VNMC_IM_ODD_EVEN;
 631                 progressive = true;
 632                 break;
 633         case V4L2_FIELD_ALTERNATE:
 634                 vnmc = VNMC_IM_ODD_EVEN;
 635                 break;
 636         default:
 637                 vnmc = VNMC_IM_ODD;
 638                 break;
 639         }
 640
 641         /*
 642          * Input interface
 643          */
 644         switch (vin->mbus_code) {
 645         case MEDIA_BUS_FMT_YUYV8_1X16:
 646                 /* BT.601/BT.1358 16bit YCbCr422 */
 647                 vnmc |= VNMC_INF_YUV16;
 648                 input_is_yuv = true;
 649                 break;
 650         case MEDIA_BUS_FMT_UYVY8_1X16:
 651                 vnmc |= VNMC_INF_YUV16 | VNMC_YCAL;
 652                 input_is_yuv = true;
 653                 break;
 654         case MEDIA_BUS_FMT_UYVY8_2X8:
 655                 /* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
 656                 if (!vin->is_csi &&
 657                     vin->parallel->mbus_type == V4L2_MBUS_BT656)
 658                         vnmc |= VNMC_INF_YUV8_BT656;
 659                 else
 660                         vnmc |= VNMC_INF_YUV8_BT601;
 661
 662                 input_is_yuv = true;
 663                 break;
 664         case MEDIA_BUS_FMT_RGB888_1X24:
 665                 vnmc |= VNMC_INF_RGB888;
 666                 break;
 667         case MEDIA_BUS_FMT_UYVY10_2X10:
 668                 /* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
 669                 if (!vin->is_csi &&
 670                     vin->parallel->mbus_type == V4L2_MBUS_BT656)
 671                         vnmc |= VNMC_INF_YUV10_BT656;
 672                 else
 673                         vnmc |= VNMC_INF_YUV10_BT601;
 674
 675                 input_is_yuv = true;
 676                 break;
 677         default:
 678                 break;
 679         }
 680
 681         /* Enable VSYNC Field Toggle mode after one VSYNC input */
 682         if (vin->info->model == RCAR_GEN3)
 683                 dmr2 = VNDMR2_FTEV;
 684         else
 685                 dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
 686
 687         if (!vin->is_csi) {
 688                 /* Hsync Signal Polarity Select */
 689                 if (!(vin->parallel->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
 690                         dmr2 |= VNDMR2_HPS;
 691
 692                 /* Vsync Signal Polarity Select */
 693                 if (!(vin->parallel->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
 694                         dmr2 |= VNDMR2_VPS;
 695
 696                 /* Data Enable Polarity Select */
 697                 if (vin->parallel->mbus_flags & V4L2_MBUS_DATA_ENABLE_LOW)
 698                         dmr2 |= VNDMR2_CES;
 699         }
 700
 701         /*
 702          * Output format
 703          */
 704         switch (vin->format.pixelformat) {
 705         case V4L2_PIX_FMT_NV12:
 706         case V4L2_PIX_FMT_NV16:
 707                 rvin_write(vin,
 708                            ALIGN(vin->format.bytesperline * vin->format.height,
 709                                  0x80), VNUVAOF_REG);
 710                 dmr = vin->format.pixelformat == V4L2_PIX_FMT_NV12 ?
 711                         VNDMR_DTMD_YCSEP_420 : VNDMR_DTMD_YCSEP;
 712                 output_is_yuv = true;
 713                 break;
 714         case V4L2_PIX_FMT_YUYV:
 715                 dmr = VNDMR_BPSM;
 716                 output_is_yuv = true;
 717                 break;
 718         case V4L2_PIX_FMT_UYVY:
 719                 dmr = 0;
 720                 output_is_yuv = true;
 721                 break;
 722         case V4L2_PIX_FMT_XRGB555:
 723                 dmr = VNDMR_DTMD_ARGB;
 724                 break;
 725         case V4L2_PIX_FMT_RGB565:
 726                 dmr = 0;
 727                 break;
 728         case V4L2_PIX_FMT_XBGR32:
 729                 /* Note: not supported on M1 */
 730                 dmr = VNDMR_EXRGB;
 731                 break;
 732         case V4L2_PIX_FMT_ARGB555:
 733                 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB;
 734                 break;
 735         case V4L2_PIX_FMT_ABGR32:
 736                 dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB;
 737                 break;
 738         default:
 739                 vin_err(vin, "Invalid pixelformat (0x%x)\n",
 740                         vin->format.pixelformat);
 741                 return -EINVAL;
 742         }
 743
 744         /* Always update on field change */
 745         vnmc |= VNMC_VUP;
 746
 747         /* If input and output use the same colorspace, use bypass mode */
 748         if (input_is_yuv == output_is_yuv)
 749                 vnmc |= VNMC_BPS;
 750
 751         if (vin->info->model == RCAR_GEN3) {
 752                 /* Select between CSI-2 and parallel input */
 753                 if (vin->is_csi)
 754                         vnmc &= ~VNMC_DPINE;
 755                 else
 756                         vnmc |= VNMC_DPINE;
 757         }
 758
 759         /* Progressive or interlaced mode */
 760         interrupts = progressive ? VNIE_FIE : VNIE_EFE;
 761
 762         /* Ack interrupts */
 763         rvin_write(vin, interrupts, VNINTS_REG);
 764         /* Enable interrupts */
 765         rvin_write(vin, interrupts, VNIE_REG);
 766         /* Start capturing */
 767         rvin_write(vin, dmr, VNDMR_REG);
 768         rvin_write(vin, dmr2, VNDMR2_REG);
 769
 770         /* Enable module */
 771         rvin_write(vin, vnmc | VNMC_ME, VNMC_REG);
 772
 773         return 0;
 774 }
 775
 776 static void rvin_disable_interrupts(struct rvin_dev *vin)
 777 {
 778         rvin_write(vin, 0, VNIE_REG);
 779 }
 780
 781 static u32 rvin_get_interrupt_status(struct rvin_dev *vin)
 782 {
 783         return rvin_read(vin, VNINTS_REG);
 784 }
 785
 786 static void rvin_ack_interrupt(struct rvin_dev *vin)
 787 {
 788         rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG);
 789 }
 790
 791 static bool rvin_capture_active(struct rvin_dev *vin)
 792 {
 793         return rvin_read(vin, VNMS_REG) & VNMS_CA;
 794 }
 795
 796 static enum v4l2_field rvin_get_active_field(struct rvin_dev *vin, u32 vnms)
 797 {
 798         if (vin->format.field == V4L2_FIELD_ALTERNATE) {
 799                 /* If FS is set it is an Even field. */
 800                 if (vnms & VNMS_FS)
 801                         return V4L2_FIELD_BOTTOM;
 802                 return V4L2_FIELD_TOP;
 803         }
 804
 805         return vin->format.field;
 806 }
 807
 808 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)
 809 {
 810         const struct rvin_video_format *fmt;
 811         int offsetx, offsety;
 812         dma_addr_t offset;
 813
 814         fmt = rvin_format_from_pixel(vin, vin->format.pixelformat);
 815
 816         /*
 817          * There is no HW support for composition do the beast we can
 818          * by modifying the buffer offset
 819          */
 820         offsetx = vin->compose.left * fmt->bpp;
 821         offsety = vin->compose.top * vin->format.bytesperline;
 822         offset = addr + offsetx + offsety;
 823
 824         /*
 825          * The address needs to be 128 bytes aligned. Driver should never accept
 826          * settings that do not satisfy this in the first place...
 827          */
 828         if (WARN_ON((offsetx | offsety | offset) & HW_BUFFER_MASK))
 829                 return;
 830
 831         rvin_write(vin, offset, VNMB_REG(slot));
 832 }
 833
 834 /*
 835  * Moves a buffer from the queue to the HW slot. If no buffer is
 836  * available use the scratch buffer. The scratch buffer is never
 837  * returned to userspace, its only function is to enable the capture
 838  * loop to keep running.
 839  */
 840 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
 841 {
 842         struct rvin_buffer *buf;
 843         struct vb2_v4l2_buffer *vbuf;
 844         dma_addr_t phys_addr;
 845
 846         /* A already populated slot shall never be overwritten. */
 847         if (WARN_ON(vin->queue_buf[slot] != NULL))
 848                 return;
 849
 850         vin_dbg(vin, "Filling HW slot: %d\n", slot);
 851
 852         if (list_empty(&vin->buf_list)) {
 853                 vin->queue_buf[slot] = NULL;
 854                 phys_addr = vin->scratch_phys;
 855         } else {
 856                 /* Keep track of buffer we give to HW */
 857                 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);
 858                 vbuf = &buf->vb;
 859                 list_del_init(to_buf_list(vbuf));
 860                 vin->queue_buf[slot] = vbuf;
 861
 862                 /* Setup DMA */
 863                 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
 864         }
 865
 866         rvin_set_slot_addr(vin, slot, phys_addr);
 867 }
 868
 869 static int rvin_capture_start(struct rvin_dev *vin)
 870 {
 871         int slot, ret;
 872
 873         for (slot = 0; slot < HW_BUFFER_NUM; slot++)
 874                 rvin_fill_hw_slot(vin, slot);
 875
 876         rvin_crop_scale_comp(vin);
 877
 878         ret = rvin_setup(vin);
 879         if (ret)
 880                 return ret;
 881
 882         vin_dbg(vin, "Starting to capture\n");
 883
 884         /* Continuous Frame Capture Mode */
 885         rvin_write(vin, VNFC_C_FRAME, VNFC_REG);
 886
 887         vin->state = STARTING;
 888
 889         return 0;
 890 }
 891
 892 static void rvin_capture_stop(struct rvin_dev *vin)
 893 {
 894         /* Set continuous & single transfer off */
 895         rvin_write(vin, 0, VNFC_REG);
 896
 897         /* Disable module */
 898         rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG);
 899 }
 900
 901 /* -----------------------------------------------------------------------------
 902  * DMA Functions
 903  */
 904
 905 #define RVIN_TIMEOUT_MS 100
 906 #define RVIN_RETRIES 10
 907
 908 static irqreturn_t rvin_irq(int irq, void *data)
 909 {
 910         struct rvin_dev *vin = data;
 911         u32 int_status, vnms;
 912         int slot;
 913         unsigned int handled = 0;
 914         unsigned long flags;
 915
 916         spin_lock_irqsave(&vin->qlock, flags);
 917
 918         int_status = rvin_get_interrupt_status(vin);
 919         if (!int_status)
 920                 goto done;
 921
 922         rvin_ack_interrupt(vin);
 923         handled = 1;
 924
 925         /* Nothing to do if capture status is 'STOPPED' */
 926         if (vin->state == STOPPED) {
 927                 vin_dbg(vin, "IRQ while state stopped\n");
 928                 goto done;
 929         }
 930
 931         /* Nothing to do if capture status is 'STOPPING' */
 932         if (vin->state == STOPPING) {
 933                 vin_dbg(vin, "IRQ while state stopping\n");
 934                 goto done;
 935         }
 936
 937         /* Prepare for capture and update state */
 938         vnms = rvin_read(vin, VNMS_REG);
 939         slot = (vnms & VNMS_FBS_MASK) >> VNMS_FBS_SHIFT;
 940
 941         /*
 942          * To hand buffers back in a known order to userspace start
 943          * to capture first from slot 0.
 944          */
 945         if (vin->state == STARTING) {
 946                 if (slot != 0) {
 947                         vin_dbg(vin, "Starting sync slot: %d\n", slot);
 948                         goto done;
 949                 }
 950
 951                 vin_dbg(vin, "Capture start synced!\n");
 952                 vin->state = RUNNING;
 953         }
 954
 955         /* Capture frame */
 956         if (vin->queue_buf[slot]) {
 957                 vin->queue_buf[slot]->field = rvin_get_active_field(vin, vnms);
 958                 vin->queue_buf[slot]->sequence = vin->sequence;
 959                 vin->queue_buf[slot]->vb2_buf.timestamp = ktime_get_ns();
 960                 vb2_buffer_done(&vin->queue_buf[slot]->vb2_buf,
 961                                 VB2_BUF_STATE_DONE);
 962                 vin->queue_buf[slot] = NULL;
 963         } else {
 964                 /* Scratch buffer was used, dropping frame. */
 965                 vin_dbg(vin, "Dropping frame %u\n", vin->sequence);
 966         }
 967
 968         vin->sequence++;
 969
 970         /* Prepare for next frame */
 971         rvin_fill_hw_slot(vin, slot);
 972 done:
 973         spin_unlock_irqrestore(&vin->qlock, flags);
 974
 975         return IRQ_RETVAL(handled);
 976 }
 977
 978 /* Need to hold qlock before calling */
 979 static void return_all_buffers(struct rvin_dev *vin,
 980                                enum vb2_buffer_state state)
 981 {
 982         struct rvin_buffer *buf, *node;
 983         int i;
 984
 985         for (i = 0; i < HW_BUFFER_NUM; i++) {
 986                 if (vin->queue_buf[i]) {
 987                         vb2_buffer_done(&vin->queue_buf[i]->vb2_buf,
 988                                         state);
 989                         vin->queue_buf[i] = NULL;
 990                 }
 991         }
 992
 993         list_for_each_entry_safe(buf, node, &vin->buf_list, list) {
 994                 vb2_buffer_done(&buf->vb.vb2_buf, state);
 995                 list_del(&buf->list);
 996         }
 997 }
 998
 999 static int rvin_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
1000                             unsigned int *nplanes, unsigned int sizes[],
1001                             struct device *alloc_devs[])
1002
1003 {
1004         struct rvin_dev *vin = vb2_get_drv_priv(vq);
1005
1006         /* Make sure the image size is large enough. */
1007         if (*nplanes)
1008                 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0;
1009
1010         *nplanes = 1;
1011         sizes[0] = vin->format.sizeimage;
1012
1013         return 0;
1014 };
1015
1016 static int rvin_buffer_prepare(struct vb2_buffer *vb)
1017 {
1018         struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);
1019         unsigned long size = vin->format.sizeimage;
1020
1021         if (vb2_plane_size(vb, 0) < size) {
1022                 vin_err(vin, "buffer too small (%lu < %lu)\n",
1023                         vb2_plane_size(vb, 0), size);
1024                 return -EINVAL;
1025         }
1026
1027         vb2_set_plane_payload(vb, 0, size);
1028
1029         return 0;
1030 }
1031
1032 static void rvin_buffer_queue(struct vb2_buffer *vb)
1033 {
1034         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1035         struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);
1036         unsigned long flags;
1037
1038         spin_lock_irqsave(&vin->qlock, flags);
1039
1040         list_add_tail(to_buf_list(vbuf), &vin->buf_list);
1041
1042         spin_unlock_irqrestore(&vin->qlock, flags);
1043 }
1044
1045 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd,
1046                                    struct media_pad *pad)
1047 {
1048         struct v4l2_subdev_format fmt = {
1049                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1050         };
1051
1052         fmt.pad = pad->index;
1053         if (v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt))
1054                 return -EPIPE;
1055
1056         switch (fmt.format.code) {
1057         case MEDIA_BUS_FMT_YUYV8_1X16:
1058         case MEDIA_BUS_FMT_UYVY8_1X16:
1059         case MEDIA_BUS_FMT_UYVY8_2X8:
1060         case MEDIA_BUS_FMT_UYVY10_2X10:
1061         case MEDIA_BUS_FMT_RGB888_1X24:
1062                 vin->mbus_code = fmt.format.code;
1063                 break;
1064         default:
1065                 return -EPIPE;
1066         }
1067
1068         switch (fmt.format.field) {
1069         case V4L2_FIELD_TOP:
1070         case V4L2_FIELD_BOTTOM:
1071         case V4L2_FIELD_NONE:
1072         case V4L2_FIELD_INTERLACED_TB:
1073         case V4L2_FIELD_INTERLACED_BT:
1074         case V4L2_FIELD_INTERLACED:
1075         case V4L2_FIELD_SEQ_TB:
1076         case V4L2_FIELD_SEQ_BT:
1077                 /* Supported natively */
1078                 break;
1079         case V4L2_FIELD_ALTERNATE:
1080                 switch (vin->format.field) {
1081                 case V4L2_FIELD_TOP:
1082                 case V4L2_FIELD_BOTTOM:
1083                 case V4L2_FIELD_NONE:
1084                 case V4L2_FIELD_ALTERNATE:
1085                         break;
1086                 case V4L2_FIELD_INTERLACED_TB:
1087                 case V4L2_FIELD_INTERLACED_BT:
1088                 case V4L2_FIELD_INTERLACED:
1089                 case V4L2_FIELD_SEQ_TB:
1090                 case V4L2_FIELD_SEQ_BT:
1091                         /* Use VIN hardware to combine the two fields */
1092                         fmt.format.height *= 2;
1093                         break;
1094                 default:
1095                         return -EPIPE;
1096                 }
1097                 break;
1098         default:
1099                 return -EPIPE;
1100         }
1101
1102         if (fmt.format.width != vin->format.width ||
1103             fmt.format.height != vin->format.height ||
1104             fmt.format.code != vin->mbus_code)
1105                 return -EPIPE;
1106
1107         return 0;
1108 }
1109
1110 static int rvin_set_stream(struct rvin_dev *vin, int on)
1111 {
1112         struct media_pipeline *pipe;
1113         struct media_device *mdev;
1114         struct v4l2_subdev *sd;
1115         struct media_pad *pad;
1116         int ret;
1117
1118         /* No media controller used, simply pass operation to subdevice. */
1119         if (!vin->info->use_mc) {
1120                 ret = v4l2_subdev_call(vin->parallel->subdev, video, s_stream,
1121                                        on);
1122
1123                 return ret == -ENOIOCTLCMD ? 0 : ret;
1124         }
1125
1126         pad = media_entity_remote_pad(&vin->pad);
1127         if (!pad)
1128                 return -EPIPE;
1129
1130         sd = media_entity_to_v4l2_subdev(pad->entity);
1131
1132         if (!on) {
1133                 media_pipeline_stop(&vin->vdev.entity);
1134                 return v4l2_subdev_call(sd, video, s_stream, 0);
1135         }
1136
1137         ret = rvin_mc_validate_format(vin, sd, pad);
1138         if (ret)
1139                 return ret;
1140
1141         /*
1142          * The graph lock needs to be taken to protect concurrent
1143          * starts of multiple VIN instances as they might share
1144          * a common subdevice down the line and then should use
1145          * the same pipe.
1146          */
1147         mdev = vin->vdev.entity.graph_obj.mdev;
1148         mutex_lock(&mdev->graph_mutex);
1149         pipe = sd->entity.pipe ? sd->entity.pipe : &vin->vdev.pipe;
1150         ret = __media_pipeline_start(&vin->vdev.entity, pipe);
1151         mutex_unlock(&mdev->graph_mutex);
1152         if (ret)
1153                 return ret;
1154
1155         ret = v4l2_subdev_call(sd, video, s_stream, 1);
1156         if (ret == -ENOIOCTLCMD)
1157                 ret = 0;
1158         if (ret)
1159                 media_pipeline_stop(&vin->vdev.entity);
1160
1161         return ret;
1162 }
1163
1164 static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
1165 {
1166         struct rvin_dev *vin = vb2_get_drv_priv(vq);
1167         unsigned long flags;
1168         int ret;
1169
1170         /* Allocate scratch buffer. */
1171         vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,
1172                                           &vin->scratch_phys, GFP_KERNEL);
1173         if (!vin->scratch) {
1174                 spin_lock_irqsave(&vin->qlock, flags);
1175                 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1176                 spin_unlock_irqrestore(&vin->qlock, flags);
1177                 vin_err(vin, "Failed to allocate scratch buffer\n");
1178                 return -ENOMEM;
1179         }
1180
1181         ret = rvin_set_stream(vin, 1);
1182         if (ret) {
1183                 spin_lock_irqsave(&vin->qlock, flags);
1184                 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1185                 spin_unlock_irqrestore(&vin->qlock, flags);
1186                 goto out;
1187         }
1188
1189         spin_lock_irqsave(&vin->qlock, flags);
1190
1191         vin->sequence = 0;
1192
1193         ret = rvin_capture_start(vin);
1194         if (ret) {
1195                 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1196                 rvin_set_stream(vin, 0);
1197         }
1198
1199         spin_unlock_irqrestore(&vin->qlock, flags);
1200 out:
1201         if (ret)
1202                 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
1203                                   vin->scratch_phys);
1204
1205         return ret;
1206 }
1207
1208 static void rvin_stop_streaming(struct vb2_queue *vq)
1209 {
1210         struct rvin_dev *vin = vb2_get_drv_priv(vq);
1211         unsigned long flags;
1212         int retries = 0;
1213
1214         spin_lock_irqsave(&vin->qlock, flags);
1215
1216         vin->state = STOPPING;
1217
1218         /* Wait for streaming to stop */
1219         while (retries++ < RVIN_RETRIES) {
1220
1221                 rvin_capture_stop(vin);
1222
1223                 /* Check if HW is stopped */
1224                 if (!rvin_capture_active(vin)) {
1225                         vin->state = STOPPED;
1226                         break;
1227                 }
1228
1229                 spin_unlock_irqrestore(&vin->qlock, flags);
1230                 msleep(RVIN_TIMEOUT_MS);
1231                 spin_lock_irqsave(&vin->qlock, flags);
1232         }
1233
1234         if (vin->state != STOPPED) {
1235                 /*
1236                  * If this happens something have gone horribly wrong.
1237                  * Set state to stopped to prevent the interrupt handler
1238                  * to make things worse...
1239                  */
1240                 vin_err(vin, "Failed stop HW, something is seriously broken\n");
1241                 vin->state = STOPPED;
1242         }
1243
1244         /* Release all active buffers */
1245         return_all_buffers(vin, VB2_BUF_STATE_ERROR);
1246
1247         spin_unlock_irqrestore(&vin->qlock, flags);
1248
1249         rvin_set_stream(vin, 0);
1250
1251         /* disable interrupts */
1252         rvin_disable_interrupts(vin);
1253
1254         /* Free scratch buffer. */
1255         dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
1256                           vin->scratch_phys);
1257 }
1258
1259 static const struct vb2_ops rvin_qops = {
1260         .queue_setup            = rvin_queue_setup,
1261         .buf_prepare            = rvin_buffer_prepare,
1262         .buf_queue              = rvin_buffer_queue,
1263         .start_streaming        = rvin_start_streaming,
1264         .stop_streaming         = rvin_stop_streaming,
1265         .wait_prepare           = vb2_ops_wait_prepare,
1266         .wait_finish            = vb2_ops_wait_finish,
1267 };
1268
1269 void rvin_dma_unregister(struct rvin_dev *vin)
1270 {
1271         mutex_destroy(&vin->lock);
1272
1273         v4l2_device_unregister(&vin->v4l2_dev);
1274 }
1275
1276 int rvin_dma_register(struct rvin_dev *vin, int irq)
1277 {
1278         struct vb2_queue *q = &vin->queue;
1279         int i, ret;
1280
1281         /* Initialize the top-level structure */
1282         ret = v4l2_device_register(vin->dev, &vin->v4l2_dev);
1283         if (ret)
1284                 return ret;
1285
1286         mutex_init(&vin->lock);
1287         INIT_LIST_HEAD(&vin->buf_list);
1288
1289         spin_lock_init(&vin->qlock);
1290
1291         vin->state = STOPPED;
1292
1293         for (i = 0; i < HW_BUFFER_NUM; i++)
1294                 vin->queue_buf[i] = NULL;
1295
1296         /* buffer queue */
1297         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1298         q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
1299         q->lock = &vin->lock;
1300         q->drv_priv = vin;
1301         q->buf_struct_size = sizeof(struct rvin_buffer);
1302         q->ops = &rvin_qops;
1303         q->mem_ops = &vb2_dma_contig_memops;
1304         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1305         q->min_buffers_needed = 4;
1306         q->dev = vin->dev;
1307
1308         ret = vb2_queue_init(q);
1309         if (ret < 0) {
1310                 vin_err(vin, "failed to initialize VB2 queue\n");
1311                 goto error;
1312         }
1313
1314         /* irq */
1315         ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED,
1316                                KBUILD_MODNAME, vin);
1317         if (ret) {
1318                 vin_err(vin, "failed to request irq\n");
1319                 goto error;
1320         }
1321
1322         return 0;
1323 error:
1324         rvin_dma_unregister(vin);
1325
1326         return ret;
1327 }
1328
1329 /* -----------------------------------------------------------------------------
1330  * Gen3 CHSEL manipulation
1331  */
1332
1333 /*
1334  * There is no need to have locking around changing the routing
1335  * as it's only possible to do so when no VIN in the group is
1336  * streaming so nothing can race with the VNMC register.
1337  */
1338 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
1339 {
1340         u32 ifmd, vnmc;
1341         int ret;
1342
1343         ret = pm_runtime_get_sync(vin->dev);
1344         if (ret < 0)
1345                 return ret;
1346
1347         /* Make register writes take effect immediately. */
1348         vnmc = rvin_read(vin, VNMC_REG);
1349         rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG);
1350
1351         ifmd = VNCSI_IFMD_DES1 | VNCSI_IFMD_DES0 | VNCSI_IFMD_CSI_CHSEL(chsel);
1352
1353         rvin_write(vin, ifmd, VNCSI_IFMD_REG);
1354
1355         vin_dbg(vin, "Set IFMD 0x%x\n", ifmd);
1356
1357         /* Restore VNMC. */
1358         rvin_write(vin, vnmc, VNMC_REG);
1359
1360         pm_runtime_put(vin->dev);
1361
1362         return 0;
1363 }
1364
1365 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha)
1366 {
1367         unsigned long flags;
1368         u32 dmr;
1369
1370         spin_lock_irqsave(&vin->qlock, flags);
1371
1372         vin->alpha = alpha;
1373
1374         if (vin->state == STOPPED)
1375                 goto out;
1376
1377         switch (vin->format.pixelformat) {
1378         case V4L2_PIX_FMT_ARGB555:
1379                 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT;
1380                 if (vin->alpha)
1381                         dmr |= VNDMR_ABIT;
1382                 break;
1383         case V4L2_PIX_FMT_ABGR32:
1384                 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK;
1385                 dmr |= VNDMR_A8BIT(vin->alpha);
1386                 break;
1387         default:
1388                 goto out;
1389         }
1390
1391         rvin_write(vin, dmr,  VNDMR_REG);
1392 out:
1393         spin_unlock_irqrestore(&vin->qlock, flags);
1394 }