drivers/media/platform/rcar-vin/rcar-dma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Renesas R-Car VIN
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  * Copyright (C) 2011-2013 Renesas Solutions Corp.
   7  * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com>
   8  * Copyright (C) 2008 Magnus Damm
   9  *
  10  * Based on the soc-camera rcar_vin driver
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/pm_runtime.h>
  16
  17 #include <media/videobuf2-dma-contig.h>
  18
  19 #include "rcar-vin.h"
  20
  21 /* -----------------------------------------------------------------------------
  22  * HW Functions
  23  */
  24
  25 /* Register offsets for R-Car VIN */
  26 #define VNMC_REG        0x00    /* Video n Main Control Register */
  27 #define VNMS_REG        0x04    /* Video n Module Status Register */
  28 #define VNFC_REG        0x08    /* Video n Frame Capture Register */
  29 #define VNSLPRC_REG     0x0C    /* Video n Start Line Pre-Clip Register */
  30 #define VNELPRC_REG     0x10    /* Video n End Line Pre-Clip Register */
  31 #define VNSPPRC_REG     0x14    /* Video n Start Pixel Pre-Clip Register */
  32 #define VNEPPRC_REG     0x18    /* Video n End Pixel Pre-Clip Register */
  33 #define VNIS_REG        0x2C    /* Video n Image Stride Register */
  34 #define VNMB_REG(m)     (0x30 + ((m) << 2)) /* Video n Memory Base m Register */
  35 #define VNIE_REG        0x40    /* Video n Interrupt Enable Register */
  36 #define VNINTS_REG      0x44    /* Video n Interrupt Status Register */
  37 #define VNSI_REG        0x48    /* Video n Scanline Interrupt Register */
  38 #define VNMTC_REG       0x4C    /* Video n Memory Transfer Control Register */
  39 #define VNDMR_REG       0x58    /* Video n Data Mode Register */
  40 #define VNDMR2_REG      0x5C    /* Video n Data Mode Register 2 */
  41 #define VNUVAOF_REG     0x60    /* Video n UV Address Offset Register */
  42
  43 /* Register offsets specific for Gen2 */
  44 #define VNSLPOC_REG     0x1C    /* Video n Start Line Post-Clip Register */
  45 #define VNELPOC_REG     0x20    /* Video n End Line Post-Clip Register */
  46 #define VNSPPOC_REG     0x24    /* Video n Start Pixel Post-Clip Register */
  47 #define VNEPPOC_REG     0x28    /* Video n End Pixel Post-Clip Register */
  48 #define VNYS_REG        0x50    /* Video n Y Scale Register */
  49 #define VNXS_REG        0x54    /* Video n X Scale Register */
  50 #define VNC1A_REG       0x80    /* Video n Coefficient Set C1A Register */
  51 #define VNC1B_REG       0x84    /* Video n Coefficient Set C1B Register */
  52 #define VNC1C_REG       0x88    /* Video n Coefficient Set C1C Register */
  53 #define VNC2A_REG       0x90    /* Video n Coefficient Set C2A Register */
  54 #define VNC2B_REG       0x94    /* Video n Coefficient Set C2B Register */
  55 #define VNC2C_REG       0x98    /* Video n Coefficient Set C2C Register */
  56 #define VNC3A_REG       0xA0    /* Video n Coefficient Set C3A Register */
  57 #define VNC3B_REG       0xA4    /* Video n Coefficient Set C3B Register */
  58 #define VNC3C_REG       0xA8    /* Video n Coefficient Set C3C Register */
  59 #define VNC4A_REG       0xB0    /* Video n Coefficient Set C4A Register */
  60 #define VNC4B_REG       0xB4    /* Video n Coefficient Set C4B Register */
  61 #define VNC4C_REG       0xB8    /* Video n Coefficient Set C4C Register */
  62 #define VNC5A_REG       0xC0    /* Video n Coefficient Set C5A Register */
  63 #define VNC5B_REG       0xC4    /* Video n Coefficient Set C5B Register */
  64 #define VNC5C_REG       0xC8    /* Video n Coefficient Set C5C Register */
  65 #define VNC6A_REG       0xD0    /* Video n Coefficient Set C6A Register */
  66 #define VNC6B_REG       0xD4    /* Video n Coefficient Set C6B Register */
  67 #define VNC6C_REG       0xD8    /* Video n Coefficient Set C6C Register */
  68 #define VNC7A_REG       0xE0    /* Video n Coefficient Set C7A Register */
  69 #define VNC7B_REG       0xE4    /* Video n Coefficient Set C7B Register */
  70 #define VNC7C_REG       0xE8    /* Video n Coefficient Set C7C Register */
  71 #define VNC8A_REG       0xF0    /* Video n Coefficient Set C8A Register */
  72 #define VNC8B_REG       0xF4    /* Video n Coefficient Set C8B Register */
  73 #define VNC8C_REG       0xF8    /* Video n Coefficient Set C8C Register */
  74
  75 /* Register offsets specific for Gen3 */
  76 #define VNCSI_IFMD_REG          0x20 /* Video n CSI2 Interface Mode Register */
  77
  78 /* Register bit fields for R-Car VIN */
  79 /* Video n Main Control Register bits */
  80 #define VNMC_DPINE              (1 << 27) /* Gen3 specific */
  81 #define VNMC_SCLE               (1 << 26) /* Gen3 specific */
  82 #define VNMC_FOC                (1 << 21)
  83 #define VNMC_YCAL               (1 << 19)
  84 #define VNMC_INF_YUV8_BT656     (0 << 16)
  85 #define VNMC_INF_YUV8_BT601     (1 << 16)
  86 #define VNMC_INF_YUV10_BT656    (2 << 16)
  87 #define VNMC_INF_YUV10_BT601    (3 << 16)
  88 #define VNMC_INF_YUV16          (5 << 16)
  89 #define VNMC_INF_RGB888         (6 << 16)
  90 #define VNMC_VUP                (1 << 10)
  91 #define VNMC_IM_ODD             (0 << 3)
  92 #define VNMC_IM_ODD_EVEN        (1 << 3)
  93 #define VNMC_IM_EVEN            (2 << 3)
  94 #define VNMC_IM_FULL            (3 << 3)
  95 #define VNMC_BPS                (1 << 1)
  96 #define VNMC_ME                 (1 << 0)
  97
  98 /* Video n Module Status Register bits */
  99 #define VNMS_FBS_MASK           (3 << 3)
 100 #define VNMS_FBS_SHIFT          3
 101 #define VNMS_FS                 (1 << 2)
 102 #define VNMS_AV                 (1 << 1)
 103 #define VNMS_CA                 (1 << 0)
 104
 105 /* Video n Frame Capture Register bits */
 106 #define VNFC_C_FRAME            (1 << 1)
 107 #define VNFC_S_FRAME            (1 << 0)
 108
 109 /* Video n Interrupt Enable Register bits */
 110 #define VNIE_FIE                (1 << 4)
 111 #define VNIE_EFE                (1 << 1)
 112
 113 /* Video n Data Mode Register bits */
 114 #define VNDMR_A8BIT(n)          (((n) & 0xff) << 24)
 115 #define VNDMR_A8BIT_MASK        (0xff << 24)
 116 #define VNDMR_EXRGB             (1 << 8)
 117 #define VNDMR_BPSM              (1 << 4)
 118 #define VNDMR_ABIT              (1 << 2)
 119 #define VNDMR_DTMD_YCSEP        (1 << 1)
 120 #define VNDMR_DTMD_ARGB         (1 << 0)
 121
 122 /* Video n Data Mode Register 2 bits */
 123 #define VNDMR2_VPS              (1 << 30)
 124 #define VNDMR2_HPS              (1 << 29)
 125 #define VNDMR2_CES              (1 << 28)
 126 #define VNDMR2_FTEV             (1 << 17)
 127 #define VNDMR2_VLV(n)           ((n & 0xf) << 12)
 128
 129 /* Video n CSI2 Interface Mode Register (Gen3) */
 130 #define VNCSI_IFMD_DES1         (1 << 26)
 131 #define VNCSI_IFMD_DES0         (1 << 25)
 132 #define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
 133 #define VNCSI_IFMD_CSI_CHSEL_MASK 0xf
 134
 135 struct rvin_buffer {
 136         struct vb2_v4l2_buffer vb;
 137         struct list_head list;
 138 };
 139
 140 #define to_buf_list(vb2_buffer) (&container_of(vb2_buffer, \
 141                                                struct rvin_buffer, \
 142                                                vb)->list)
 143
 144 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset)
 145 {
 146         iowrite32(value, vin->base + offset);
 147 }
 148
 149 static u32 rvin_read(struct rvin_dev *vin, u32 offset)
 150 {
 151         return ioread32(vin->base + offset);
 152 }
 153
 154 /* -----------------------------------------------------------------------------
 155  * Crop and Scaling Gen2
 156  */
 157
 158 struct vin_coeff {
 159         unsigned short xs_value;
 160         u32 coeff_set[24];
 161 };
 162
 163 static const struct vin_coeff vin_coeff_set[] = {
 164         { 0x0000, {
 165                           0x00000000, 0x00000000, 0x00000000,
 166                           0x00000000, 0x00000000, 0x00000000,
 167                           0x00000000, 0x00000000, 0x00000000,
 168                           0x00000000, 0x00000000, 0x00000000,
 169                           0x00000000, 0x00000000, 0x00000000,
 170                           0x00000000, 0x00000000, 0x00000000,
 171                           0x00000000, 0x00000000, 0x00000000,
 172                           0x00000000, 0x00000000, 0x00000000 },
 173         },
 174         { 0x1000, {
 175                           0x000fa400, 0x000fa400, 0x09625902,
 176                           0x000003f8, 0x00000403, 0x3de0d9f0,
 177                           0x001fffed, 0x00000804, 0x3cc1f9c3,
 178                           0x001003de, 0x00000c01, 0x3cb34d7f,
 179                           0x002003d2, 0x00000c00, 0x3d24a92d,
 180                           0x00200bca, 0x00000bff, 0x3df600d2,
 181                           0x002013cc, 0x000007ff, 0x3ed70c7e,
 182                           0x00100fde, 0x00000000, 0x3f87c036 },
 183         },
 184         { 0x1200, {
 185                           0x002ffff1, 0x002ffff1, 0x02a0a9c8,
 186                           0x002003e7, 0x001ffffa, 0x000185bc,
 187                           0x002007dc, 0x000003ff, 0x3e52859c,
 188                           0x00200bd4, 0x00000002, 0x3d53996b,
 189                           0x00100fd0, 0x00000403, 0x3d04ad2d,
 190                           0x00000bd5, 0x00000403, 0x3d35ace7,
 191                           0x3ff003e4, 0x00000801, 0x3dc674a1,
 192                           0x3fffe800, 0x00000800, 0x3e76f461 },
 193         },
 194         { 0x1400, {
 195                           0x00100be3, 0x00100be3, 0x04d1359a,
 196                           0x00000fdb, 0x002003ed, 0x0211fd93,
 197                           0x00000fd6, 0x002003f4, 0x0002d97b,
 198                           0x000007d6, 0x002ffffb, 0x3e93b956,
 199                           0x3ff003da, 0x001003ff, 0x3db49926,
 200                           0x3fffefe9, 0x00100001, 0x3d655cee,
 201                           0x3fffd400, 0x00000003, 0x3d65f4b6,
 202                           0x000fb421, 0x00000402, 0x3dc6547e },
 203         },
 204         { 0x1600, {
 205                           0x00000bdd, 0x00000bdd, 0x06519578,
 206                           0x3ff007da, 0x00000be3, 0x03c24973,
 207                           0x3ff003d9, 0x00000be9, 0x01b30d5f,
 208                           0x3ffff7df, 0x001003f1, 0x0003c542,
 209                           0x000fdfec, 0x001003f7, 0x3ec4711d,
 210                           0x000fc400, 0x002ffffd, 0x3df504f1,
 211                           0x001fa81a, 0x002ffc00, 0x3d957cc2,
 212                           0x002f8c3c, 0x00100000, 0x3db5c891 },
 213         },
 214         { 0x1800, {
 215                           0x3ff003dc, 0x3ff003dc, 0x0791e558,
 216                           0x000ff7dd, 0x3ff007de, 0x05328554,
 217                           0x000fe7e3, 0x3ff00be2, 0x03232546,
 218                           0x000fd7ee, 0x000007e9, 0x0143bd30,
 219                           0x001fb800, 0x000007ee, 0x00044511,
 220                           0x002fa015, 0x000007f4, 0x3ef4bcee,
 221                           0x002f8832, 0x001003f9, 0x3e4514c7,
 222                           0x001f7853, 0x001003fd, 0x3de54c9f },
 223         },
 224         { 0x1a00, {
 225                           0x000fefe0, 0x000fefe0, 0x08721d3c,
 226                           0x001fdbe7, 0x000ffbde, 0x0652a139,
 227                           0x001fcbf0, 0x000003df, 0x0463292e,
 228                           0x002fb3ff, 0x3ff007e3, 0x0293a91d,
 229                           0x002f9c12, 0x3ff00be7, 0x01241905,
 230                           0x001f8c29, 0x000007ed, 0x3fe470eb,
 231                           0x000f7c46, 0x000007f2, 0x3f04b8ca,
 232                           0x3fef7865, 0x000007f6, 0x3e74e4a8 },
 233         },
 234         { 0x1c00, {
 235                           0x001fd3e9, 0x001fd3e9, 0x08f23d26,
 236                           0x002fbff3, 0x001fe3e4, 0x0712ad23,
 237                           0x002fa800, 0x000ff3e0, 0x05631d1b,
 238                           0x001f9810, 0x000ffbe1, 0x03b3890d,
 239                           0x000f8c23, 0x000003e3, 0x0233e8fa,
 240                           0x3fef843b, 0x000003e7, 0x00f430e4,
 241                           0x3fbf8456, 0x3ff00bea, 0x00046cc8,
 242                           0x3f8f8c72, 0x3ff00bef, 0x3f3490ac },
 243         },
 244         { 0x1e00, {
 245                           0x001fbbf4, 0x001fbbf4, 0x09425112,
 246                           0x001fa800, 0x002fc7ed, 0x0792b110,
 247                           0x000f980e, 0x001fdbe6, 0x0613110a,
 248                           0x3fff8c20, 0x001fe7e3, 0x04a368fd,
 249                           0x3fcf8c33, 0x000ff7e2, 0x0343b8ed,
 250                           0x3f9f8c4a, 0x000fffe3, 0x0203f8da,
 251                           0x3f5f9c61, 0x000003e6, 0x00e428c5,
 252                           0x3f1fb07b, 0x000003eb, 0x3fe440af },
 253         },
 254         { 0x2000, {
 255                           0x000fa400, 0x000fa400, 0x09625902,
 256                           0x3fff980c, 0x001fb7f5, 0x0812b0ff,
 257                           0x3fdf901c, 0x001fc7ed, 0x06b2fcfa,
 258                           0x3faf902d, 0x001fd3e8, 0x055348f1,
 259                           0x3f7f983f, 0x001fe3e5, 0x04038ce3,
 260                           0x3f3fa454, 0x001fefe3, 0x02e3c8d1,
 261                           0x3f0fb86a, 0x001ff7e4, 0x01c3e8c0,
 262                           0x3ecfd880, 0x000fffe6, 0x00c404ac },
 263         },
 264         { 0x2200, {
 265                           0x3fdf9c0b, 0x3fdf9c0b, 0x09725cf4,
 266                           0x3fbf9818, 0x3fffa400, 0x0842a8f1,
 267                           0x3f8f9827, 0x000fb3f7, 0x0702f0ec,
 268                           0x3f5fa037, 0x000fc3ef, 0x05d330e4,
 269                           0x3f2fac49, 0x001fcfea, 0x04a364d9,
 270                           0x3effc05c, 0x001fdbe7, 0x038394ca,
 271                           0x3ecfdc6f, 0x001fe7e6, 0x0273b0bb,
 272                           0x3ea00083, 0x001fefe6, 0x0183c0a9 },
 273         },
 274         { 0x2400, {
 275                           0x3f9fa014, 0x3f9fa014, 0x098260e6,
 276                           0x3f7f9c23, 0x3fcf9c0a, 0x08629ce5,
 277                           0x3f4fa431, 0x3fefa400, 0x0742d8e1,
 278                           0x3f1fb440, 0x3fffb3f8, 0x062310d9,
 279                           0x3eefc850, 0x000fbbf2, 0x050340d0,
 280                           0x3ecfe062, 0x000fcbec, 0x041364c2,
 281                           0x3ea00073, 0x001fd3ea, 0x03037cb5,
 282                           0x3e902086, 0x001fdfe8, 0x022388a5 },
 283         },
 284         { 0x2600, {
 285                           0x3f5fa81e, 0x3f5fa81e, 0x096258da,
 286                           0x3f3fac2b, 0x3f8fa412, 0x088290d8,
 287                           0x3f0fbc38, 0x3fafa408, 0x0772c8d5,
 288                           0x3eefcc47, 0x3fcfa800, 0x0672f4ce,
 289                           0x3ecfe456, 0x3fefaffa, 0x05531cc6,
 290                           0x3eb00066, 0x3fffbbf3, 0x047334bb,
 291                           0x3ea01c77, 0x000fc7ee, 0x039348ae,
 292                           0x3ea04486, 0x000fd3eb, 0x02b350a1 },
 293         },
 294         { 0x2800, {
 295                           0x3f2fb426, 0x3f2fb426, 0x094250ce,
 296                           0x3f0fc032, 0x3f4fac1b, 0x086284cd,
 297                           0x3eefd040, 0x3f7fa811, 0x0782acc9,
 298                           0x3ecfe84c, 0x3f9fa807, 0x06a2d8c4,
 299                           0x3eb0005b, 0x3fbfac00, 0x05b2f4bc,
 300                           0x3eb0186a, 0x3fdfb3fa, 0x04c308b4,
 301                           0x3eb04077, 0x3fefbbf4, 0x03f31ca8,
 302                           0x3ec06884, 0x000fbff2, 0x03031c9e },
 303         },
 304         { 0x2a00, {
 305                           0x3f0fc42d, 0x3f0fc42d, 0x090240c4,
 306                           0x3eefd439, 0x3f2fb822, 0x08526cc2,
 307                           0x3edfe845, 0x3f4fb018, 0x078294bf,
 308                           0x3ec00051, 0x3f6fac0f, 0x06b2b4bb,
 309                           0x3ec0185f, 0x3f8fac07, 0x05e2ccb4,
 310                           0x3ec0386b, 0x3fafac00, 0x0502e8ac,
 311                           0x3ed05c77, 0x3fcfb3fb, 0x0432f0a3,
 312                           0x3ef08482, 0x3fdfbbf6, 0x0372f898 },
 313         },
 314         { 0x2c00, {
 315                           0x3eefdc31, 0x3eefdc31, 0x08e238b8,
 316                           0x3edfec3d, 0x3f0fc828, 0x082258b9,
 317                           0x3ed00049, 0x3f1fc01e, 0x077278b6,
 318                           0x3ed01455, 0x3f3fb815, 0x06c294b2,
 319                           0x3ed03460, 0x3f5fb40d, 0x0602acac,
 320                           0x3ef0506c, 0x3f7fb006, 0x0542c0a4,
 321                           0x3f107476, 0x3f9fb400, 0x0472c89d,
 322                           0x3f309c80, 0x3fbfb7fc, 0x03b2cc94 },
 323         },
 324         { 0x2e00, {
 325                           0x3eefec37, 0x3eefec37, 0x088220b0,
 326                           0x3ee00041, 0x3effdc2d, 0x07f244ae,
 327                           0x3ee0144c, 0x3f0fd023, 0x07625cad,
 328                           0x3ef02c57, 0x3f1fc81a, 0x06c274a9,
 329                           0x3f004861, 0x3f3fbc13, 0x060288a6,
 330                           0x3f20686b, 0x3f5fb80c, 0x05529c9e,
 331                           0x3f408c74, 0x3f6fb805, 0x04b2ac96,
 332                           0x3f80ac7e, 0x3f8fb800, 0x0402ac8e },
 333         },
 334         { 0x3000, {
 335                           0x3ef0003a, 0x3ef0003a, 0x084210a6,
 336                           0x3ef01045, 0x3effec32, 0x07b228a7,
 337                           0x3f00284e, 0x3f0fdc29, 0x073244a4,
 338                           0x3f104058, 0x3f0fd420, 0x06a258a2,
 339                           0x3f305c62, 0x3f2fc818, 0x0612689d,
 340                           0x3f508069, 0x3f3fc011, 0x05728496,
 341                           0x3f80a072, 0x3f4fc00a, 0x04d28c90,
 342                           0x3fc0c07b, 0x3f6fbc04, 0x04429088 },
 343         },
 344         { 0x3200, {
 345                           0x3f00103e, 0x3f00103e, 0x07f1fc9e,
 346                           0x3f102447, 0x3f000035, 0x0782149d,
 347                           0x3f203c4f, 0x3f0ff02c, 0x07122c9c,
 348                           0x3f405458, 0x3f0fe424, 0x06924099,
 349                           0x3f607061, 0x3f1fd41d, 0x06024c97,
 350                           0x3f909068, 0x3f2fcc16, 0x05726490,
 351                           0x3fc0b070, 0x3f3fc80f, 0x04f26c8a,
 352                           0x0000d077, 0x3f4fc409, 0x04627484 },
 353         },
 354         { 0x3400, {
 355                           0x3f202040, 0x3f202040, 0x07a1e898,
 356                           0x3f303449, 0x3f100c38, 0x0741fc98,
 357                           0x3f504c50, 0x3f10002f, 0x06e21495,
 358                           0x3f706459, 0x3f1ff028, 0x06722492,
 359                           0x3fa08060, 0x3f1fe421, 0x05f2348f,
 360                           0x3fd09c67, 0x3f1fdc19, 0x05824c89,
 361                           0x0000bc6e, 0x3f2fd014, 0x04f25086,
 362                           0x0040dc74, 0x3f3fcc0d, 0x04825c7f },
 363         },
 364         { 0x3600, {
 365                           0x3f403042, 0x3f403042, 0x0761d890,
 366                           0x3f504848, 0x3f301c3b, 0x0701f090,
 367                           0x3f805c50, 0x3f200c33, 0x06a2008f,
 368                           0x3fa07458, 0x3f10002b, 0x06520c8d,
 369                           0x3fd0905e, 0x3f1ff424, 0x05e22089,
 370                           0x0000ac65, 0x3f1fe81d, 0x05823483,
 371                           0x0030cc6a, 0x3f2fdc18, 0x04f23c81,
 372                           0x0080e871, 0x3f2fd412, 0x0482407c },
 373         },
 374         { 0x3800, {
 375                           0x3f604043, 0x3f604043, 0x0721c88a,
 376                           0x3f80544a, 0x3f502c3c, 0x06d1d88a,
 377                           0x3fb06851, 0x3f301c35, 0x0681e889,
 378                           0x3fd08456, 0x3f30082f, 0x0611fc88,
 379                           0x00009c5d, 0x3f200027, 0x05d20884,
 380                           0x0030b863, 0x3f2ff421, 0x05621880,
 381                           0x0070d468, 0x3f2fe81b, 0x0502247c,
 382                           0x00c0ec6f, 0x3f2fe015, 0x04a22877 },
 383         },
 384         { 0x3a00, {
 385                           0x3f904c44, 0x3f904c44, 0x06e1b884,
 386                           0x3fb0604a, 0x3f70383e, 0x0691c885,
 387                           0x3fe07451, 0x3f502c36, 0x0661d483,
 388                           0x00009055, 0x3f401831, 0x0601ec81,
 389                           0x0030a85b, 0x3f300c2a, 0x05b1f480,
 390                           0x0070c061, 0x3f300024, 0x0562047a,
 391                           0x00b0d867, 0x3f3ff41e, 0x05020c77,
 392                           0x00f0f46b, 0x3f2fec19, 0x04a21474 },
 393         },
 394         { 0x3c00, {
 395                           0x3fb05c43, 0x3fb05c43, 0x06c1b07e,
 396                           0x3fe06c4b, 0x3f902c3f, 0x0681c081,
 397                           0x0000844f, 0x3f703838, 0x0631cc7d,
 398                           0x00309855, 0x3f602433, 0x05d1d47e,
 399                           0x0060b459, 0x3f50142e, 0x0581e47b,
 400                           0x00a0c85f, 0x3f400828, 0x0531f078,
 401                           0x00e0e064, 0x3f300021, 0x0501fc73,
 402                           0x00b0fc6a, 0x3f3ff41d, 0x04a20873 },
 403         },
 404         { 0x3e00, {
 405                           0x3fe06444, 0x3fe06444, 0x0681a07a,
 406                           0x00007849, 0x3fc0503f, 0x0641b07a,
 407                           0x0020904d, 0x3fa0403a, 0x05f1c07a,
 408                           0x0060a453, 0x3f803034, 0x05c1c878,
 409                           0x0090b858, 0x3f70202f, 0x0571d477,
 410                           0x00d0d05d, 0x3f501829, 0x0531e073,
 411                           0x0110e462, 0x3f500825, 0x04e1e471,
 412                           0x01510065, 0x3f40001f, 0x04a1f06d },
 413         },
 414         { 0x4000, {
 415                           0x00007044, 0x00007044, 0x06519476,
 416                           0x00208448, 0x3fe05c3f, 0x0621a476,
 417                           0x0050984d, 0x3fc04c3a, 0x05e1b075,
 418                           0x0080ac52, 0x3fa03c35, 0x05a1b875,
 419                           0x00c0c056, 0x3f803030, 0x0561c473,
 420                           0x0100d45b, 0x3f70202b, 0x0521d46f,
 421                           0x0140e860, 0x3f601427, 0x04d1d46e,
 422                           0x01810064, 0x3f500822, 0x0491dc6b },
 423         },
 424         { 0x5000, {
 425                           0x0110a442, 0x0110a442, 0x0551545e,
 426                           0x0140b045, 0x00e0983f, 0x0531585f,
 427                           0x0160c047, 0x00c08c3c, 0x0511645e,
 428                           0x0190cc4a, 0x00908039, 0x04f1685f,
 429                           0x01c0dc4c, 0x00707436, 0x04d1705e,
 430                           0x0200e850, 0x00506833, 0x04b1785b,
 431                           0x0230f453, 0x00305c30, 0x0491805a,
 432                           0x02710056, 0x0010542d, 0x04718059 },
 433         },
 434         { 0x6000, {
 435                           0x01c0bc40, 0x01c0bc40, 0x04c13052,
 436                           0x01e0c841, 0x01a0b43d, 0x04c13851,
 437                           0x0210cc44, 0x0180a83c, 0x04a13453,
 438                           0x0230d845, 0x0160a03a, 0x04913c52,
 439                           0x0260e047, 0x01409838, 0x04714052,
 440                           0x0280ec49, 0x01208c37, 0x04514c50,
 441                           0x02b0f44b, 0x01008435, 0x04414c50,
 442                           0x02d1004c, 0x00e07c33, 0x0431544f },
 443         },
 444         { 0x7000, {
 445                           0x0230c83e, 0x0230c83e, 0x04711c4c,
 446                           0x0250d03f, 0x0210c43c, 0x0471204b,
 447                           0x0270d840, 0x0200b83c, 0x0451244b,
 448                           0x0290dc42, 0x01e0b43a, 0x0441244c,
 449                           0x02b0e443, 0x01c0b038, 0x0441284b,
 450                           0x02d0ec44, 0x01b0a438, 0x0421304a,
 451                           0x02f0f445, 0x0190a036, 0x04213449,
 452                           0x0310f847, 0x01709c34, 0x04213848 },
 453         },
 454         { 0x8000, {
 455                           0x0280d03d, 0x0280d03d, 0x04310c48,
 456                           0x02a0d43e, 0x0270c83c, 0x04311047,
 457                           0x02b0dc3e, 0x0250c83a, 0x04311447,
 458                           0x02d0e040, 0x0240c03a, 0x04211446,
 459                           0x02e0e840, 0x0220bc39, 0x04111847,
 460                           0x0300e842, 0x0210b438, 0x04012445,
 461                           0x0310f043, 0x0200b037, 0x04012045,
 462                           0x0330f444, 0x01e0ac36, 0x03f12445 },
 463         },
 464         { 0xefff, {
 465                           0x0340dc3a, 0x0340dc3a, 0x03b0ec40,
 466                           0x0340e03a, 0x0330e039, 0x03c0f03e,
 467                           0x0350e03b, 0x0330dc39, 0x03c0ec3e,
 468                           0x0350e43a, 0x0320dc38, 0x03c0f43e,
 469                           0x0360e43b, 0x0320d839, 0x03b0f03e,
 470                           0x0360e83b, 0x0310d838, 0x03c0fc3b,
 471                           0x0370e83b, 0x0310d439, 0x03a0f83d,
 472                           0x0370e83c, 0x0300d438, 0x03b0fc3c },
 473         }
 474 };
 475
 476 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs)
 477 {
 478         int i;
 479         const struct vin_coeff *p_prev_set = NULL;
 480         const struct vin_coeff *p_set = NULL;
 481
 482         /* Look for suitable coefficient values */
 483         for (i = 0; i < ARRAY_SIZE(vin_coeff_set); i++) {
 484                 p_prev_set = p_set;
 485                 p_set = &vin_coeff_set[i];
 486
 487                 if (xs < p_set->xs_value)
 488                         break;
 489         }
 490
 491         /* Use previous value if its XS value is closer */
 492         if (p_prev_set &&
 493             xs - p_prev_set->xs_value < p_set->xs_value - xs)
 494                 p_set = p_prev_set;
 495
 496         /* Set coefficient registers */
 497         rvin_write(vin, p_set->coeff_set[0], VNC1A_REG);
 498         rvin_write(vin, p_set->coeff_set[1], VNC1B_REG);
 499         rvin_write(vin, p_set->coeff_set[2], VNC1C_REG);
 500
 501         rvin_write(vin, p_set->coeff_set[3], VNC2A_REG);
 502         rvin_write(vin, p_set->coeff_set[4], VNC2B_REG);
 503         rvin_write(vin, p_set->coeff_set[5], VNC2C_REG);
 504
 505         rvin_write(vin, p_set->coeff_set[6], VNC3A_REG);
 506         rvin_write(vin, p_set->coeff_set[7], VNC3B_REG);
 507         rvin_write(vin, p_set->coeff_set[8], VNC3C_REG);
 508
 509         rvin_write(vin, p_set->coeff_set[9], VNC4A_REG);
 510         rvin_write(vin, p_set->coeff_set[10], VNC4B_REG);
 511         rvin_write(vin, p_set->coeff_set[11], VNC4C_REG);
 512
 513         rvin_write(vin, p_set->coeff_set[12], VNC5A_REG);
 514         rvin_write(vin, p_set->coeff_set[13], VNC5B_REG);
 515         rvin_write(vin, p_set->coeff_set[14], VNC5C_REG);
 516
 517         rvin_write(vin, p_set->coeff_set[15], VNC6A_REG);
 518         rvin_write(vin, p_set->coeff_set[16], VNC6B_REG);
 519         rvin_write(vin, p_set->coeff_set[17], VNC6C_REG);
 520
 521         rvin_write(vin, p_set->coeff_set[18], VNC7A_REG);
 522         rvin_write(vin, p_set->coeff_set[19], VNC7B_REG);
 523         rvin_write(vin, p_set->coeff_set[20], VNC7C_REG);
 524
 525         rvin_write(vin, p_set->coeff_set[21], VNC8A_REG);
 526         rvin_write(vin, p_set->coeff_set[22], VNC8B_REG);
 527         rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);
 528 }
 529
 530 static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin)
 531 {
 532         u32 xs, ys;
 533
 534         /* Set scaling coefficient */
 535         ys = 0;
 536         if (vin->crop.height != vin->compose.height)
 537                 ys = (4096 * vin->crop.height) / vin->compose.height;
 538         rvin_write(vin, ys, VNYS_REG);
 539
 540         xs = 0;
 541         if (vin->crop.width != vin->compose.width)
 542                 xs = (4096 * vin->crop.width) / vin->compose.width;
 543
 544         /* Horizontal upscaling is up to double size */
 545         if (xs > 0 && xs < 2048)
 546                 xs = 2048;
 547
 548         rvin_write(vin, xs, VNXS_REG);
 549
 550         /* Horizontal upscaling is done out by scaling down from double size */
 551         if (xs < 4096)
 552                 xs *= 2;
 553
 554         rvin_set_coeff(vin, xs);
 555
 556         /* Set Start/End Pixel/Line Post-Clip */
 557         rvin_write(vin, 0, VNSPPOC_REG);
 558         rvin_write(vin, 0, VNSLPOC_REG);
 559         rvin_write(vin, vin->format.width - 1, VNEPPOC_REG);
 560         switch (vin->format.field) {
 561         case V4L2_FIELD_INTERLACED:
 562         case V4L2_FIELD_INTERLACED_TB:
 563         case V4L2_FIELD_INTERLACED_BT:
 564                 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG);
 565                 break;
 566         default:
 567                 rvin_write(vin, vin->format.height - 1, VNELPOC_REG);
 568                 break;
 569         }
 570
 571         vin_dbg(vin,
 572                 "Pre-Clip: %ux%u@%u:%u YS: %d XS: %d Post-Clip: %ux%u@%u:%u\n",
 573                 vin->crop.width, vin->crop.height, vin->crop.left,
 574                 vin->crop.top, ys, xs, vin->format.width, vin->format.height,
 575                 0, 0);
 576 }
 577
 578 void rvin_crop_scale_comp(struct rvin_dev *vin)
 579 {
 580         /* Set Start/End Pixel/Line Pre-Clip */
 581         rvin_write(vin, vin->crop.left, VNSPPRC_REG);
 582         rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
 583
 584         switch (vin->format.field) {
 585         case V4L2_FIELD_INTERLACED:
 586         case V4L2_FIELD_INTERLACED_TB:
 587         case V4L2_FIELD_INTERLACED_BT:
 588                 rvin_write(vin, vin->crop.top / 2, VNSLPRC_REG);
 589                 rvin_write(vin, (vin->crop.top + vin->crop.height) / 2 - 1,
 590                            VNELPRC_REG);
 591                 break;
 592         default:
 593                 rvin_write(vin, vin->crop.top, VNSLPRC_REG);
 594                 rvin_write(vin, vin->crop.top + vin->crop.height - 1,
 595                            VNELPRC_REG);
 596                 break;
 597         }
 598
 599         /* TODO: Add support for the UDS scaler. */
 600         if (vin->info->model != RCAR_GEN3)
 601                 rvin_crop_scale_comp_gen2(vin);
 602
 603         if (vin->format.pixelformat == V4L2_PIX_FMT_NV16)
 604                 rvin_write(vin, ALIGN(vin->format.width, 0x20), VNIS_REG);
 605         else
 606                 rvin_write(vin, ALIGN(vin->format.width, 0x10), VNIS_REG);
 607 }
 608
 609 /* -----------------------------------------------------------------------------
 610  * Hardware setup
 611  */
 612
 613 static int rvin_setup(struct rvin_dev *vin)
 614 {
 615         u32 vnmc, dmr, dmr2, interrupts;
 616         bool progressive = false, output_is_yuv = false, input_is_yuv = false;
 617
 618         switch (vin->format.field) {
 619         case V4L2_FIELD_TOP:
 620                 vnmc = VNMC_IM_ODD;
 621                 break;
 622         case V4L2_FIELD_BOTTOM:
 623                 vnmc = VNMC_IM_EVEN;
 624                 break;
 625         case V4L2_FIELD_INTERLACED:
 626                 /* Default to TB */
 627                 vnmc = VNMC_IM_FULL;
 628                 /* Use BT if video standard can be read and is 60 Hz format */
 629                 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60)
 630                         vnmc = VNMC_IM_FULL | VNMC_FOC;
 631                 break;
 632         case V4L2_FIELD_INTERLACED_TB:
 633                 vnmc = VNMC_IM_FULL;
 634                 break;
 635         case V4L2_FIELD_INTERLACED_BT:
 636                 vnmc = VNMC_IM_FULL | VNMC_FOC;
 637                 break;
 638         case V4L2_FIELD_NONE:
 639                 vnmc = VNMC_IM_ODD_EVEN;
 640                 progressive = true;
 641                 break;
 642         default:
 643                 vnmc = VNMC_IM_ODD;
 644                 break;
 645         }
 646
 647         /*
 648          * Input interface
 649          */
 650         switch (vin->mbus_code) {
 651         case MEDIA_BUS_FMT_YUYV8_1X16:
 652                 /* BT.601/BT.1358 16bit YCbCr422 */
 653                 vnmc |= VNMC_INF_YUV16;
 654                 input_is_yuv = true;
 655                 break;
 656         case MEDIA_BUS_FMT_UYVY8_1X16:
 657                 vnmc |= VNMC_INF_YUV16 | VNMC_YCAL;
 658                 input_is_yuv = true;
 659                 break;
 660         case MEDIA_BUS_FMT_UYVY8_2X8:
 661                 /* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
 662                 if (!vin->is_csi &&
 663                     vin->parallel->mbus_type == V4L2_MBUS_BT656)
 664                         vnmc |= VNMC_INF_YUV8_BT656;
 665                 else
 666                         vnmc |= VNMC_INF_YUV8_BT601;
 667
 668                 input_is_yuv = true;
 669                 break;
 670         case MEDIA_BUS_FMT_RGB888_1X24:
 671                 vnmc |= VNMC_INF_RGB888;
 672                 break;
 673         case MEDIA_BUS_FMT_UYVY10_2X10:
 674                 /* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
 675                 if (!vin->is_csi &&
 676                     vin->parallel->mbus_type == V4L2_MBUS_BT656)
 677                         vnmc |= VNMC_INF_YUV10_BT656;
 678                 else
 679                         vnmc |= VNMC_INF_YUV10_BT601;
 680
 681                 input_is_yuv = true;
 682                 break;
 683         default:
 684                 break;
 685         }
 686
 687         /* Enable VSYNC Field Toggle mode after one VSYNC input */
 688         if (vin->info->model == RCAR_GEN3)
 689                 dmr2 = VNDMR2_FTEV;
 690         else
 691                 dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
 692
 693         if (!vin->is_csi) {
 694                 /* Hsync Signal Polarity Select */
 695                 if (!(vin->parallel->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
 696                         dmr2 |= VNDMR2_HPS;
 697
 698                 /* Vsync Signal Polarity Select */
 699                 if (!(vin->parallel->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
 700                         dmr2 |= VNDMR2_VPS;
 701
 702                 /* Data Enable Polarity Select */
 703                 if (vin->parallel->mbus_flags & V4L2_MBUS_DATA_ENABLE_LOW)
 704                         dmr2 |= VNDMR2_CES;
 705         }
 706
 707         /*
 708          * Output format
 709          */
 710         switch (vin->format.pixelformat) {
 711         case V4L2_PIX_FMT_NV16:
 712                 rvin_write(vin,
 713                            ALIGN(vin->format.width * vin->format.height, 0x80),
 714                            VNUVAOF_REG);
 715                 dmr = VNDMR_DTMD_YCSEP;
 716                 output_is_yuv = true;
 717                 break;
 718         case V4L2_PIX_FMT_YUYV:
 719                 dmr = VNDMR_BPSM;
 720                 output_is_yuv = true;
 721                 break;
 722         case V4L2_PIX_FMT_UYVY:
 723                 dmr = 0;
 724                 output_is_yuv = true;
 725                 break;
 726         case V4L2_PIX_FMT_XRGB555:
 727                 dmr = VNDMR_DTMD_ARGB;
 728                 break;
 729         case V4L2_PIX_FMT_RGB565:
 730                 dmr = 0;
 731                 break;
 732         case V4L2_PIX_FMT_XBGR32:
 733                 /* Note: not supported on M1 */
 734                 dmr = VNDMR_EXRGB;
 735                 break;
 736         case V4L2_PIX_FMT_ARGB555:
 737                 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB;
 738                 break;
 739         case V4L2_PIX_FMT_ABGR32:
 740                 dmr = VNDMR_A8BIT(vin->alpha) | VNDMR_EXRGB | VNDMR_DTMD_ARGB;
 741                 break;
 742         default:
 743                 vin_err(vin, "Invalid pixelformat (0x%x)\n",
 744                         vin->format.pixelformat);
 745                 return -EINVAL;
 746         }
 747
 748         /* Always update on field change */
 749         vnmc |= VNMC_VUP;
 750
 751         /* If input and output use the same colorspace, use bypass mode */
 752         if (input_is_yuv == output_is_yuv)
 753                 vnmc |= VNMC_BPS;
 754
 755         if (vin->info->model == RCAR_GEN3) {
 756                 /* Select between CSI-2 and parallel input */
 757                 if (vin->is_csi)
 758                         vnmc &= ~VNMC_DPINE;
 759                 else
 760                         vnmc |= VNMC_DPINE;
 761         }
 762
 763         /* Progressive or interlaced mode */
 764         interrupts = progressive ? VNIE_FIE : VNIE_EFE;
 765
 766         /* Ack interrupts */
 767         rvin_write(vin, interrupts, VNINTS_REG);
 768         /* Enable interrupts */
 769         rvin_write(vin, interrupts, VNIE_REG);
 770         /* Start capturing */
 771         rvin_write(vin, dmr, VNDMR_REG);
 772         rvin_write(vin, dmr2, VNDMR2_REG);
 773
 774         /* Enable module */
 775         rvin_write(vin, vnmc | VNMC_ME, VNMC_REG);
 776
 777         return 0;
 778 }
 779
 780 static void rvin_disable_interrupts(struct rvin_dev *vin)
 781 {
 782         rvin_write(vin, 0, VNIE_REG);
 783 }
 784
 785 static u32 rvin_get_interrupt_status(struct rvin_dev *vin)
 786 {
 787         return rvin_read(vin, VNINTS_REG);
 788 }
 789
 790 static void rvin_ack_interrupt(struct rvin_dev *vin)
 791 {
 792         rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG);
 793 }
 794
 795 static bool rvin_capture_active(struct rvin_dev *vin)
 796 {
 797         return rvin_read(vin, VNMS_REG) & VNMS_CA;
 798 }
 799
 800 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)
 801 {
 802         const struct rvin_video_format *fmt;
 803         int offsetx, offsety;
 804         dma_addr_t offset;
 805
 806         fmt = rvin_format_from_pixel(vin, vin->format.pixelformat);
 807
 808         /*
 809          * There is no HW support for composition do the beast we can
 810          * by modifying the buffer offset
 811          */
 812         offsetx = vin->compose.left * fmt->bpp;
 813         offsety = vin->compose.top * vin->format.bytesperline;
 814         offset = addr + offsetx + offsety;
 815
 816         /*
 817          * The address needs to be 128 bytes aligned. Driver should never accept
 818          * settings that do not satisfy this in the first place...
 819          */
 820         if (WARN_ON((offsetx | offsety | offset) & HW_BUFFER_MASK))
 821                 return;
 822
 823         rvin_write(vin, offset, VNMB_REG(slot));
 824 }
 825
 826 /*
 827  * Moves a buffer from the queue to the HW slot. If no buffer is
 828  * available use the scratch buffer. The scratch buffer is never
 829  * returned to userspace, its only function is to enable the capture
 830  * loop to keep running.
 831  */
 832 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
 833 {
 834         struct rvin_buffer *buf;
 835         struct vb2_v4l2_buffer *vbuf;
 836         dma_addr_t phys_addr;
 837
 838         /* A already populated slot shall never be overwritten. */
 839         if (WARN_ON(vin->queue_buf[slot] != NULL))
 840                 return;
 841
 842         vin_dbg(vin, "Filling HW slot: %d\n", slot);
 843
 844         if (list_empty(&vin->buf_list)) {
 845                 vin->queue_buf[slot] = NULL;
 846                 phys_addr = vin->scratch_phys;
 847         } else {
 848                 /* Keep track of buffer we give to HW */
 849                 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);
 850                 vbuf = &buf->vb;
 851                 list_del_init(to_buf_list(vbuf));
 852                 vin->queue_buf[slot] = vbuf;
 853
 854                 /* Setup DMA */
 855                 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
 856         }
 857
 858         rvin_set_slot_addr(vin, slot, phys_addr);
 859 }
 860
 861 static int rvin_capture_start(struct rvin_dev *vin)
 862 {
 863         int slot, ret;
 864
 865         for (slot = 0; slot < HW_BUFFER_NUM; slot++)
 866                 rvin_fill_hw_slot(vin, slot);
 867
 868         rvin_crop_scale_comp(vin);
 869
 870         ret = rvin_setup(vin);
 871         if (ret)
 872                 return ret;
 873
 874         vin_dbg(vin, "Starting to capture\n");
 875
 876         /* Continuous Frame Capture Mode */
 877         rvin_write(vin, VNFC_C_FRAME, VNFC_REG);
 878
 879         vin->state = STARTING;
 880
 881         return 0;
 882 }
 883
 884 static void rvin_capture_stop(struct rvin_dev *vin)
 885 {
 886         /* Set continuous & single transfer off */
 887         rvin_write(vin, 0, VNFC_REG);
 888
 889         /* Disable module */
 890         rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG);
 891 }
 892
 893 /* -----------------------------------------------------------------------------
 894  * DMA Functions
 895  */
 896
 897 #define RVIN_TIMEOUT_MS 100
 898 #define RVIN_RETRIES 10
 899
 900 static irqreturn_t rvin_irq(int irq, void *data)
 901 {
 902         struct rvin_dev *vin = data;
 903         u32 int_status, vnms;
 904         int slot;
 905         unsigned int handled = 0;
 906         unsigned long flags;
 907
 908         spin_lock_irqsave(&vin->qlock, flags);
 909
 910         int_status = rvin_get_interrupt_status(vin);
 911         if (!int_status)
 912                 goto done;
 913
 914         rvin_ack_interrupt(vin);
 915         handled = 1;
 916
 917         /* Nothing to do if capture status is 'STOPPED' */
 918         if (vin->state == STOPPED) {
 919                 vin_dbg(vin, "IRQ while state stopped\n");
 920                 goto done;
 921         }
 922
 923         /* Nothing to do if capture status is 'STOPPING' */
 924         if (vin->state == STOPPING) {
 925                 vin_dbg(vin, "IRQ while state stopping\n");
 926                 goto done;
 927         }
 928
 929         /* Prepare for capture and update state */
 930         vnms = rvin_read(vin, VNMS_REG);
 931         slot = (vnms & VNMS_FBS_MASK) >> VNMS_FBS_SHIFT;
 932
 933         /*
 934          * To hand buffers back in a known order to userspace start
 935          * to capture first from slot 0.
 936          */
 937         if (vin->state == STARTING) {
 938                 if (slot != 0) {
 939                         vin_dbg(vin, "Starting sync slot: %d\n", slot);
 940                         goto done;
 941                 }
 942
 943                 vin_dbg(vin, "Capture start synced!\n");
 944                 vin->state = RUNNING;
 945         }
 946
 947         /* Capture frame */
 948         if (vin->queue_buf[slot]) {
 949                 vin->queue_buf[slot]->field = vin->format.field;
 950                 vin->queue_buf[slot]->sequence = vin->sequence;
 951                 vin->queue_buf[slot]->vb2_buf.timestamp = ktime_get_ns();
 952                 vb2_buffer_done(&vin->queue_buf[slot]->vb2_buf,
 953                                 VB2_BUF_STATE_DONE);
 954                 vin->queue_buf[slot] = NULL;
 955         } else {
 956                 /* Scratch buffer was used, dropping frame. */
 957                 vin_dbg(vin, "Dropping frame %u\n", vin->sequence);
 958         }
 959
 960         vin->sequence++;
 961
 962         /* Prepare for next frame */
 963         rvin_fill_hw_slot(vin, slot);
 964 done:
 965         spin_unlock_irqrestore(&vin->qlock, flags);
 966
 967         return IRQ_RETVAL(handled);
 968 }
 969
 970 /* Need to hold qlock before calling */
 971 static void return_all_buffers(struct rvin_dev *vin,
 972                                enum vb2_buffer_state state)
 973 {
 974         struct rvin_buffer *buf, *node;
 975         int i;
 976
 977         for (i = 0; i < HW_BUFFER_NUM; i++) {
 978                 if (vin->queue_buf[i]) {
 979                         vb2_buffer_done(&vin->queue_buf[i]->vb2_buf,
 980                                         state);
 981                         vin->queue_buf[i] = NULL;
 982                 }
 983         }
 984
 985         list_for_each_entry_safe(buf, node, &vin->buf_list, list) {
 986                 vb2_buffer_done(&buf->vb.vb2_buf, state);
 987                 list_del(&buf->list);
 988         }
 989 }
 990
 991 static int rvin_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
 992                             unsigned int *nplanes, unsigned int sizes[],
 993                             struct device *alloc_devs[])
 994
 995 {
 996         struct rvin_dev *vin = vb2_get_drv_priv(vq);
 997
 998         /* Make sure the image size is large enough. */
 999         if (*nplanes)
1000                 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0;
1001
1002         *nplanes = 1;
1003         sizes[0] = vin->format.sizeimage;
1004
1005         return 0;
1006 };
1007
1008 static int rvin_buffer_prepare(struct vb2_buffer *vb)
1009 {
1010         struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);
1011         unsigned long size = vin->format.sizeimage;
1012
1013         if (vb2_plane_size(vb, 0) < size) {
1014                 vin_err(vin, "buffer too small (%lu < %lu)\n",
1015                         vb2_plane_size(vb, 0), size);
1016                 return -EINVAL;
1017         }
1018
1019         vb2_set_plane_payload(vb, 0, size);
1020
1021         return 0;
1022 }
1023
1024 static void rvin_buffer_queue(struct vb2_buffer *vb)
1025 {
1026         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1027         struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);
1028         unsigned long flags;
1029
1030         spin_lock_irqsave(&vin->qlock, flags);
1031
1032         list_add_tail(to_buf_list(vbuf), &vin->buf_list);
1033
1034         spin_unlock_irqrestore(&vin->qlock, flags);
1035 }
1036
1037 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd,
1038                                    struct media_pad *pad)
1039 {
1040         struct v4l2_subdev_format fmt = {
1041                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1042         };
1043
1044         fmt.pad = pad->index;
1045         if (v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt))
1046                 return -EPIPE;
1047
1048         switch (fmt.format.code) {
1049         case MEDIA_BUS_FMT_YUYV8_1X16:
1050         case MEDIA_BUS_FMT_UYVY8_1X16:
1051         case MEDIA_BUS_FMT_UYVY8_2X8:
1052         case MEDIA_BUS_FMT_UYVY10_2X10:
1053         case MEDIA_BUS_FMT_RGB888_1X24:
1054                 vin->mbus_code = fmt.format.code;
1055                 break;
1056         default:
1057                 return -EPIPE;
1058         }
1059
1060         switch (fmt.format.field) {
1061         case V4L2_FIELD_TOP:
1062         case V4L2_FIELD_BOTTOM:
1063         case V4L2_FIELD_NONE:
1064         case V4L2_FIELD_INTERLACED_TB:
1065         case V4L2_FIELD_INTERLACED_BT:
1066         case V4L2_FIELD_INTERLACED:
1067         case V4L2_FIELD_SEQ_TB:
1068         case V4L2_FIELD_SEQ_BT:
1069                 /* Supported natively */
1070                 break;
1071         case V4L2_FIELD_ALTERNATE:
1072                 switch (vin->format.field) {
1073                 case V4L2_FIELD_TOP:
1074                 case V4L2_FIELD_BOTTOM:
1075                 case V4L2_FIELD_NONE:
1076                         break;
1077                 case V4L2_FIELD_INTERLACED_TB:
1078                 case V4L2_FIELD_INTERLACED_BT:
1079                 case V4L2_FIELD_INTERLACED:
1080                 case V4L2_FIELD_SEQ_TB:
1081                 case V4L2_FIELD_SEQ_BT:
1082                         /* Use VIN hardware to combine the two fields */
1083                         fmt.format.height *= 2;
1084                         break;
1085                 default:
1086                         return -EPIPE;
1087                 }
1088                 break;
1089         default:
1090                 return -EPIPE;
1091         }
1092
1093         if (fmt.format.width != vin->format.width ||
1094             fmt.format.height != vin->format.height ||
1095             fmt.format.code != vin->mbus_code)
1096                 return -EPIPE;
1097
1098         return 0;
1099 }
1100
1101 static int rvin_set_stream(struct rvin_dev *vin, int on)
1102 {
1103         struct media_pipeline *pipe;
1104         struct media_device *mdev;
1105         struct v4l2_subdev *sd;
1106         struct media_pad *pad;
1107         int ret;
1108
1109         /* No media controller used, simply pass operation to subdevice. */
1110         if (!vin->info->use_mc) {
1111                 ret = v4l2_subdev_call(vin->parallel->subdev, video, s_stream,
1112                                        on);
1113
1114                 return ret == -ENOIOCTLCMD ? 0 : ret;
1115         }
1116
1117         pad = media_entity_remote_pad(&vin->pad);
1118         if (!pad)
1119                 return -EPIPE;
1120
1121         sd = media_entity_to_v4l2_subdev(pad->entity);
1122
1123         if (!on) {
1124                 media_pipeline_stop(&vin->vdev.entity);
1125                 return v4l2_subdev_call(sd, video, s_stream, 0);
1126         }
1127
1128         ret = rvin_mc_validate_format(vin, sd, pad);
1129         if (ret)
1130                 return ret;
1131
1132         /*
1133          * The graph lock needs to be taken to protect concurrent
1134          * starts of multiple VIN instances as they might share
1135          * a common subdevice down the line and then should use
1136          * the same pipe.
1137          */
1138         mdev = vin->vdev.entity.graph_obj.mdev;
1139         mutex_lock(&mdev->graph_mutex);
1140         pipe = sd->entity.pipe ? sd->entity.pipe : &vin->vdev.pipe;
1141         ret = __media_pipeline_start(&vin->vdev.entity, pipe);
1142         mutex_unlock(&mdev->graph_mutex);
1143         if (ret)
1144                 return ret;
1145
1146         ret = v4l2_subdev_call(sd, video, s_stream, 1);
1147         if (ret == -ENOIOCTLCMD)
1148                 ret = 0;
1149         if (ret)
1150                 media_pipeline_stop(&vin->vdev.entity);
1151
1152         return ret;
1153 }
1154
1155 static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
1156 {
1157         struct rvin_dev *vin = vb2_get_drv_priv(vq);
1158         unsigned long flags;
1159         int ret;
1160
1161         /* Allocate scratch buffer. */
1162         vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,
1163                                           &vin->scratch_phys, GFP_KERNEL);
1164         if (!vin->scratch) {
1165                 spin_lock_irqsave(&vin->qlock, flags);
1166                 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1167                 spin_unlock_irqrestore(&vin->qlock, flags);
1168                 vin_err(vin, "Failed to allocate scratch buffer\n");
1169                 return -ENOMEM;
1170         }
1171
1172         ret = rvin_set_stream(vin, 1);
1173         if (ret) {
1174                 spin_lock_irqsave(&vin->qlock, flags);
1175                 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1176                 spin_unlock_irqrestore(&vin->qlock, flags);
1177                 goto out;
1178         }
1179
1180         spin_lock_irqsave(&vin->qlock, flags);
1181
1182         vin->sequence = 0;
1183
1184         ret = rvin_capture_start(vin);
1185         if (ret) {
1186                 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1187                 rvin_set_stream(vin, 0);
1188         }
1189
1190         spin_unlock_irqrestore(&vin->qlock, flags);
1191 out:
1192         if (ret)
1193                 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
1194                                   vin->scratch_phys);
1195
1196         return ret;
1197 }
1198
1199 static void rvin_stop_streaming(struct vb2_queue *vq)
1200 {
1201         struct rvin_dev *vin = vb2_get_drv_priv(vq);
1202         unsigned long flags;
1203         int retries = 0;
1204
1205         spin_lock_irqsave(&vin->qlock, flags);
1206
1207         vin->state = STOPPING;
1208
1209         /* Wait for streaming to stop */
1210         while (retries++ < RVIN_RETRIES) {
1211
1212                 rvin_capture_stop(vin);
1213
1214                 /* Check if HW is stopped */
1215                 if (!rvin_capture_active(vin)) {
1216                         vin->state = STOPPED;
1217                         break;
1218                 }
1219
1220                 spin_unlock_irqrestore(&vin->qlock, flags);
1221                 msleep(RVIN_TIMEOUT_MS);
1222                 spin_lock_irqsave(&vin->qlock, flags);
1223         }
1224
1225         if (vin->state != STOPPED) {
1226                 /*
1227                  * If this happens something have gone horribly wrong.
1228                  * Set state to stopped to prevent the interrupt handler
1229                  * to make things worse...
1230                  */
1231                 vin_err(vin, "Failed stop HW, something is seriously broken\n");
1232                 vin->state = STOPPED;
1233         }
1234
1235         /* Release all active buffers */
1236         return_all_buffers(vin, VB2_BUF_STATE_ERROR);
1237
1238         spin_unlock_irqrestore(&vin->qlock, flags);
1239
1240         rvin_set_stream(vin, 0);
1241
1242         /* disable interrupts */
1243         rvin_disable_interrupts(vin);
1244
1245         /* Free scratch buffer. */
1246         dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
1247                           vin->scratch_phys);
1248 }
1249
1250 static const struct vb2_ops rvin_qops = {
1251         .queue_setup            = rvin_queue_setup,
1252         .buf_prepare            = rvin_buffer_prepare,
1253         .buf_queue              = rvin_buffer_queue,
1254         .start_streaming        = rvin_start_streaming,
1255         .stop_streaming         = rvin_stop_streaming,
1256         .wait_prepare           = vb2_ops_wait_prepare,
1257         .wait_finish            = vb2_ops_wait_finish,
1258 };
1259
1260 void rvin_dma_unregister(struct rvin_dev *vin)
1261 {
1262         mutex_destroy(&vin->lock);
1263
1264         v4l2_device_unregister(&vin->v4l2_dev);
1265 }
1266
1267 int rvin_dma_register(struct rvin_dev *vin, int irq)
1268 {
1269         struct vb2_queue *q = &vin->queue;
1270         int i, ret;
1271
1272         /* Initialize the top-level structure */
1273         ret = v4l2_device_register(vin->dev, &vin->v4l2_dev);
1274         if (ret)
1275                 return ret;
1276
1277         mutex_init(&vin->lock);
1278         INIT_LIST_HEAD(&vin->buf_list);
1279
1280         spin_lock_init(&vin->qlock);
1281
1282         vin->state = STOPPED;
1283
1284         for (i = 0; i < HW_BUFFER_NUM; i++)
1285                 vin->queue_buf[i] = NULL;
1286
1287         /* buffer queue */
1288         q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1289         q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
1290         q->lock = &vin->lock;
1291         q->drv_priv = vin;
1292         q->buf_struct_size = sizeof(struct rvin_buffer);
1293         q->ops = &rvin_qops;
1294         q->mem_ops = &vb2_dma_contig_memops;
1295         q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1296         q->min_buffers_needed = 4;
1297         q->dev = vin->dev;
1298
1299         ret = vb2_queue_init(q);
1300         if (ret < 0) {
1301                 vin_err(vin, "failed to initialize VB2 queue\n");
1302                 goto error;
1303         }
1304
1305         /* irq */
1306         ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED,
1307                                KBUILD_MODNAME, vin);
1308         if (ret) {
1309                 vin_err(vin, "failed to request irq\n");
1310                 goto error;
1311         }
1312
1313         return 0;
1314 error:
1315         rvin_dma_unregister(vin);
1316
1317         return ret;
1318 }
1319
1320 /* -----------------------------------------------------------------------------
1321  * Gen3 CHSEL manipulation
1322  */
1323
1324 /*
1325  * There is no need to have locking around changing the routing
1326  * as it's only possible to do so when no VIN in the group is
1327  * streaming so nothing can race with the VNMC register.
1328  */
1329 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
1330 {
1331         u32 ifmd, vnmc;
1332         int ret;
1333
1334         ret = pm_runtime_get_sync(vin->dev);
1335         if (ret < 0)
1336                 return ret;
1337
1338         /* Make register writes take effect immediately. */
1339         vnmc = rvin_read(vin, VNMC_REG);
1340         rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG);
1341
1342         ifmd = VNCSI_IFMD_DES1 | VNCSI_IFMD_DES0 | VNCSI_IFMD_CSI_CHSEL(chsel);
1343
1344         rvin_write(vin, ifmd, VNCSI_IFMD_REG);
1345
1346         vin_dbg(vin, "Set IFMD 0x%x\n", ifmd);
1347
1348         /* Restore VNMC. */
1349         rvin_write(vin, vnmc, VNMC_REG);
1350
1351         pm_runtime_put(vin->dev);
1352
1353         return 0;
1354 }
1355
1356 void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha)
1357 {
1358         unsigned long flags;
1359         u32 dmr;
1360
1361         spin_lock_irqsave(&vin->qlock, flags);
1362
1363         vin->alpha = alpha;
1364
1365         if (vin->state == STOPPED)
1366                 goto out;
1367
1368         switch (vin->format.pixelformat) {
1369         case V4L2_PIX_FMT_ARGB555:
1370                 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_ABIT;
1371                 if (vin->alpha)
1372                         dmr |= VNDMR_ABIT;
1373                 break;
1374         case V4L2_PIX_FMT_ABGR32:
1375                 dmr = rvin_read(vin, VNDMR_REG) & ~VNDMR_A8BIT_MASK;
1376                 dmr |= VNDMR_A8BIT(vin->alpha);
1377                 break;
1378         default:
1379                 goto out;
1380         }
1381
1382         rvin_write(vin, dmr,  VNDMR_REG);
1383 out:
1384         spin_unlock_irqrestore(&vin->qlock, flags);
1385 }