drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * c8sectpfe-core.c - C8SECTPFE STi DVB driver
   4  *
   5  * Copyright (c) STMicroelectronics 2015
   6  *
   7  *   Author:Peter Bennett <peter.bennett@st.com>
   8  *          Peter Griffin <peter.griffin@linaro.org>
   9  *
  10  */
  11 #include <linux/atomic.h>
  12 #include <linux/clk.h>
  13 #include <linux/completion.h>
  14 #include <linux/delay.h>
  15 #include <linux/device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dvb/dmx.h>
  18 #include <linux/dvb/frontend.h>
  19 #include <linux/errno.h>
  20 #include <linux/firmware.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/module.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/usb.h>
  29 #include <linux/slab.h>
  30 #include <linux/time.h>
  31 #include <linux/version.h>
  32 #include <linux/wait.h>
  33 #include <linux/pinctrl/pinctrl.h>
  34
  35 #include "c8sectpfe-core.h"
  36 #include "c8sectpfe-common.h"
  37 #include "c8sectpfe-debugfs.h"
  38 #include <media/dmxdev.h>
  39 #include <media/dvb_demux.h>
  40 #include <media/dvb_frontend.h>
  41 #include <media/dvb_net.h>
  42
  43 #define FIRMWARE_MEMDMA "pti_memdma_h407.elf"
  44 MODULE_FIRMWARE(FIRMWARE_MEMDMA);
  45
  46 #define PID_TABLE_SIZE 1024
  47 #define POLL_MSECS 50
  48
  49 static int load_c8sectpfe_fw(struct c8sectpfei *fei);
  50
  51 #define TS_PKT_SIZE 188
  52 #define HEADER_SIZE (4)
  53 #define PACKET_SIZE (TS_PKT_SIZE+HEADER_SIZE)
  54
  55 #define FEI_ALIGNMENT (32)
  56 /* hw requires minimum of 8*PACKET_SIZE and padded to 8byte boundary */
  57 #define FEI_BUFFER_SIZE (8*PACKET_SIZE*340)
  58
  59 #define FIFO_LEN 1024
  60
  61 static void c8sectpfe_timer_interrupt(struct timer_list *t)
  62 {
  63         struct c8sectpfei *fei = from_timer(fei, t, timer);
  64         struct channel_info *channel;
  65         int chan_num;
  66
  67         /* iterate through input block channels */
  68         for (chan_num = 0; chan_num < fei->tsin_count; chan_num++) {
  69                 channel = fei->channel_data[chan_num];
  70
  71                 /* is this descriptor initialised and TP enabled */
  72                 if (channel->irec && readl(channel->irec + DMA_PRDS_TPENABLE))
  73                         tasklet_schedule(&channel->tsklet);
  74         }
  75
  76         fei->timer.expires = jiffies +  msecs_to_jiffies(POLL_MSECS);
  77         add_timer(&fei->timer);
  78 }
  79
  80 static void channel_swdemux_tsklet(unsigned long data)
  81 {
  82         struct channel_info *channel = (struct channel_info *)data;
  83         struct c8sectpfei *fei;
  84         unsigned long wp, rp;
  85         int pos, num_packets, n, size;
  86         u8 *buf;
  87
  88         if (unlikely(!channel || !channel->irec))
  89                 return;
  90
  91         fei = channel->fei;
  92
  93         wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0));
  94         rp = readl(channel->irec + DMA_PRDS_BUSRP_TP(0));
  95
  96         pos = rp - channel->back_buffer_busaddr;
  97
  98         /* has it wrapped */
  99         if (wp < rp)
 100                 wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE;
 101
 102         size = wp - rp;
 103         num_packets = size / PACKET_SIZE;
 104
 105         /* manage cache so data is visible to CPU */
 106         dma_sync_single_for_cpu(fei->dev,
 107                                 rp,
 108                                 size,
 109                                 DMA_FROM_DEVICE);
 110
 111         buf = (u8 *) channel->back_buffer_aligned;
 112
 113         dev_dbg(fei->dev,
 114                 "chan=%d channel=%p num_packets = %d, buf = %p, pos = 0x%x\n\trp=0x%lx, wp=0x%lx\n",
 115                 channel->tsin_id, channel, num_packets, buf, pos, rp, wp);
 116
 117         for (n = 0; n < num_packets; n++) {
 118                 dvb_dmx_swfilter_packets(
 119                         &fei->c8sectpfe[0]->
 120                                 demux[channel->demux_mapping].dvb_demux,
 121                         &buf[pos], 1);
 122
 123                 pos += PACKET_SIZE;
 124         }
 125
 126         /* advance the read pointer */
 127         if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE))
 128                 writel(channel->back_buffer_busaddr, channel->irec +
 129                         DMA_PRDS_BUSRP_TP(0));
 130         else
 131                 writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0));
 132 }
 133
 134 static int c8sectpfe_start_feed(struct dvb_demux_feed *dvbdmxfeed)
 135 {
 136         struct dvb_demux *demux = dvbdmxfeed->demux;
 137         struct stdemux *stdemux = (struct stdemux *)demux->priv;
 138         struct c8sectpfei *fei = stdemux->c8sectpfei;
 139         struct channel_info *channel;
 140         u32 tmp;
 141         unsigned long *bitmap;
 142         int ret;
 143
 144         switch (dvbdmxfeed->type) {
 145         case DMX_TYPE_TS:
 146                 break;
 147         case DMX_TYPE_SEC:
 148                 break;
 149         default:
 150                 dev_err(fei->dev, "%s:%d Error bailing\n"
 151                         , __func__, __LINE__);
 152                 return -EINVAL;
 153         }
 154
 155         if (dvbdmxfeed->type == DMX_TYPE_TS) {
 156                 switch (dvbdmxfeed->pes_type) {
 157                 case DMX_PES_VIDEO:
 158                 case DMX_PES_AUDIO:
 159                 case DMX_PES_TELETEXT:
 160                 case DMX_PES_PCR:
 161                 case DMX_PES_OTHER:
 162                         break;
 163                 default:
 164                         dev_err(fei->dev, "%s:%d Error bailing\n"
 165                                 , __func__, __LINE__);
 166                         return -EINVAL;
 167                 }
 168         }
 169
 170         if (!atomic_read(&fei->fw_loaded)) {
 171                 ret = load_c8sectpfe_fw(fei);
 172                 if (ret)
 173                         return ret;
 174         }
 175
 176         mutex_lock(&fei->lock);
 177
 178         channel = fei->channel_data[stdemux->tsin_index];
 179
 180         bitmap = (unsigned long *) channel->pid_buffer_aligned;
 181
 182         /* 8192 is a special PID */
 183         if (dvbdmxfeed->pid == 8192) {
 184                 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 185                 tmp &= ~C8SECTPFE_PID_ENABLE;
 186                 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 187
 188         } else {
 189                 bitmap_set(bitmap, dvbdmxfeed->pid, 1);
 190         }
 191
 192         /* manage cache so PID bitmap is visible to HW */
 193         dma_sync_single_for_device(fei->dev,
 194                                         channel->pid_buffer_busaddr,
 195                                         PID_TABLE_SIZE,
 196                                         DMA_TO_DEVICE);
 197
 198         channel->active = 1;
 199
 200         if (fei->global_feed_count == 0) {
 201                 fei->timer.expires = jiffies +
 202                         msecs_to_jiffies(msecs_to_jiffies(POLL_MSECS));
 203
 204                 add_timer(&fei->timer);
 205         }
 206
 207         if (stdemux->running_feed_count == 0) {
 208
 209                 dev_dbg(fei->dev, "Starting channel=%p\n", channel);
 210
 211                 tasklet_init(&channel->tsklet, channel_swdemux_tsklet,
 212                              (unsigned long) channel);
 213
 214                 /* Reset the internal inputblock sram pointers */
 215                 writel(channel->fifo,
 216                         fei->io + C8SECTPFE_IB_BUFF_STRT(channel->tsin_id));
 217                 writel(channel->fifo + FIFO_LEN - 1,
 218                         fei->io + C8SECTPFE_IB_BUFF_END(channel->tsin_id));
 219
 220                 writel(channel->fifo,
 221                         fei->io + C8SECTPFE_IB_READ_PNT(channel->tsin_id));
 222                 writel(channel->fifo,
 223                         fei->io + C8SECTPFE_IB_WRT_PNT(channel->tsin_id));
 224
 225
 226                 /* reset read / write memdma ptrs for this channel */
 227                 writel(channel->back_buffer_busaddr, channel->irec +
 228                         DMA_PRDS_BUSBASE_TP(0));
 229
 230                 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 231                 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
 232
 233                 writel(channel->back_buffer_busaddr, channel->irec +
 234                         DMA_PRDS_BUSWP_TP(0));
 235
 236                 /* Issue a reset and enable InputBlock */
 237                 writel(C8SECTPFE_SYS_ENABLE | C8SECTPFE_SYS_RESET
 238                         , fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
 239
 240                 /* and enable the tp */
 241                 writel(0x1, channel->irec + DMA_PRDS_TPENABLE);
 242
 243                 dev_dbg(fei->dev, "%s:%d Starting DMA feed on stdemux=%p\n"
 244                         , __func__, __LINE__, stdemux);
 245         }
 246
 247         stdemux->running_feed_count++;
 248         fei->global_feed_count++;
 249
 250         mutex_unlock(&fei->lock);
 251
 252         return 0;
 253 }
 254
 255 static int c8sectpfe_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
 256 {
 257
 258         struct dvb_demux *demux = dvbdmxfeed->demux;
 259         struct stdemux *stdemux = (struct stdemux *)demux->priv;
 260         struct c8sectpfei *fei = stdemux->c8sectpfei;
 261         struct channel_info *channel;
 262         int idlereq;
 263         u32 tmp;
 264         int ret;
 265         unsigned long *bitmap;
 266
 267         if (!atomic_read(&fei->fw_loaded)) {
 268                 ret = load_c8sectpfe_fw(fei);
 269                 if (ret)
 270                         return ret;
 271         }
 272
 273         mutex_lock(&fei->lock);
 274
 275         channel = fei->channel_data[stdemux->tsin_index];
 276
 277         bitmap = (unsigned long *) channel->pid_buffer_aligned;
 278
 279         if (dvbdmxfeed->pid == 8192) {
 280                 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 281                 tmp |= C8SECTPFE_PID_ENABLE;
 282                 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
 283         } else {
 284                 bitmap_clear(bitmap, dvbdmxfeed->pid, 1);
 285         }
 286
 287         /* manage cache so data is visible to HW */
 288         dma_sync_single_for_device(fei->dev,
 289                                         channel->pid_buffer_busaddr,
 290                                         PID_TABLE_SIZE,
 291                                         DMA_TO_DEVICE);
 292
 293         if (--stdemux->running_feed_count == 0) {
 294
 295                 channel = fei->channel_data[stdemux->tsin_index];
 296
 297                 /* TP re-configuration on page 168 of functional spec */
 298
 299                 /* disable IB (prevents more TS data going to memdma) */
 300                 writel(0, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
 301
 302                 /* disable this channels descriptor */
 303                 writel(0,  channel->irec + DMA_PRDS_TPENABLE);
 304
 305                 tasklet_disable(&channel->tsklet);
 306
 307                 /* now request memdma channel goes idle */
 308                 idlereq = (1 << channel->tsin_id) | IDLEREQ;
 309                 writel(idlereq, fei->io + DMA_IDLE_REQ);
 310
 311                 /* wait for idle irq handler to signal completion */
 312                 ret = wait_for_completion_timeout(&channel->idle_completion,
 313                                                 msecs_to_jiffies(100));
 314
 315                 if (ret == 0)
 316                         dev_warn(fei->dev,
 317                                 "Timeout waiting for idle irq on tsin%d\n",
 318                                 channel->tsin_id);
 319
 320                 reinit_completion(&channel->idle_completion);
 321
 322                 /* reset read / write ptrs for this channel */
 323
 324                 writel(channel->back_buffer_busaddr,
 325                         channel->irec + DMA_PRDS_BUSBASE_TP(0));
 326
 327                 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 328                 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
 329
 330                 writel(channel->back_buffer_busaddr,
 331                         channel->irec + DMA_PRDS_BUSWP_TP(0));
 332
 333                 dev_dbg(fei->dev,
 334                         "%s:%d stopping DMA feed on stdemux=%p channel=%d\n",
 335                         __func__, __LINE__, stdemux, channel->tsin_id);
 336
 337                 /* turn off all PIDS in the bitmap */
 338                 memset((void *)channel->pid_buffer_aligned
 339                         , 0x00, PID_TABLE_SIZE);
 340
 341                 /* manage cache so data is visible to HW */
 342                 dma_sync_single_for_device(fei->dev,
 343                                         channel->pid_buffer_busaddr,
 344                                         PID_TABLE_SIZE,
 345                                         DMA_TO_DEVICE);
 346
 347                 channel->active = 0;
 348         }
 349
 350         if (--fei->global_feed_count == 0) {
 351                 dev_dbg(fei->dev, "%s:%d global_feed_count=%d\n"
 352                         , __func__, __LINE__, fei->global_feed_count);
 353
 354                 del_timer(&fei->timer);
 355         }
 356
 357         mutex_unlock(&fei->lock);
 358
 359         return 0;
 360 }
 361
 362 static struct channel_info *find_channel(struct c8sectpfei *fei, int tsin_num)
 363 {
 364         int i;
 365
 366         for (i = 0; i < C8SECTPFE_MAX_TSIN_CHAN; i++) {
 367                 if (!fei->channel_data[i])
 368                         continue;
 369
 370                 if (fei->channel_data[i]->tsin_id == tsin_num)
 371                         return fei->channel_data[i];
 372         }
 373
 374         return NULL;
 375 }
 376
 377 static void c8sectpfe_getconfig(struct c8sectpfei *fei)
 378 {
 379         struct c8sectpfe_hw *hw = &fei->hw_stats;
 380
 381         hw->num_ib = readl(fei->io + SYS_CFG_NUM_IB);
 382         hw->num_mib = readl(fei->io + SYS_CFG_NUM_MIB);
 383         hw->num_swts = readl(fei->io + SYS_CFG_NUM_SWTS);
 384         hw->num_tsout = readl(fei->io + SYS_CFG_NUM_TSOUT);
 385         hw->num_ccsc = readl(fei->io + SYS_CFG_NUM_CCSC);
 386         hw->num_ram = readl(fei->io + SYS_CFG_NUM_RAM);
 387         hw->num_tp = readl(fei->io + SYS_CFG_NUM_TP);
 388
 389         dev_info(fei->dev, "C8SECTPFE hw supports the following:\n");
 390         dev_info(fei->dev, "Input Blocks: %d\n", hw->num_ib);
 391         dev_info(fei->dev, "Merged Input Blocks: %d\n", hw->num_mib);
 392         dev_info(fei->dev, "Software Transport Stream Inputs: %d\n"
 393                                 , hw->num_swts);
 394         dev_info(fei->dev, "Transport Stream Output: %d\n", hw->num_tsout);
 395         dev_info(fei->dev, "Cable Card Converter: %d\n", hw->num_ccsc);
 396         dev_info(fei->dev, "RAMs supported by C8SECTPFE: %d\n", hw->num_ram);
 397         dev_info(fei->dev, "Tango TPs supported by C8SECTPFE: %d\n"
 398                         , hw->num_tp);
 399 }
 400
 401 static irqreturn_t c8sectpfe_idle_irq_handler(int irq, void *priv)
 402 {
 403         struct c8sectpfei *fei = priv;
 404         struct channel_info *chan;
 405         int bit;
 406         unsigned long tmp = readl(fei->io + DMA_IDLE_REQ);
 407
 408         /* page 168 of functional spec: Clear the idle request
 409            by writing 0 to the C8SECTPFE_DMA_IDLE_REQ register. */
 410
 411         /* signal idle completion */
 412         for_each_set_bit(bit, &tmp, fei->hw_stats.num_ib) {
 413
 414                 chan = find_channel(fei, bit);
 415
 416                 if (chan)
 417                         complete(&chan->idle_completion);
 418         }
 419
 420         writel(0, fei->io + DMA_IDLE_REQ);
 421
 422         return IRQ_HANDLED;
 423 }
 424
 425
 426 static void free_input_block(struct c8sectpfei *fei, struct channel_info *tsin)
 427 {
 428         if (!fei || !tsin)
 429                 return;
 430
 431         if (tsin->back_buffer_busaddr)
 432                 if (!dma_mapping_error(fei->dev, tsin->back_buffer_busaddr))
 433                         dma_unmap_single(fei->dev, tsin->back_buffer_busaddr,
 434                                 FEI_BUFFER_SIZE, DMA_BIDIRECTIONAL);
 435
 436         kfree(tsin->back_buffer_start);
 437
 438         if (tsin->pid_buffer_busaddr)
 439                 if (!dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr))
 440                         dma_unmap_single(fei->dev, tsin->pid_buffer_busaddr,
 441                                 PID_TABLE_SIZE, DMA_BIDIRECTIONAL);
 442
 443         kfree(tsin->pid_buffer_start);
 444 }
 445
 446 #define MAX_NAME 20
 447
 448 static int configure_memdma_and_inputblock(struct c8sectpfei *fei,
 449                                 struct channel_info *tsin)
 450 {
 451         int ret;
 452         u32 tmp;
 453         char tsin_pin_name[MAX_NAME];
 454
 455         if (!fei || !tsin)
 456                 return -EINVAL;
 457
 458         dev_dbg(fei->dev, "%s:%d Configuring channel=%p tsin=%d\n"
 459                 , __func__, __LINE__, tsin, tsin->tsin_id);
 460
 461         init_completion(&tsin->idle_completion);
 462
 463         tsin->back_buffer_start = kzalloc(FEI_BUFFER_SIZE +
 464                                         FEI_ALIGNMENT, GFP_KERNEL);
 465
 466         if (!tsin->back_buffer_start) {
 467                 ret = -ENOMEM;
 468                 goto err_unmap;
 469         }
 470
 471         /* Ensure backbuffer is 32byte aligned */
 472         tsin->back_buffer_aligned = tsin->back_buffer_start
 473                 + FEI_ALIGNMENT;
 474
 475         tsin->back_buffer_aligned = (void *)
 476                 (((uintptr_t) tsin->back_buffer_aligned) & ~0x1F);
 477
 478         tsin->back_buffer_busaddr = dma_map_single(fei->dev,
 479                                         (void *)tsin->back_buffer_aligned,
 480                                         FEI_BUFFER_SIZE,
 481                                         DMA_BIDIRECTIONAL);
 482
 483         if (dma_mapping_error(fei->dev, tsin->back_buffer_busaddr)) {
 484                 dev_err(fei->dev, "failed to map back_buffer\n");
 485                 ret = -EFAULT;
 486                 goto err_unmap;
 487         }
 488
 489         /*
 490          * The pid buffer can be configured (in hw) for byte or bit
 491          * per pid. By powers of deduction we conclude stih407 family
 492          * is configured (at SoC design stage) for bit per pid.
 493          */
 494         tsin->pid_buffer_start = kzalloc(2048, GFP_KERNEL);
 495
 496         if (!tsin->pid_buffer_start) {
 497                 ret = -ENOMEM;
 498                 goto err_unmap;
 499         }
 500
 501         /*
 502          * PID buffer needs to be aligned to size of the pid table
 503          * which at bit per pid is 1024 bytes (8192 pids / 8).
 504          * PIDF_BASE register enforces this alignment when writing
 505          * the register.
 506          */
 507
 508         tsin->pid_buffer_aligned = tsin->pid_buffer_start +
 509                 PID_TABLE_SIZE;
 510
 511         tsin->pid_buffer_aligned = (void *)
 512                 (((uintptr_t) tsin->pid_buffer_aligned) & ~0x3ff);
 513
 514         tsin->pid_buffer_busaddr = dma_map_single(fei->dev,
 515                                                 tsin->pid_buffer_aligned,
 516                                                 PID_TABLE_SIZE,
 517                                                 DMA_BIDIRECTIONAL);
 518
 519         if (dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr)) {
 520                 dev_err(fei->dev, "failed to map pid_bitmap\n");
 521                 ret = -EFAULT;
 522                 goto err_unmap;
 523         }
 524
 525         /* manage cache so pid bitmap is visible to HW */
 526         dma_sync_single_for_device(fei->dev,
 527                                 tsin->pid_buffer_busaddr,
 528                                 PID_TABLE_SIZE,
 529                                 DMA_TO_DEVICE);
 530
 531         snprintf(tsin_pin_name, MAX_NAME, "tsin%d-%s", tsin->tsin_id,
 532                 (tsin->serial_not_parallel ? "serial" : "parallel"));
 533
 534         tsin->pstate = pinctrl_lookup_state(fei->pinctrl, tsin_pin_name);
 535         if (IS_ERR(tsin->pstate)) {
 536                 dev_err(fei->dev, "%s: pinctrl_lookup_state couldn't find %s state\n"
 537                         , __func__, tsin_pin_name);
 538                 ret = PTR_ERR(tsin->pstate);
 539                 goto err_unmap;
 540         }
 541
 542         ret = pinctrl_select_state(fei->pinctrl, tsin->pstate);
 543
 544         if (ret) {
 545                 dev_err(fei->dev, "%s: pinctrl_select_state failed\n"
 546                         , __func__);
 547                 goto err_unmap;
 548         }
 549
 550         /* Enable this input block */
 551         tmp = readl(fei->io + SYS_INPUT_CLKEN);
 552         tmp |= BIT(tsin->tsin_id);
 553         writel(tmp, fei->io + SYS_INPUT_CLKEN);
 554
 555         if (tsin->serial_not_parallel)
 556                 tmp |= C8SECTPFE_SERIAL_NOT_PARALLEL;
 557
 558         if (tsin->invert_ts_clk)
 559                 tmp |= C8SECTPFE_INVERT_TSCLK;
 560
 561         if (tsin->async_not_sync)
 562                 tmp |= C8SECTPFE_ASYNC_NOT_SYNC;
 563
 564         tmp |= C8SECTPFE_ALIGN_BYTE_SOP | C8SECTPFE_BYTE_ENDIANNESS_MSB;
 565
 566         writel(tmp, fei->io + C8SECTPFE_IB_IP_FMT_CFG(tsin->tsin_id));
 567
 568         writel(C8SECTPFE_SYNC(0x9) |
 569                 C8SECTPFE_DROP(0x9) |
 570                 C8SECTPFE_TOKEN(0x47),
 571                 fei->io + C8SECTPFE_IB_SYNCLCKDRP_CFG(tsin->tsin_id));
 572
 573         writel(TS_PKT_SIZE, fei->io + C8SECTPFE_IB_PKT_LEN(tsin->tsin_id));
 574
 575         /* Place the FIFO's at the end of the irec descriptors */
 576
 577         tsin->fifo = (tsin->tsin_id * FIFO_LEN);
 578
 579         writel(tsin->fifo, fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id));
 580         writel(tsin->fifo + FIFO_LEN - 1,
 581                 fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id));
 582
 583         writel(tsin->fifo, fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id));
 584         writel(tsin->fifo, fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id));
 585
 586         writel(tsin->pid_buffer_busaddr,
 587                 fei->io + PIDF_BASE(tsin->tsin_id));
 588
 589         dev_dbg(fei->dev, "chan=%d PIDF_BASE=0x%x pid_bus_addr=%pad\n",
 590                 tsin->tsin_id, readl(fei->io + PIDF_BASE(tsin->tsin_id)),
 591                 &tsin->pid_buffer_busaddr);
 592
 593         /* Configure and enable HW PID filtering */
 594
 595         /*
 596          * The PID value is created by assembling the first 8 bytes of
 597          * the TS packet into a 64-bit word in big-endian format. A
 598          * slice of that 64-bit word is taken from
 599          * (PID_OFFSET+PID_NUM_BITS-1) to PID_OFFSET.
 600          */
 601         tmp = (C8SECTPFE_PID_ENABLE | C8SECTPFE_PID_NUMBITS(13)
 602                 | C8SECTPFE_PID_OFFSET(40));
 603
 604         writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(tsin->tsin_id));
 605
 606         dev_dbg(fei->dev, "chan=%d setting wp: %d, rp: %d, buf: %d-%d\n",
 607                 tsin->tsin_id,
 608                 readl(fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id)),
 609                 readl(fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id)),
 610                 readl(fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id)),
 611                 readl(fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id)));
 612
 613         /* Get base addpress of pointer record block from DMEM */
 614         tsin->irec = fei->io + DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET +
 615                         readl(fei->io + DMA_PTRREC_BASE);
 616
 617         /* fill out pointer record data structure */
 618
 619         /* advance pointer record block to our channel */
 620         tsin->irec += (tsin->tsin_id * DMA_PRDS_SIZE);
 621
 622         writel(tsin->fifo, tsin->irec + DMA_PRDS_MEMBASE);
 623
 624         writel(tsin->fifo + FIFO_LEN - 1, tsin->irec + DMA_PRDS_MEMTOP);
 625
 626         writel((188 + 7)&~7, tsin->irec + DMA_PRDS_PKTSIZE);
 627
 628         writel(0x1, tsin->irec + DMA_PRDS_TPENABLE);
 629
 630         /* read/write pointers with physical bus address */
 631
 632         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSBASE_TP(0));
 633
 634         tmp = tsin->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
 635         writel(tmp, tsin->irec + DMA_PRDS_BUSTOP_TP(0));
 636
 637         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSWP_TP(0));
 638         writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSRP_TP(0));
 639
 640         /* initialize tasklet */
 641         tasklet_init(&tsin->tsklet, channel_swdemux_tsklet,
 642                 (unsigned long) tsin);
 643
 644         return 0;
 645
 646 err_unmap:
 647         free_input_block(fei, tsin);
 648         return ret;
 649 }
 650
 651 static irqreturn_t c8sectpfe_error_irq_handler(int irq, void *priv)
 652 {
 653         struct c8sectpfei *fei = priv;
 654
 655         dev_err(fei->dev, "%s: error handling not yet implemented\n"
 656                 , __func__);
 657
 658         /*
 659          * TODO FIXME we should detect some error conditions here
 660          * and ideally so something about them!
 661          */
 662
 663         return IRQ_HANDLED;
 664 }
 665
 666 static int c8sectpfe_probe(struct platform_device *pdev)
 667 {
 668         struct device *dev = &pdev->dev;
 669         struct device_node *child, *np = dev->of_node;
 670         struct c8sectpfei *fei;
 671         struct resource *res;
 672         int ret, index = 0;
 673         struct channel_info *tsin;
 674
 675         /* Allocate the c8sectpfei structure */
 676         fei = devm_kzalloc(dev, sizeof(struct c8sectpfei), GFP_KERNEL);
 677         if (!fei)
 678                 return -ENOMEM;
 679
 680         fei->dev = dev;
 681
 682         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "c8sectpfe");
 683         fei->io = devm_ioremap_resource(dev, res);
 684         if (IS_ERR(fei->io))
 685                 return PTR_ERR(fei->io);
 686
 687         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 688                                         "c8sectpfe-ram");
 689         fei->sram = devm_ioremap_resource(dev, res);
 690         if (IS_ERR(fei->sram))
 691                 return PTR_ERR(fei->sram);
 692
 693         fei->sram_size = resource_size(res);
 694
 695         fei->idle_irq = platform_get_irq_byname(pdev, "c8sectpfe-idle-irq");
 696         if (fei->idle_irq < 0)
 697                 return fei->idle_irq;
 698
 699         fei->error_irq = platform_get_irq_byname(pdev, "c8sectpfe-error-irq");
 700         if (fei->error_irq < 0)
 701                 return fei->error_irq;
 702
 703         platform_set_drvdata(pdev, fei);
 704
 705         fei->c8sectpfeclk = devm_clk_get(dev, "c8sectpfe");
 706         if (IS_ERR(fei->c8sectpfeclk)) {
 707                 dev_err(dev, "c8sectpfe clk not found\n");
 708                 return PTR_ERR(fei->c8sectpfeclk);
 709         }
 710
 711         ret = clk_prepare_enable(fei->c8sectpfeclk);
 712         if (ret) {
 713                 dev_err(dev, "Failed to enable c8sectpfe clock\n");
 714                 return ret;
 715         }
 716
 717         /* to save power disable all IP's (on by default) */
 718         writel(0, fei->io + SYS_INPUT_CLKEN);
 719
 720         /* Enable memdma clock */
 721         writel(MEMDMAENABLE, fei->io + SYS_OTHER_CLKEN);
 722
 723         /* clear internal sram */
 724         memset_io(fei->sram, 0x0, fei->sram_size);
 725
 726         c8sectpfe_getconfig(fei);
 727
 728         ret = devm_request_irq(dev, fei->idle_irq, c8sectpfe_idle_irq_handler,
 729                         0, "c8sectpfe-idle-irq", fei);
 730         if (ret) {
 731                 dev_err(dev, "Can't register c8sectpfe-idle-irq IRQ.\n");
 732                 goto err_clk_disable;
 733         }
 734
 735         ret = devm_request_irq(dev, fei->error_irq,
 736                                 c8sectpfe_error_irq_handler, 0,
 737                                 "c8sectpfe-error-irq", fei);
 738         if (ret) {
 739                 dev_err(dev, "Can't register c8sectpfe-error-irq IRQ.\n");
 740                 goto err_clk_disable;
 741         }
 742
 743         fei->tsin_count = of_get_child_count(np);
 744
 745         if (fei->tsin_count > C8SECTPFE_MAX_TSIN_CHAN ||
 746                 fei->tsin_count > fei->hw_stats.num_ib) {
 747
 748                 dev_err(dev, "More tsin declared than exist on SoC!\n");
 749                 ret = -EINVAL;
 750                 goto err_clk_disable;
 751         }
 752
 753         fei->pinctrl = devm_pinctrl_get(dev);
 754
 755         if (IS_ERR(fei->pinctrl)) {
 756                 dev_err(dev, "Error getting tsin pins\n");
 757                 ret = PTR_ERR(fei->pinctrl);
 758                 goto err_clk_disable;
 759         }
 760
 761         for_each_child_of_node(np, child) {
 762                 struct device_node *i2c_bus;
 763
 764                 fei->channel_data[index] = devm_kzalloc(dev,
 765                                                 sizeof(struct channel_info),
 766                                                 GFP_KERNEL);
 767
 768                 if (!fei->channel_data[index]) {
 769                         ret = -ENOMEM;
 770                         goto err_clk_disable;
 771                 }
 772
 773                 tsin = fei->channel_data[index];
 774
 775                 tsin->fei = fei;
 776
 777                 ret = of_property_read_u32(child, "tsin-num", &tsin->tsin_id);
 778                 if (ret) {
 779                         dev_err(&pdev->dev, "No tsin_num found\n");
 780                         goto err_clk_disable;
 781                 }
 782
 783                 /* sanity check value */
 784                 if (tsin->tsin_id > fei->hw_stats.num_ib) {
 785                         dev_err(&pdev->dev,
 786                                 "tsin-num %d specified greater than number\n\tof input block hw in SoC! (%d)",
 787                                 tsin->tsin_id, fei->hw_stats.num_ib);
 788                         ret = -EINVAL;
 789                         goto err_clk_disable;
 790                 }
 791
 792                 tsin->invert_ts_clk = of_property_read_bool(child,
 793                                                         "invert-ts-clk");
 794
 795                 tsin->serial_not_parallel = of_property_read_bool(child,
 796                                                         "serial-not-parallel");
 797
 798                 tsin->async_not_sync = of_property_read_bool(child,
 799                                                         "async-not-sync");
 800
 801                 ret = of_property_read_u32(child, "dvb-card",
 802                                         &tsin->dvb_card);
 803                 if (ret) {
 804                         dev_err(&pdev->dev, "No dvb-card found\n");
 805                         goto err_clk_disable;
 806                 }
 807
 808                 i2c_bus = of_parse_phandle(child, "i2c-bus", 0);
 809                 if (!i2c_bus) {
 810                         dev_err(&pdev->dev, "No i2c-bus found\n");
 811                         ret = -ENODEV;
 812                         goto err_clk_disable;
 813                 }
 814                 tsin->i2c_adapter =
 815                         of_find_i2c_adapter_by_node(i2c_bus);
 816                 if (!tsin->i2c_adapter) {
 817                         dev_err(&pdev->dev, "No i2c adapter found\n");
 818                         of_node_put(i2c_bus);
 819                         ret = -ENODEV;
 820                         goto err_clk_disable;
 821                 }
 822                 of_node_put(i2c_bus);
 823
 824                 tsin->rst_gpio = of_get_named_gpio(child, "reset-gpios", 0);
 825
 826                 ret = gpio_is_valid(tsin->rst_gpio);
 827                 if (!ret) {
 828                         dev_err(dev,
 829                                 "reset gpio for tsin%d not valid (gpio=%d)\n",
 830                                 tsin->tsin_id, tsin->rst_gpio);
 831                         goto err_clk_disable;
 832                 }
 833
 834                 ret = devm_gpio_request_one(dev, tsin->rst_gpio,
 835                                         GPIOF_OUT_INIT_LOW, "NIM reset");
 836                 if (ret && ret != -EBUSY) {
 837                         dev_err(dev, "Can't request tsin%d reset gpio\n"
 838                                 , fei->channel_data[index]->tsin_id);
 839                         goto err_clk_disable;
 840                 }
 841
 842                 if (!ret) {
 843                         /* toggle reset lines */
 844                         gpio_direction_output(tsin->rst_gpio, 0);
 845                         usleep_range(3500, 5000);
 846                         gpio_direction_output(tsin->rst_gpio, 1);
 847                         usleep_range(3000, 5000);
 848                 }
 849
 850                 tsin->demux_mapping = index;
 851
 852                 dev_dbg(fei->dev,
 853                         "channel=%p n=%d tsin_num=%d, invert-ts-clk=%d\n\tserial-not-parallel=%d pkt-clk-valid=%d dvb-card=%d\n",
 854                         fei->channel_data[index], index,
 855                         tsin->tsin_id, tsin->invert_ts_clk,
 856                         tsin->serial_not_parallel, tsin->async_not_sync,
 857                         tsin->dvb_card);
 858
 859                 index++;
 860         }
 861
 862         /* Setup timer interrupt */
 863         timer_setup(&fei->timer, c8sectpfe_timer_interrupt, 0);
 864
 865         mutex_init(&fei->lock);
 866
 867         /* Get the configuration information about the tuners */
 868         ret = c8sectpfe_tuner_register_frontend(&fei->c8sectpfe[0],
 869                                         (void *)fei,
 870                                         c8sectpfe_start_feed,
 871                                         c8sectpfe_stop_feed);
 872         if (ret) {
 873                 dev_err(dev, "c8sectpfe_tuner_register_frontend failed (%d)\n",
 874                         ret);
 875                 goto err_clk_disable;
 876         }
 877
 878         c8sectpfe_debugfs_init(fei);
 879
 880         return 0;
 881
 882 err_clk_disable:
 883         clk_disable_unprepare(fei->c8sectpfeclk);
 884         return ret;
 885 }
 886
 887 static int c8sectpfe_remove(struct platform_device *pdev)
 888 {
 889         struct c8sectpfei *fei = platform_get_drvdata(pdev);
 890         struct channel_info *channel;
 891         int i;
 892
 893         wait_for_completion(&fei->fw_ack);
 894
 895         c8sectpfe_tuner_unregister_frontend(fei->c8sectpfe[0], fei);
 896
 897         /*
 898          * Now loop through and un-configure each of the InputBlock resources
 899          */
 900         for (i = 0; i < fei->tsin_count; i++) {
 901                 channel = fei->channel_data[i];
 902                 free_input_block(fei, channel);
 903         }
 904
 905         c8sectpfe_debugfs_exit(fei);
 906
 907         dev_info(fei->dev, "Stopping memdma SLIM core\n");
 908         if (readl(fei->io + DMA_CPU_RUN))
 909                 writel(0x0,  fei->io + DMA_CPU_RUN);
 910
 911         /* unclock all internal IP's */
 912         if (readl(fei->io + SYS_INPUT_CLKEN))
 913                 writel(0, fei->io + SYS_INPUT_CLKEN);
 914
 915         if (readl(fei->io + SYS_OTHER_CLKEN))
 916                 writel(0, fei->io + SYS_OTHER_CLKEN);
 917
 918         if (fei->c8sectpfeclk)
 919                 clk_disable_unprepare(fei->c8sectpfeclk);
 920
 921         return 0;
 922 }
 923
 924
 925 static int configure_channels(struct c8sectpfei *fei)
 926 {
 927         int index = 0, ret;
 928         struct channel_info *tsin;
 929         struct device_node *child, *np = fei->dev->of_node;
 930
 931         /* iterate round each tsin and configure memdma descriptor and IB hw */
 932         for_each_child_of_node(np, child) {
 933
 934                 tsin = fei->channel_data[index];
 935
 936                 ret = configure_memdma_and_inputblock(fei,
 937                                                 fei->channel_data[index]);
 938
 939                 if (ret) {
 940                         dev_err(fei->dev,
 941                                 "configure_memdma_and_inputblock failed\n");
 942                         goto err_unmap;
 943                 }
 944                 index++;
 945         }
 946
 947         return 0;
 948
 949 err_unmap:
 950         for (index = 0; index < fei->tsin_count; index++) {
 951                 tsin = fei->channel_data[index];
 952                 free_input_block(fei, tsin);
 953         }
 954         return ret;
 955 }
 956
 957 static int
 958 c8sectpfe_elf_sanity_check(struct c8sectpfei *fei, const struct firmware *fw)
 959 {
 960         struct elf32_hdr *ehdr;
 961         char class;
 962
 963         if (!fw) {
 964                 dev_err(fei->dev, "failed to load %s\n", FIRMWARE_MEMDMA);
 965                 return -EINVAL;
 966         }
 967
 968         if (fw->size < sizeof(struct elf32_hdr)) {
 969                 dev_err(fei->dev, "Image is too small\n");
 970                 return -EINVAL;
 971         }
 972
 973         ehdr = (struct elf32_hdr *)fw->data;
 974
 975         /* We only support ELF32 at this point */
 976         class = ehdr->e_ident[EI_CLASS];
 977         if (class != ELFCLASS32) {
 978                 dev_err(fei->dev, "Unsupported class: %d\n", class);
 979                 return -EINVAL;
 980         }
 981
 982         if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
 983                 dev_err(fei->dev, "Unsupported firmware endianness\n");
 984                 return -EINVAL;
 985         }
 986
 987         if (fw->size < ehdr->e_shoff + sizeof(struct elf32_shdr)) {
 988                 dev_err(fei->dev, "Image is too small\n");
 989                 return -EINVAL;
 990         }
 991
 992         if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
 993                 dev_err(fei->dev, "Image is corrupted (bad magic)\n");
 994                 return -EINVAL;
 995         }
 996
 997         /* Check ELF magic */
 998         ehdr = (Elf32_Ehdr *)fw->data;
 999         if (ehdr->e_ident[EI_MAG0] != ELFMAG0 ||
1000             ehdr->e_ident[EI_MAG1] != ELFMAG1 ||
1001             ehdr->e_ident[EI_MAG2] != ELFMAG2 ||
1002             ehdr->e_ident[EI_MAG3] != ELFMAG3) {
1003                 dev_err(fei->dev, "Invalid ELF magic\n");
1004                 return -EINVAL;
1005         }
1006
1007         if (ehdr->e_type != ET_EXEC) {
1008                 dev_err(fei->dev, "Unsupported ELF header type\n");
1009                 return -EINVAL;
1010         }
1011
1012         if (ehdr->e_phoff > fw->size) {
1013                 dev_err(fei->dev, "Firmware size is too small\n");
1014                 return -EINVAL;
1015         }
1016
1017         return 0;
1018 }
1019
1020
1021 static void load_imem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1022                         const struct firmware *fw, u8 __iomem *dest,
1023                         int seg_num)
1024 {
1025         const u8 *imem_src = fw->data + phdr->p_offset;
1026         int i;
1027
1028         /*
1029          * For IMEM segments, the segment contains 24-bit
1030          * instructions which must be padded to 32-bit
1031          * instructions before being written. The written
1032          * segment is padded with NOP instructions.
1033          */
1034
1035         dev_dbg(fei->dev,
1036                 "Loading IMEM segment %d 0x%08x\n\t (0x%x bytes) -> 0x%p (0x%x bytes)\n",
1037 seg_num,
1038                 phdr->p_paddr, phdr->p_filesz,
1039                 dest, phdr->p_memsz + phdr->p_memsz / 3);
1040
1041         for (i = 0; i < phdr->p_filesz; i++) {
1042
1043                 writeb(readb((void __iomem *)imem_src), (void __iomem *)dest);
1044
1045                 /* Every 3 bytes, add an additional
1046                  * padding zero in destination */
1047                 if (i % 3 == 2) {
1048                         dest++;
1049                         writeb(0x00, (void __iomem *)dest);
1050                 }
1051
1052                 dest++;
1053                 imem_src++;
1054         }
1055 }
1056
1057 static void load_dmem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
1058                         const struct firmware *fw, u8 __iomem *dst, int seg_num)
1059 {
1060         /*
1061          * For DMEM segments copy the segment data from the ELF
1062          * file and pad segment with zeroes
1063          */
1064
1065         dev_dbg(fei->dev,
1066                 "Loading DMEM segment %d 0x%08x\n\t(0x%x bytes) -> 0x%p (0x%x bytes)\n",
1067                 seg_num, phdr->p_paddr, phdr->p_filesz,
1068                 dst, phdr->p_memsz);
1069
1070         memcpy((void __force *)dst, (void *)fw->data + phdr->p_offset,
1071                 phdr->p_filesz);
1072
1073         memset((void __force *)dst + phdr->p_filesz, 0,
1074                 phdr->p_memsz - phdr->p_filesz);
1075 }
1076
1077 static int load_slim_core_fw(const struct firmware *fw, struct c8sectpfei *fei)
1078 {
1079         Elf32_Ehdr *ehdr;
1080         Elf32_Phdr *phdr;
1081         u8 __iomem *dst;
1082         int err = 0, i;
1083
1084         if (!fw || !fei)
1085                 return -EINVAL;
1086
1087         ehdr = (Elf32_Ehdr *)fw->data;
1088         phdr = (Elf32_Phdr *)(fw->data + ehdr->e_phoff);
1089
1090         /* go through the available ELF segments */
1091         for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
1092
1093                 /* Only consider LOAD segments */
1094                 if (phdr->p_type != PT_LOAD)
1095                         continue;
1096
1097                 /*
1098                  * Check segment is contained within the fw->data buffer
1099                  */
1100                 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1101                         dev_err(fei->dev,
1102                                 "Segment %d is outside of firmware file\n", i);
1103                         err = -EINVAL;
1104                         break;
1105                 }
1106
1107                 /*
1108                  * MEMDMA IMEM has executable flag set, otherwise load
1109                  * this segment into DMEM.
1110                  *
1111                  */
1112
1113                 if (phdr->p_flags & PF_X) {
1114                         dst = (u8 __iomem *) fei->io + DMA_MEMDMA_IMEM;
1115                         /*
1116                          * The Slim ELF file uses 32-bit word addressing for
1117                          * load offsets.
1118                          */
1119                         dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1120                         load_imem_segment(fei, phdr, fw, dst, i);
1121                 } else {
1122                         dst = (u8 __iomem *) fei->io + DMA_MEMDMA_DMEM;
1123                         /*
1124                          * The Slim ELF file uses 32-bit word addressing for
1125                          * load offsets.
1126                          */
1127                         dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int);
1128                         load_dmem_segment(fei, phdr, fw, dst, i);
1129                 }
1130         }
1131
1132         release_firmware(fw);
1133         return err;
1134 }
1135
1136 static int load_c8sectpfe_fw(struct c8sectpfei *fei)
1137 {
1138         const struct firmware *fw;
1139         int err;
1140
1141         dev_info(fei->dev, "Loading firmware: %s\n", FIRMWARE_MEMDMA);
1142
1143         err = request_firmware(&fw, FIRMWARE_MEMDMA, fei->dev);
1144         if (err)
1145                 return err;
1146
1147         err = c8sectpfe_elf_sanity_check(fei, fw);
1148         if (err) {
1149                 dev_err(fei->dev, "c8sectpfe_elf_sanity_check failed err=(%d)\n"
1150                         , err);
1151                 release_firmware(fw);
1152                 return err;
1153         }
1154
1155         err = load_slim_core_fw(fw, fei);
1156         if (err) {
1157                 dev_err(fei->dev, "load_slim_core_fw failed err=(%d)\n", err);
1158                 return err;
1159         }
1160
1161         /* now the firmware is loaded configure the input blocks */
1162         err = configure_channels(fei);
1163         if (err) {
1164                 dev_err(fei->dev, "configure_channels failed err=(%d)\n", err);
1165                 return err;
1166         }
1167
1168         /*
1169          * STBus target port can access IMEM and DMEM ports
1170          * without waiting for CPU
1171          */
1172         writel(0x1, fei->io + DMA_PER_STBUS_SYNC);
1173
1174         dev_info(fei->dev, "Boot the memdma SLIM core\n");
1175         writel(0x1,  fei->io + DMA_CPU_RUN);
1176
1177         atomic_set(&fei->fw_loaded, 1);
1178
1179         return 0;
1180 }
1181
1182 static const struct of_device_id c8sectpfe_match[] = {
1183         { .compatible = "st,stih407-c8sectpfe" },
1184         { /* sentinel */ },
1185 };
1186 MODULE_DEVICE_TABLE(of, c8sectpfe_match);
1187
1188 static struct platform_driver c8sectpfe_driver = {
1189         .driver = {
1190                 .name = "c8sectpfe",
1191                 .of_match_table = of_match_ptr(c8sectpfe_match),
1192         },
1193         .probe  = c8sectpfe_probe,
1194         .remove = c8sectpfe_remove,
1195 };
1196
1197 module_platform_driver(c8sectpfe_driver);
1198
1199 MODULE_AUTHOR("Peter Bennett <peter.bennett@st.com>");
1200 MODULE_AUTHOR("Peter Griffin <peter.griffin@linaro.org>");
1201 MODULE_DESCRIPTION("C8SECTPFE STi DVB Driver");
1202 MODULE_LICENSE("GPL");