1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) STMicroelectronics SA 2017
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
17 #include <media/cec.h>
19 #define CEC_NAME "stm32-cec"
22 #define CEC_CR 0x0000 /* Control Register */
23 #define CEC_CFGR 0x0004 /* ConFiGuration Register */
24 #define CEC_TXDR 0x0008 /* Rx data Register */
25 #define CEC_RXDR 0x000C /* Rx data Register */
26 #define CEC_ISR 0x0010 /* Interrupt and status Register */
27 #define CEC_IER 0x0014 /* Interrupt enable Register */
34 #define OAR GENMASK(30, 16)
36 #define BRDNOGEN BIT(7)
37 #define LBPEGEN BIT(6)
41 #define SFT GENMASK(2, 0)
42 #define FULL_CFG (LSTN | SFTOP | BRDNOGEN | LBPEGEN | BREGEN | BRESTP \
45 #define TXACKE BIT(12)
56 #define ALL_TX_IT (TXEND | TXBR | TXACKE | TXERR | TXUDR | ARBLST)
57 #define ALL_RX_IT (RXEND | RXBR | RXACKE | RXOVR)
60 * 400 ms is the time it takes for one 16 byte message to be
61 * transferred and 5 is the maximum number of retries. Add
62 * another 100 ms as a margin.
64 #define CEC_XFER_TIMEOUT_MS (5 * 400 + 100)
67 struct cec_adapter *adap;
70 struct clk *clk_hdmi_cec;
71 struct reset_control *rstc;
72 struct regmap *regmap;
75 struct cec_msg rx_msg;
76 struct cec_msg tx_msg;
80 static void cec_hw_init(struct stm32_cec *cec)
82 regmap_update_bits(cec->regmap, CEC_CR, TXEOM | TXSOM | CECEN, 0);
84 regmap_update_bits(cec->regmap, CEC_IER, ALL_TX_IT | ALL_RX_IT,
85 ALL_TX_IT | ALL_RX_IT);
87 regmap_update_bits(cec->regmap, CEC_CFGR, FULL_CFG, FULL_CFG);
90 static void stm32_tx_done(struct stm32_cec *cec, u32 status)
92 if (status & (TXERR | TXUDR)) {
93 cec_transmit_done(cec->adap, CEC_TX_STATUS_ERROR,
98 if (status & ARBLST) {
99 cec_transmit_done(cec->adap, CEC_TX_STATUS_ARB_LOST,
104 if (status & TXACKE) {
105 cec_transmit_done(cec->adap, CEC_TX_STATUS_NACK,
110 if (cec->irq_status & TXBR) {
112 if (cec->tx_cnt < cec->tx_msg.len)
113 regmap_write(cec->regmap, CEC_TXDR,
114 cec->tx_msg.msg[cec->tx_cnt++]);
116 /* TXEOM is set to command transmission of the last byte */
117 if (cec->tx_cnt == cec->tx_msg.len)
118 regmap_update_bits(cec->regmap, CEC_CR, TXEOM, TXEOM);
121 if (cec->irq_status & TXEND)
122 cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
125 static void stm32_rx_done(struct stm32_cec *cec, u32 status)
127 if (cec->irq_status & (RXACKE | RXOVR)) {
132 if (cec->irq_status & RXBR) {
135 regmap_read(cec->regmap, CEC_RXDR, &val);
136 cec->rx_msg.msg[cec->rx_msg.len++] = val & 0xFF;
139 if (cec->irq_status & RXEND) {
140 cec_received_msg(cec->adap, &cec->rx_msg);
145 static irqreturn_t stm32_cec_irq_thread(int irq, void *arg)
147 struct stm32_cec *cec = arg;
149 if (cec->irq_status & ALL_TX_IT)
150 stm32_tx_done(cec, cec->irq_status);
152 if (cec->irq_status & ALL_RX_IT)
153 stm32_rx_done(cec, cec->irq_status);
160 static irqreturn_t stm32_cec_irq_handler(int irq, void *arg)
162 struct stm32_cec *cec = arg;
164 regmap_read(cec->regmap, CEC_ISR, &cec->irq_status);
166 regmap_update_bits(cec->regmap, CEC_ISR,
167 ALL_TX_IT | ALL_RX_IT,
168 ALL_TX_IT | ALL_RX_IT);
170 return IRQ_WAKE_THREAD;
173 static int stm32_cec_adap_enable(struct cec_adapter *adap, bool enable)
175 struct stm32_cec *cec = adap->priv;
179 ret = clk_enable(cec->clk_cec);
181 dev_err(cec->dev, "fail to enable cec clock\n");
183 clk_enable(cec->clk_hdmi_cec);
184 regmap_update_bits(cec->regmap, CEC_CR, CECEN, CECEN);
186 clk_disable(cec->clk_cec);
187 clk_disable(cec->clk_hdmi_cec);
188 regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
194 static int stm32_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
196 struct stm32_cec *cec = adap->priv;
197 u32 oar = (1 << logical_addr) << 16;
200 /* Poll every 100µs the register CEC_CR to wait end of transmission */
201 regmap_read_poll_timeout(cec->regmap, CEC_CR, val, !(val & TXSOM),
202 100, CEC_XFER_TIMEOUT_MS * 1000);
203 regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
205 if (logical_addr == CEC_LOG_ADDR_INVALID)
206 regmap_update_bits(cec->regmap, CEC_CFGR, OAR, 0);
208 regmap_update_bits(cec->regmap, CEC_CFGR, oar, oar);
210 regmap_update_bits(cec->regmap, CEC_CR, CECEN, CECEN);
215 static int stm32_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
216 u32 signal_free_time, struct cec_msg *msg)
218 struct stm32_cec *cec = adap->priv;
225 * If the CEC message consists of only one byte,
226 * TXEOM must be set before of TXSOM.
228 if (cec->tx_msg.len == 1)
229 regmap_update_bits(cec->regmap, CEC_CR, TXEOM, TXEOM);
231 /* TXSOM is set to command transmission of the first byte */
232 regmap_update_bits(cec->regmap, CEC_CR, TXSOM, TXSOM);
234 /* Write the header (first byte of message) */
235 regmap_write(cec->regmap, CEC_TXDR, cec->tx_msg.msg[0]);
241 static const struct cec_adap_ops stm32_cec_adap_ops = {
242 .adap_enable = stm32_cec_adap_enable,
243 .adap_log_addr = stm32_cec_adap_log_addr,
244 .adap_transmit = stm32_cec_adap_transmit,
247 static const struct regmap_config stm32_cec_regmap_cfg = {
250 .reg_stride = sizeof(u32),
251 .max_register = 0x14,
255 static int stm32_cec_probe(struct platform_device *pdev)
257 u32 caps = CEC_CAP_DEFAULTS | CEC_CAP_PHYS_ADDR | CEC_MODE_MONITOR_ALL;
258 struct resource *res;
259 struct stm32_cec *cec;
263 cec = devm_kzalloc(&pdev->dev, sizeof(*cec), GFP_KERNEL);
267 cec->dev = &pdev->dev;
269 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
270 mmio = devm_ioremap_resource(&pdev->dev, res);
272 return PTR_ERR(mmio);
274 cec->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "cec", mmio,
275 &stm32_cec_regmap_cfg);
277 if (IS_ERR(cec->regmap))
278 return PTR_ERR(cec->regmap);
280 cec->irq = platform_get_irq(pdev, 0);
284 ret = devm_request_threaded_irq(&pdev->dev, cec->irq,
285 stm32_cec_irq_handler,
286 stm32_cec_irq_thread,
292 cec->clk_cec = devm_clk_get(&pdev->dev, "cec");
293 if (IS_ERR(cec->clk_cec)) {
294 dev_err(&pdev->dev, "Cannot get cec clock\n");
295 return PTR_ERR(cec->clk_cec);
298 ret = clk_prepare(cec->clk_cec);
300 dev_err(&pdev->dev, "Unable to prepare cec clock\n");
304 cec->clk_hdmi_cec = devm_clk_get(&pdev->dev, "hdmi-cec");
305 if (!IS_ERR(cec->clk_hdmi_cec)) {
306 ret = clk_prepare(cec->clk_hdmi_cec);
308 dev_err(&pdev->dev, "Unable to prepare hdmi-cec clock\n");
314 * CEC_CAP_PHYS_ADDR caps should be removed when a cec notifier is
315 * available for example when a drm driver can provide edid
317 cec->adap = cec_allocate_adapter(&stm32_cec_adap_ops, cec,
318 CEC_NAME, caps, CEC_MAX_LOG_ADDRS);
319 ret = PTR_ERR_OR_ZERO(cec->adap);
323 ret = cec_register_adapter(cec->adap, &pdev->dev);
325 cec_delete_adapter(cec->adap);
331 platform_set_drvdata(pdev, cec);
336 static int stm32_cec_remove(struct platform_device *pdev)
338 struct stm32_cec *cec = platform_get_drvdata(pdev);
340 clk_unprepare(cec->clk_cec);
341 clk_unprepare(cec->clk_hdmi_cec);
343 cec_unregister_adapter(cec->adap);
348 static const struct of_device_id stm32_cec_of_match[] = {
349 { .compatible = "st,stm32-cec" },
352 MODULE_DEVICE_TABLE(of, stm32_cec_of_match);
354 static struct platform_driver stm32_cec_driver = {
355 .probe = stm32_cec_probe,
356 .remove = stm32_cec_remove,
359 .of_match_table = stm32_cec_of_match,
363 module_platform_driver(stm32_cec_driver);
365 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
366 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
367 MODULE_DESCRIPTION("STMicroelectronics STM32 Consumer Electronics Control");
368 MODULE_LICENSE("GPL v2");