1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
5 * Copyright (c) 2013 Texas Instruments Inc.
6 * David Griego, <dagriego@biglakesoftware.com>
7 * Dale Farnsworth, <dale@farnsworth.org>
8 * Archit Taneja, <archit@ti.com>
10 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
11 * Pawel Osciak, <pawel@osciak.com>
12 * Marek Szyprowski, <m.szyprowski@samsung.com>
14 * Based on the virtual v4l2-mem2mem example device
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
21 #include <linux/interrupt.h>
23 #include <linux/ioctl.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/videodev2.h>
31 #include <linux/log2.h>
32 #include <linux/sizes.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-ctrls.h>
36 #include <media/v4l2-device.h>
37 #include <media/v4l2-event.h>
38 #include <media/v4l2-ioctl.h>
39 #include <media/v4l2-mem2mem.h>
40 #include <media/videobuf2-v4l2.h>
41 #include <media/videobuf2-dma-contig.h>
44 #include "vpdma_priv.h"
49 #define VPE_MODULE_NAME "vpe"
51 /* minimum and maximum frame sizes */
57 /* required alignments */
58 #define S_ALIGN 0 /* multiple of 1 */
59 #define H_ALIGN 1 /* multiple of 2 */
61 /* flags that indicate a format can be used for capture/output */
62 #define VPE_FMT_TYPE_CAPTURE (1 << 0)
63 #define VPE_FMT_TYPE_OUTPUT (1 << 1)
65 /* used as plane indices */
66 #define VPE_MAX_PLANES 2
70 /* per m2m context info */
71 #define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
73 #define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
76 * each VPE context can need up to 3 config descriptors, 7 input descriptors,
77 * 3 output descriptors, and 10 control descriptors
79 #define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
80 13 * VPDMA_CFD_CTD_DESC_SIZE)
82 #define vpe_dbg(vpedev, fmt, arg...) \
83 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
84 #define vpe_err(vpedev, fmt, arg...) \
85 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
87 struct vpe_us_coeffs {
88 unsigned short anchor_fid0_c0;
89 unsigned short anchor_fid0_c1;
90 unsigned short anchor_fid0_c2;
91 unsigned short anchor_fid0_c3;
92 unsigned short interp_fid0_c0;
93 unsigned short interp_fid0_c1;
94 unsigned short interp_fid0_c2;
95 unsigned short interp_fid0_c3;
96 unsigned short anchor_fid1_c0;
97 unsigned short anchor_fid1_c1;
98 unsigned short anchor_fid1_c2;
99 unsigned short anchor_fid1_c3;
100 unsigned short interp_fid1_c0;
101 unsigned short interp_fid1_c1;
102 unsigned short interp_fid1_c2;
103 unsigned short interp_fid1_c3;
107 * Default upsampler coefficients
109 static const struct vpe_us_coeffs us_coeffs[] = {
111 /* Coefficients for progressive input */
112 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
113 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
116 /* Coefficients for Top Field Interlaced input */
117 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
118 /* Coefficients for Bottom Field Interlaced input */
119 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
124 * the following registers are for configuring some of the parameters of the
125 * motion and edge detection blocks inside DEI, these generally remain the same,
126 * these could be passed later via userspace if some one needs to tweak these.
128 struct vpe_dei_regs {
129 unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */
130 unsigned long edi_config_reg; /* VPE_DEI_REG3 */
131 unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */
132 unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */
133 unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */
134 unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */
138 * default expert DEI register values, unlikely to be modified.
140 static const struct vpe_dei_regs dei_regs = {
141 .mdt_spacial_freq_thr_reg = 0x020C0804u,
142 .edi_config_reg = 0x0118100Cu,
143 .edi_lut_reg0 = 0x08040200u,
144 .edi_lut_reg1 = 0x1010100Cu,
145 .edi_lut_reg2 = 0x10101010u,
146 .edi_lut_reg3 = 0x10101010u,
150 * The port_data structure contains per-port data.
152 struct vpe_port_data {
153 enum vpdma_channel channel; /* VPDMA channel */
154 u8 vb_index; /* input frame f, f-1, f-2 index */
155 u8 vb_part; /* plane index for co-panar formats */
159 * Define indices into the port_data tables
161 #define VPE_PORT_LUMA1_IN 0
162 #define VPE_PORT_CHROMA1_IN 1
163 #define VPE_PORT_LUMA2_IN 2
164 #define VPE_PORT_CHROMA2_IN 3
165 #define VPE_PORT_LUMA3_IN 4
166 #define VPE_PORT_CHROMA3_IN 5
167 #define VPE_PORT_MV_IN 6
168 #define VPE_PORT_MV_OUT 7
169 #define VPE_PORT_LUMA_OUT 8
170 #define VPE_PORT_CHROMA_OUT 9
171 #define VPE_PORT_RGB_OUT 10
173 static const struct vpe_port_data port_data[11] = {
174 [VPE_PORT_LUMA1_IN] = {
175 .channel = VPE_CHAN_LUMA1_IN,
179 [VPE_PORT_CHROMA1_IN] = {
180 .channel = VPE_CHAN_CHROMA1_IN,
182 .vb_part = VPE_CHROMA,
184 [VPE_PORT_LUMA2_IN] = {
185 .channel = VPE_CHAN_LUMA2_IN,
189 [VPE_PORT_CHROMA2_IN] = {
190 .channel = VPE_CHAN_CHROMA2_IN,
192 .vb_part = VPE_CHROMA,
194 [VPE_PORT_LUMA3_IN] = {
195 .channel = VPE_CHAN_LUMA3_IN,
199 [VPE_PORT_CHROMA3_IN] = {
200 .channel = VPE_CHAN_CHROMA3_IN,
202 .vb_part = VPE_CHROMA,
205 .channel = VPE_CHAN_MV_IN,
207 [VPE_PORT_MV_OUT] = {
208 .channel = VPE_CHAN_MV_OUT,
210 [VPE_PORT_LUMA_OUT] = {
211 .channel = VPE_CHAN_LUMA_OUT,
214 [VPE_PORT_CHROMA_OUT] = {
215 .channel = VPE_CHAN_CHROMA_OUT,
216 .vb_part = VPE_CHROMA,
218 [VPE_PORT_RGB_OUT] = {
219 .channel = VPE_CHAN_RGB_OUT,
225 /* driver info for each of the supported video formats */
227 u32 fourcc; /* standard format identifier */
228 u8 types; /* CAPTURE and/or OUTPUT */
229 u8 coplanar; /* set for unpacked Luma and Chroma */
230 /* vpdma format info for each plane */
231 struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
234 static struct vpe_fmt vpe_formats[] = {
236 .fourcc = V4L2_PIX_FMT_NV16,
237 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
239 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
240 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
244 .fourcc = V4L2_PIX_FMT_NV12,
245 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
247 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
248 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
252 .fourcc = V4L2_PIX_FMT_YUYV,
253 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
255 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422],
259 .fourcc = V4L2_PIX_FMT_UYVY,
260 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
262 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422],
266 .fourcc = V4L2_PIX_FMT_RGB24,
267 .types = VPE_FMT_TYPE_CAPTURE,
269 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
273 .fourcc = V4L2_PIX_FMT_RGB32,
274 .types = VPE_FMT_TYPE_CAPTURE,
276 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
280 .fourcc = V4L2_PIX_FMT_BGR24,
281 .types = VPE_FMT_TYPE_CAPTURE,
283 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
287 .fourcc = V4L2_PIX_FMT_BGR32,
288 .types = VPE_FMT_TYPE_CAPTURE,
290 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
294 .fourcc = V4L2_PIX_FMT_RGB565,
295 .types = VPE_FMT_TYPE_CAPTURE,
297 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB565],
301 .fourcc = V4L2_PIX_FMT_RGB555,
302 .types = VPE_FMT_TYPE_CAPTURE,
304 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGBA16_5551],
310 * per-queue, driver-specific private data.
311 * there is one source queue and one destination queue for each m2m context.
314 unsigned int width; /* frame width */
315 unsigned int height; /* frame height */
316 unsigned int nplanes; /* Current number of planes */
317 unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */
318 enum v4l2_colorspace colorspace;
319 enum v4l2_field field; /* supported field value */
321 unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */
322 struct v4l2_rect c_rect; /* crop/compose rectangle */
323 struct vpe_fmt *fmt; /* format info */
326 /* vpe_q_data flag bits */
327 #define Q_DATA_FRAME_1D BIT(0)
328 #define Q_DATA_MODE_TILED BIT(1)
329 #define Q_DATA_INTERLACED_ALTERNATE BIT(2)
330 #define Q_DATA_INTERLACED_SEQ_TB BIT(3)
332 #define Q_IS_INTERLACED (Q_DATA_INTERLACED_ALTERNATE | \
333 Q_DATA_INTERLACED_SEQ_TB)
340 /* find our format description corresponding to the passed v4l2_format */
341 static struct vpe_fmt *find_format(struct v4l2_format *f)
346 for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
347 fmt = &vpe_formats[k];
348 if (fmt->fourcc == f->fmt.pix.pixelformat)
356 * there is one vpe_dev structure in the driver, it is shared by
360 struct v4l2_device v4l2_dev;
361 struct video_device vfd;
362 struct v4l2_m2m_dev *m2m_dev;
364 atomic_t num_instances; /* count of driver instances */
365 dma_addr_t loaded_mmrs; /* shadow mmrs in device */
366 struct mutex dev_mutex;
371 struct resource *res;
373 struct vpdma_data vpdma_data;
374 struct vpdma_data *vpdma; /* vpdma data handle */
375 struct sc_data *sc; /* scaler data handle */
376 struct csc_data *csc; /* csc data handle */
380 * There is one vpe_ctx structure for each m2m context.
385 struct v4l2_ctrl_handler hdl;
387 unsigned int field; /* current field */
388 unsigned int sequence; /* current frame/field seq */
389 unsigned int aborting; /* abort after next irq */
391 unsigned int bufs_per_job; /* input buffers per batch */
392 unsigned int bufs_completed; /* bufs done in this batch */
394 struct vpe_q_data q_data[2]; /* src & dst queue data */
395 struct vb2_v4l2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
396 struct vb2_v4l2_buffer *dst_vb;
398 dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */
399 void *mv_buf[2]; /* virtual addrs of motion vector bufs */
400 size_t mv_buf_size; /* current motion vector buffer size */
401 struct vpdma_buf mmr_adb; /* shadow reg addr/data block */
402 struct vpdma_buf sc_coeff_h; /* h coeff buffer */
403 struct vpdma_buf sc_coeff_v; /* v coeff buffer */
404 struct vpdma_desc_list desc_list; /* DMA descriptor list */
406 bool deinterlacing; /* using de-interlacer */
407 bool load_mmrs; /* have new shadow reg values */
409 unsigned int src_mv_buf_selector;
414 * M2M devices get 2 queues.
415 * Return the queue given the type.
417 static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
418 enum v4l2_buf_type type)
421 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
422 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
423 return &ctx->q_data[Q_DATA_SRC];
424 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
425 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
426 return &ctx->q_data[Q_DATA_DST];
433 static u32 read_reg(struct vpe_dev *dev, int offset)
435 return ioread32(dev->base + offset);
438 static void write_reg(struct vpe_dev *dev, int offset, u32 value)
440 iowrite32(value, dev->base + offset);
443 /* register field read/write helpers */
444 static int get_field(u32 value, u32 mask, int shift)
446 return (value & (mask << shift)) >> shift;
449 static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
451 return get_field(read_reg(dev, offset), mask, shift);
454 static void write_field(u32 *valp, u32 field, u32 mask, int shift)
458 val &= ~(mask << shift);
459 val |= (field & mask) << shift;
463 static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
466 u32 val = read_reg(dev, offset);
468 write_field(&val, field, mask, shift);
470 write_reg(dev, offset, val);
474 * DMA address/data block for the shadow registers
477 struct vpdma_adb_hdr out_fmt_hdr;
480 struct vpdma_adb_hdr us1_hdr;
482 struct vpdma_adb_hdr us2_hdr;
484 struct vpdma_adb_hdr us3_hdr;
486 struct vpdma_adb_hdr dei_hdr;
488 struct vpdma_adb_hdr sc_hdr0;
491 struct vpdma_adb_hdr sc_hdr8;
494 struct vpdma_adb_hdr sc_hdr17;
497 struct vpdma_adb_hdr csc_hdr;
502 #define GET_OFFSET_TOP(ctx, obj, reg) \
503 ((obj)->res->start - ctx->dev->res->start + reg)
505 #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
506 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
508 * Set the headers for all of the address/data block structures.
510 static void init_adb_hdrs(struct vpe_ctx *ctx)
512 VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
513 VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
514 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
515 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
516 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
517 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
518 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
519 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
520 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
521 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
522 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
523 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
524 GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
528 * Allocate or re-allocate the motion vector DMA buffers
529 * There are two buffers, one for input and one for output.
530 * However, the roles are reversed after each field is processed.
531 * In other words, after each field is processed, the previous
532 * output (dst) MV buffer becomes the new input (src) MV buffer.
534 static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
536 struct device *dev = ctx->dev->v4l2_dev.dev;
538 if (ctx->mv_buf_size == size)
542 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
546 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
552 ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
554 if (!ctx->mv_buf[0]) {
555 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
559 ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
561 if (!ctx->mv_buf[1]) {
562 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
563 dma_free_coherent(dev, size, ctx->mv_buf[0],
569 ctx->mv_buf_size = size;
570 ctx->src_mv_buf_selector = 0;
575 static void free_mv_buffers(struct vpe_ctx *ctx)
577 realloc_mv_buffers(ctx, 0);
581 * While de-interlacing, we keep the two most recent input buffers
582 * around. This function frees those two buffers when we have
583 * finished processing the current stream.
585 static void free_vbs(struct vpe_ctx *ctx)
587 struct vpe_dev *dev = ctx->dev;
590 if (ctx->src_vbs[2] == NULL)
593 spin_lock_irqsave(&dev->lock, flags);
594 if (ctx->src_vbs[2]) {
595 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
596 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
597 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
598 ctx->src_vbs[2] = NULL;
599 ctx->src_vbs[1] = NULL;
601 spin_unlock_irqrestore(&dev->lock, flags);
605 * Enable or disable the VPE clocks
607 static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
612 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
613 write_reg(dev, VPE_CLK_ENABLE, val);
616 static void vpe_top_reset(struct vpe_dev *dev)
619 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
620 VPE_DATA_PATH_CLK_RESET_SHIFT);
622 usleep_range(100, 150);
624 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
625 VPE_DATA_PATH_CLK_RESET_SHIFT);
628 static void vpe_top_vpdma_reset(struct vpe_dev *dev)
630 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
631 VPE_VPDMA_CLK_RESET_SHIFT);
633 usleep_range(100, 150);
635 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
636 VPE_VPDMA_CLK_RESET_SHIFT);
640 * Load the correct of upsampler coefficients into the shadow MMRs
642 static void set_us_coefficients(struct vpe_ctx *ctx)
644 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
645 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
646 u32 *us1_reg = &mmr_adb->us1_regs[0];
647 u32 *us2_reg = &mmr_adb->us2_regs[0];
648 u32 *us3_reg = &mmr_adb->us3_regs[0];
649 const unsigned short *cp, *end_cp;
651 cp = &us_coeffs[0].anchor_fid0_c0;
653 if (s_q_data->flags & Q_IS_INTERLACED) /* interlaced */
654 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
656 end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
658 while (cp < end_cp) {
659 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
660 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
661 *us2_reg++ = *us1_reg;
662 *us3_reg++ = *us1_reg++;
664 ctx->load_mmrs = true;
668 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
670 static void set_cfg_modes(struct vpe_ctx *ctx)
672 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
673 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
674 u32 *us1_reg0 = &mmr_adb->us1_regs[0];
675 u32 *us2_reg0 = &mmr_adb->us2_regs[0];
676 u32 *us3_reg0 = &mmr_adb->us3_regs[0];
680 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
681 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
684 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
687 write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
688 write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
689 write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
691 ctx->load_mmrs = true;
694 static void set_line_modes(struct vpe_ctx *ctx)
696 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
699 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
700 line_mode = 0; /* double lines to line buffer */
703 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
704 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
705 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
707 /* frame start for input luma */
708 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
710 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
712 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
715 /* frame start for input chroma */
716 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
717 VPE_CHAN_CHROMA1_IN);
718 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
719 VPE_CHAN_CHROMA2_IN);
720 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
721 VPE_CHAN_CHROMA3_IN);
723 /* frame start for MV in client */
724 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
729 * Set the shadow registers that are modified when the source
732 static void set_src_registers(struct vpe_ctx *ctx)
734 set_us_coefficients(ctx);
738 * Set the shadow registers that are modified when the destination
741 static void set_dst_registers(struct vpe_ctx *ctx)
743 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
744 enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace;
745 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
748 if (clrspc == V4L2_COLORSPACE_SRGB) {
749 val |= VPE_RGB_OUT_SELECT;
750 vpdma_set_bg_color(ctx->dev->vpdma,
751 (struct vpdma_data_format *)fmt->vpdma_fmt[0], 0xff);
752 } else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
753 val |= VPE_COLOR_SEPARATE_422;
756 * the source of CHR_DS and CSC is always the scaler, irrespective of
757 * whether it's used or not
759 val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
761 if (fmt->fourcc != V4L2_PIX_FMT_NV12)
762 val |= VPE_DS_BYPASS;
764 mmr_adb->out_fmt_reg[0] = val;
766 ctx->load_mmrs = true;
770 * Set the de-interlacer shadow register values
772 static void set_dei_regs(struct vpe_ctx *ctx)
774 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
775 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
776 unsigned int src_h = s_q_data->c_rect.height;
777 unsigned int src_w = s_q_data->c_rect.width;
778 u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
779 bool deinterlace = true;
783 * according to TRM, we should set DEI in progressive bypass mode when
784 * the input content is progressive, however, DEI is bypassed correctly
785 * for both progressive and interlace content in interlace bypass mode.
786 * It has been recommended not to use progressive bypass mode.
788 if (!(s_q_data->flags & Q_IS_INTERLACED) || !ctx->deinterlacing) {
790 val = VPE_DEI_INTERLACE_BYPASS;
793 src_h = deinterlace ? src_h * 2 : src_h;
795 val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
796 (src_w << VPE_DEI_WIDTH_SHIFT) |
801 ctx->load_mmrs = true;
804 static void set_dei_shadow_registers(struct vpe_ctx *ctx)
806 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
807 u32 *dei_mmr = &mmr_adb->dei_regs[0];
808 const struct vpe_dei_regs *cur = &dei_regs;
810 dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
811 dei_mmr[3] = cur->edi_config_reg;
812 dei_mmr[4] = cur->edi_lut_reg0;
813 dei_mmr[5] = cur->edi_lut_reg1;
814 dei_mmr[6] = cur->edi_lut_reg2;
815 dei_mmr[7] = cur->edi_lut_reg3;
817 ctx->load_mmrs = true;
820 static void config_edi_input_mode(struct vpe_ctx *ctx, int mode)
822 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
823 u32 *edi_config_reg = &mmr_adb->dei_regs[3];
826 write_field(edi_config_reg, 1, 1, 2); /* EDI_ENABLE_3D */
829 write_field(edi_config_reg, 1, 1, 3); /* EDI_CHROMA_3D */
831 write_field(edi_config_reg, mode, VPE_EDI_INP_MODE_MASK,
832 VPE_EDI_INP_MODE_SHIFT);
834 ctx->load_mmrs = true;
838 * Set the shadow registers whose values are modified when either the
839 * source or destination format is changed.
841 static int set_srcdst_params(struct vpe_ctx *ctx)
843 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
844 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
845 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
846 unsigned int src_w = s_q_data->c_rect.width;
847 unsigned int src_h = s_q_data->c_rect.height;
848 unsigned int dst_w = d_q_data->c_rect.width;
849 unsigned int dst_h = d_q_data->c_rect.height;
854 ctx->field = V4L2_FIELD_TOP;
856 if ((s_q_data->flags & Q_IS_INTERLACED) &&
857 !(d_q_data->flags & Q_IS_INTERLACED)) {
859 const struct vpdma_data_format *mv =
860 &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
863 * we make sure that the source image has a 16 byte aligned
864 * stride, we need to do the same for the motion vector buffer
865 * by aligning it's stride to the next 16 byte boundary. this
866 * extra space will not be used by the de-interlacer, but will
867 * ensure that vpdma operates correctly
869 bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3,
871 mv_buf_size = bytes_per_line * s_q_data->height;
873 ctx->deinterlacing = true;
876 ctx->deinterlacing = false;
881 ctx->src_vbs[2] = ctx->src_vbs[1] = ctx->src_vbs[0] = NULL;
883 ret = realloc_mv_buffers(ctx, mv_buf_size);
890 csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
891 s_q_data->colorspace, d_q_data->colorspace);
893 sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
894 sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
896 sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
897 &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
898 src_w, src_h, dst_w, dst_h);
908 * job_ready() - check whether an instance is ready to be scheduled to run
910 static int job_ready(void *priv)
912 struct vpe_ctx *ctx = priv;
915 * This check is needed as this might be called directly from driver
916 * When called by m2m framework, this will always satisfy, but when
917 * called from vpe_irq, this might fail. (src stream with zero buffers)
919 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) <= 0 ||
920 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) <= 0)
926 static void job_abort(void *priv)
928 struct vpe_ctx *ctx = priv;
930 /* Will cancel the transaction in the next interrupt handler */
934 static void vpe_dump_regs(struct vpe_dev *dev)
936 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
938 vpe_dbg(dev, "VPE Registers:\n");
942 DUMPREG(INT0_STATUS0_RAW);
943 DUMPREG(INT0_STATUS0);
944 DUMPREG(INT0_ENABLE0);
945 DUMPREG(INT0_STATUS1_RAW);
946 DUMPREG(INT0_STATUS1);
947 DUMPREG(INT0_ENABLE1);
950 DUMPREG(CLK_FORMAT_SELECT);
951 DUMPREG(CLK_RANGE_MAP);
976 DUMPREG(DEI_FRAME_SIZE);
978 DUMPREG(MDT_SF_THRESHOLD);
980 DUMPREG(DEI_EDI_LUT_R0);
981 DUMPREG(DEI_EDI_LUT_R1);
982 DUMPREG(DEI_EDI_LUT_R2);
983 DUMPREG(DEI_EDI_LUT_R3);
984 DUMPREG(DEI_FMD_WINDOW_R0);
985 DUMPREG(DEI_FMD_WINDOW_R1);
986 DUMPREG(DEI_FMD_CONTROL_R0);
987 DUMPREG(DEI_FMD_CONTROL_R1);
988 DUMPREG(DEI_FMD_STATUS_R0);
989 DUMPREG(DEI_FMD_STATUS_R1);
990 DUMPREG(DEI_FMD_STATUS_R2);
993 sc_dump_regs(dev->sc);
994 csc_dump_regs(dev->csc);
997 static void add_out_dtd(struct vpe_ctx *ctx, int port)
999 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
1000 const struct vpe_port_data *p_data = &port_data[port];
1001 struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf;
1002 struct vpe_fmt *fmt = q_data->fmt;
1003 const struct vpdma_data_format *vpdma_fmt;
1004 int mv_buf_selector = !ctx->src_mv_buf_selector;
1005 dma_addr_t dma_addr;
1010 if (port == VPE_PORT_MV_OUT) {
1011 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1012 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1013 q_data = &ctx->q_data[Q_DATA_SRC];
1014 stride = ALIGN((q_data->width * vpdma_fmt->depth) >> 3,
1015 VPDMA_STRIDE_ALIGN);
1017 /* to incorporate interleaved formats */
1018 int plane = fmt->coplanar ? p_data->vb_part : 0;
1020 vpdma_fmt = fmt->vpdma_fmt[plane];
1022 * If we are using a single plane buffer and
1023 * we need to set a separate vpdma chroma channel.
1025 if (q_data->nplanes == 1 && plane) {
1026 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1027 /* Compute required offset */
1028 offset = q_data->bytesperline[0] * q_data->height;
1030 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1031 /* Use address as is, no offset */
1036 "acquiring output buffer(%d) dma_addr failed\n",
1040 /* Apply the offset */
1042 stride = q_data->bytesperline[VPE_LUMA];
1045 if (q_data->flags & Q_DATA_FRAME_1D)
1046 flags |= VPDMA_DATA_FRAME_1D;
1047 if (q_data->flags & Q_DATA_MODE_TILED)
1048 flags |= VPDMA_DATA_MODE_TILED;
1050 vpdma_set_max_size(ctx->dev->vpdma, VPDMA_MAX_SIZE1,
1053 vpdma_add_out_dtd(&ctx->desc_list, q_data->width,
1054 stride, &q_data->c_rect,
1055 vpdma_fmt, dma_addr, MAX_OUT_WIDTH_REG1,
1056 MAX_OUT_HEIGHT_REG1, p_data->channel, flags);
1059 static void add_in_dtd(struct vpe_ctx *ctx, int port)
1061 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1062 const struct vpe_port_data *p_data = &port_data[port];
1063 struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf;
1064 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1065 struct vpe_fmt *fmt = q_data->fmt;
1066 const struct vpdma_data_format *vpdma_fmt;
1067 int mv_buf_selector = ctx->src_mv_buf_selector;
1068 int field = vbuf->field == V4L2_FIELD_BOTTOM;
1069 int frame_width, frame_height;
1070 dma_addr_t dma_addr;
1075 if (port == VPE_PORT_MV_IN) {
1076 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1077 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1078 stride = ALIGN((q_data->width * vpdma_fmt->depth) >> 3,
1079 VPDMA_STRIDE_ALIGN);
1081 /* to incorporate interleaved formats */
1082 int plane = fmt->coplanar ? p_data->vb_part : 0;
1084 vpdma_fmt = fmt->vpdma_fmt[plane];
1086 * If we are using a single plane buffer and
1087 * we need to set a separate vpdma chroma channel.
1089 if (q_data->nplanes == 1 && plane) {
1090 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1091 /* Compute required offset */
1092 offset = q_data->bytesperline[0] * q_data->height;
1094 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1095 /* Use address as is, no offset */
1100 "acquiring output buffer(%d) dma_addr failed\n",
1104 /* Apply the offset */
1106 stride = q_data->bytesperline[VPE_LUMA];
1108 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB) {
1110 * Use top or bottom field from same vb alternately
1111 * f,f-1,f-2 = TBT when seq is even
1112 * f,f-1,f-2 = BTB when seq is odd
1114 field = (p_data->vb_index + (ctx->sequence % 2)) % 2;
1118 * bottom field of a SEQ_TB buffer
1119 * Skip the top field data by
1121 int height = q_data->height / 2;
1122 int bpp = fmt->fourcc == V4L2_PIX_FMT_NV12 ?
1123 1 : (vpdma_fmt->depth >> 3);
1126 dma_addr += q_data->width * height * bpp;
1131 if (q_data->flags & Q_DATA_FRAME_1D)
1132 flags |= VPDMA_DATA_FRAME_1D;
1133 if (q_data->flags & Q_DATA_MODE_TILED)
1134 flags |= VPDMA_DATA_MODE_TILED;
1136 frame_width = q_data->c_rect.width;
1137 frame_height = q_data->c_rect.height;
1139 if (p_data->vb_part && fmt->fourcc == V4L2_PIX_FMT_NV12)
1142 vpdma_add_in_dtd(&ctx->desc_list, q_data->width, stride,
1143 &q_data->c_rect, vpdma_fmt, dma_addr,
1144 p_data->channel, field, flags, frame_width,
1145 frame_height, 0, 0);
1149 * Enable the expected IRQ sources
1151 static void enable_irqs(struct vpe_ctx *ctx)
1153 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1154 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1155 VPE_DS1_UV_ERROR_INT);
1157 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, true);
1160 static void disable_irqs(struct vpe_ctx *ctx)
1162 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1163 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1165 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, false);
1168 /* device_run() - prepares and starts the device
1170 * This function is only called when both the source and destination
1171 * buffers are in place.
1173 static void device_run(void *priv)
1175 struct vpe_ctx *ctx = priv;
1176 struct sc_data *sc = ctx->dev->sc;
1177 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1178 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
1180 if (ctx->deinterlacing && s_q_data->flags & Q_DATA_INTERLACED_SEQ_TB &&
1181 ctx->sequence % 2 == 0) {
1182 /* When using SEQ_TB buffers, When using it first time,
1183 * No need to remove the buffer as the next field is present
1184 * in the same buffer. (so that job_ready won't fail)
1185 * It will be removed when using bottom field
1187 ctx->src_vbs[0] = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1188 WARN_ON(ctx->src_vbs[0] == NULL);
1190 ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1191 WARN_ON(ctx->src_vbs[0] == NULL);
1194 ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1195 WARN_ON(ctx->dst_vb == NULL);
1197 if (ctx->deinterlacing) {
1199 if (ctx->src_vbs[2] == NULL) {
1200 ctx->src_vbs[2] = ctx->src_vbs[0];
1201 WARN_ON(ctx->src_vbs[2] == NULL);
1202 ctx->src_vbs[1] = ctx->src_vbs[0];
1203 WARN_ON(ctx->src_vbs[1] == NULL);
1207 * we have output the first 2 frames through line average, we
1208 * now switch to EDI de-interlacer
1210 if (ctx->sequence == 2)
1211 config_edi_input_mode(ctx, 0x3); /* EDI (Y + UV) */
1214 /* config descriptors */
1215 if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1216 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1217 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1219 set_line_modes(ctx);
1221 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1222 ctx->load_mmrs = false;
1225 if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1227 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1228 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1229 &ctx->sc_coeff_h, 0);
1231 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1232 sc->load_coeff_h = false;
1235 if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1237 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1238 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1239 &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1241 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1242 sc->load_coeff_v = false;
1245 /* output data descriptors */
1246 if (ctx->deinterlacing)
1247 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1249 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1250 add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1252 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1253 if (d_q_data->fmt->coplanar)
1254 add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1257 /* input data descriptors */
1258 if (ctx->deinterlacing) {
1259 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1260 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1262 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1263 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1266 add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1267 add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1269 if (ctx->deinterlacing)
1270 add_in_dtd(ctx, VPE_PORT_MV_IN);
1272 /* sync on channel control descriptors for input ports */
1273 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1274 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1276 if (ctx->deinterlacing) {
1277 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1279 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1280 VPE_CHAN_CHROMA2_IN);
1282 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1284 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1285 VPE_CHAN_CHROMA3_IN);
1287 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1290 /* sync on channel control descriptors for output ports */
1291 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1292 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1295 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1297 if (d_q_data->fmt->coplanar)
1298 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1299 VPE_CHAN_CHROMA_OUT);
1302 if (ctx->deinterlacing)
1303 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1307 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1308 vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list, 0);
1311 static void dei_error(struct vpe_ctx *ctx)
1313 dev_warn(ctx->dev->v4l2_dev.dev,
1314 "received DEI error interrupt\n");
1317 static void ds1_uv_error(struct vpe_ctx *ctx)
1319 dev_warn(ctx->dev->v4l2_dev.dev,
1320 "received downsampler error interrupt\n");
1323 static irqreturn_t vpe_irq(int irq_vpe, void *data)
1325 struct vpe_dev *dev = (struct vpe_dev *)data;
1326 struct vpe_ctx *ctx;
1327 struct vpe_q_data *d_q_data;
1328 struct vb2_v4l2_buffer *s_vb, *d_vb;
1329 unsigned long flags;
1331 bool list_complete = false;
1333 irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1335 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1336 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1339 irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1341 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1342 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1345 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1347 vpe_err(dev, "instance released before end of transaction\n");
1352 if (irqst1 & VPE_DEI_ERROR_INT) {
1353 irqst1 &= ~VPE_DEI_ERROR_INT;
1356 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1357 irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1363 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1364 vpdma_clear_list_stat(ctx->dev->vpdma, 0, 0);
1366 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1367 list_complete = true;
1370 if (irqst0 | irqst1) {
1371 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1376 * Setup next operation only when list complete IRQ occurs
1377 * otherwise, skip the following code
1384 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1385 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1386 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1387 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1389 vpdma_reset_desc_list(&ctx->desc_list);
1391 /* the previous dst mv buffer becomes the next src mv buffer */
1392 ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1397 s_vb = ctx->src_vbs[0];
1400 d_vb->flags = s_vb->flags;
1401 d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp;
1403 if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE)
1404 d_vb->timecode = s_vb->timecode;
1406 d_vb->sequence = ctx->sequence;
1408 d_q_data = &ctx->q_data[Q_DATA_DST];
1409 if (d_q_data->flags & Q_IS_INTERLACED) {
1410 d_vb->field = ctx->field;
1411 if (ctx->field == V4L2_FIELD_BOTTOM) {
1413 ctx->field = V4L2_FIELD_TOP;
1415 WARN_ON(ctx->field != V4L2_FIELD_TOP);
1416 ctx->field = V4L2_FIELD_BOTTOM;
1419 d_vb->field = V4L2_FIELD_NONE;
1423 if (ctx->deinterlacing) {
1425 * Allow source buffer to be dequeued only if it won't be used
1426 * in the next iteration. All vbs are initialized to first
1427 * buffer and we are shifting buffers every iteration, for the
1428 * first two iterations, no buffer will be dequeued.
1429 * This ensures that driver will keep (n-2)th (n-1)th and (n)th
1430 * field when deinterlacing is enabled
1432 if (ctx->src_vbs[2] != ctx->src_vbs[1])
1433 s_vb = ctx->src_vbs[2];
1438 spin_lock_irqsave(&dev->lock, flags);
1441 v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1443 v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1445 spin_unlock_irqrestore(&dev->lock, flags);
1447 if (ctx->deinterlacing) {
1448 ctx->src_vbs[2] = ctx->src_vbs[1];
1449 ctx->src_vbs[1] = ctx->src_vbs[0];
1453 * Since the vb2_buf_done has already been called fir therse
1454 * buffer we can now NULL them out so that we won't try
1455 * to clean out stray pointer later on.
1457 ctx->src_vbs[0] = NULL;
1460 ctx->bufs_completed++;
1461 if (ctx->bufs_completed < ctx->bufs_per_job && job_ready(ctx)) {
1467 vpe_dbg(ctx->dev, "finishing transaction\n");
1468 ctx->bufs_completed = 0;
1469 v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
1477 static int vpe_querycap(struct file *file, void *priv,
1478 struct v4l2_capability *cap)
1480 strscpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver));
1481 strscpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card));
1482 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1487 static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1490 struct vpe_fmt *fmt = NULL;
1493 for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1494 if (vpe_formats[i].types & type) {
1495 if (index == f->index) {
1496 fmt = &vpe_formats[i];
1506 f->pixelformat = fmt->fourcc;
1510 static int vpe_enum_fmt(struct file *file, void *priv,
1511 struct v4l2_fmtdesc *f)
1513 if (V4L2_TYPE_IS_OUTPUT(f->type))
1514 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1516 return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1519 static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1521 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1522 struct vpe_ctx *ctx = file->private_data;
1523 struct vb2_queue *vq;
1524 struct vpe_q_data *q_data;
1527 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1531 q_data = get_q_data(ctx, f->type);
1535 pix->width = q_data->width;
1536 pix->height = q_data->height;
1537 pix->pixelformat = q_data->fmt->fourcc;
1538 pix->field = q_data->field;
1540 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1541 pix->colorspace = q_data->colorspace;
1543 struct vpe_q_data *s_q_data;
1545 /* get colorspace from the source queue */
1546 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1548 pix->colorspace = s_q_data->colorspace;
1551 pix->num_planes = q_data->nplanes;
1553 for (i = 0; i < pix->num_planes; i++) {
1554 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1555 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1561 static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1562 struct vpe_fmt *fmt, int type)
1564 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1565 struct v4l2_plane_pix_format *plane_fmt;
1566 unsigned int w_align;
1567 int i, depth, depth_bytes, height;
1568 unsigned int stride = 0;
1570 if (!fmt || !(fmt->types & type)) {
1571 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1576 if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE
1577 && pix->field != V4L2_FIELD_SEQ_TB)
1578 pix->field = V4L2_FIELD_NONE;
1580 depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1583 * the line stride should 16 byte aligned for VPDMA to work, based on
1584 * the bytes per pixel, figure out how much the width should be aligned
1585 * to make sure line stride is 16 byte aligned
1587 depth_bytes = depth >> 3;
1589 if (depth_bytes == 3) {
1591 * if bpp is 3(as in some RGB formats), the pixel width doesn't
1592 * really help in ensuring line stride is 16 byte aligned
1597 * for the remainder bpp(4, 2 and 1), the pixel width alignment
1598 * can ensure a line stride alignment of 16 bytes. For example,
1599 * if bpp is 2, then the line stride can be 16 byte aligned if
1600 * the width is 8 byte aligned
1604 * HACK: using order_base_2() here causes lots of asm output
1605 * errors with smatch, on i386:
1606 * ./arch/x86/include/asm/bitops.h:457:22:
1607 * warning: asm output is not an lvalue
1608 * Perhaps some gcc optimization is doing the wrong thing
1610 * Let's get rid of them by doing the calculus on two steps
1612 w_align = roundup_pow_of_two(VPDMA_DESC_ALIGN / depth_bytes);
1613 w_align = ilog2(w_align);
1616 v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1617 &pix->height, MIN_H, MAX_H, H_ALIGN,
1620 if (!pix->num_planes)
1621 pix->num_planes = fmt->coplanar ? 2 : 1;
1622 else if (pix->num_planes > 1 && !fmt->coplanar)
1623 pix->num_planes = 1;
1625 pix->pixelformat = fmt->fourcc;
1628 * For the actual image parameters, we need to consider the field
1629 * height of the image for SEQ_TB buffers.
1631 if (pix->field == V4L2_FIELD_SEQ_TB)
1632 height = pix->height / 2;
1634 height = pix->height;
1636 if (!pix->colorspace) {
1637 if (fmt->fourcc == V4L2_PIX_FMT_RGB24 ||
1638 fmt->fourcc == V4L2_PIX_FMT_BGR24 ||
1639 fmt->fourcc == V4L2_PIX_FMT_RGB32 ||
1640 fmt->fourcc == V4L2_PIX_FMT_BGR32) {
1641 pix->colorspace = V4L2_COLORSPACE_SRGB;
1643 if (height > 1280) /* HD */
1644 pix->colorspace = V4L2_COLORSPACE_REC709;
1646 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1650 memset(pix->reserved, 0, sizeof(pix->reserved));
1651 for (i = 0; i < pix->num_planes; i++) {
1652 plane_fmt = &pix->plane_fmt[i];
1653 depth = fmt->vpdma_fmt[i]->depth;
1655 stride = (pix->width * fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
1656 if (stride > plane_fmt->bytesperline)
1657 plane_fmt->bytesperline = stride;
1659 plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline,
1660 VPDMA_STRIDE_ALIGN);
1662 if (i == VPE_LUMA) {
1663 plane_fmt->sizeimage = pix->height *
1664 plane_fmt->bytesperline;
1666 if (pix->num_planes == 1 && fmt->coplanar)
1667 plane_fmt->sizeimage += pix->height *
1668 plane_fmt->bytesperline *
1669 fmt->vpdma_fmt[VPE_CHROMA]->depth >> 3;
1671 } else { /* i == VIP_CHROMA */
1672 plane_fmt->sizeimage = (pix->height *
1673 plane_fmt->bytesperline *
1676 memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
1682 static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1684 struct vpe_ctx *ctx = file->private_data;
1685 struct vpe_fmt *fmt = find_format(f);
1687 if (V4L2_TYPE_IS_OUTPUT(f->type))
1688 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1690 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1693 static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1695 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1696 struct v4l2_plane_pix_format *plane_fmt;
1697 struct vpe_q_data *q_data;
1698 struct vb2_queue *vq;
1701 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1705 if (vb2_is_busy(vq)) {
1706 vpe_err(ctx->dev, "queue busy\n");
1710 q_data = get_q_data(ctx, f->type);
1714 q_data->fmt = find_format(f);
1715 q_data->width = pix->width;
1716 q_data->height = pix->height;
1717 q_data->colorspace = pix->colorspace;
1718 q_data->field = pix->field;
1719 q_data->nplanes = pix->num_planes;
1721 for (i = 0; i < pix->num_planes; i++) {
1722 plane_fmt = &pix->plane_fmt[i];
1724 q_data->bytesperline[i] = plane_fmt->bytesperline;
1725 q_data->sizeimage[i] = plane_fmt->sizeimage;
1728 q_data->c_rect.left = 0;
1729 q_data->c_rect.top = 0;
1730 q_data->c_rect.width = q_data->width;
1731 q_data->c_rect.height = q_data->height;
1733 if (q_data->field == V4L2_FIELD_ALTERNATE)
1734 q_data->flags |= Q_DATA_INTERLACED_ALTERNATE;
1735 else if (q_data->field == V4L2_FIELD_SEQ_TB)
1736 q_data->flags |= Q_DATA_INTERLACED_SEQ_TB;
1738 q_data->flags &= ~Q_IS_INTERLACED;
1740 /* the crop height is halved for the case of SEQ_TB buffers */
1741 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1742 q_data->c_rect.height /= 2;
1744 vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1745 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1746 q_data->bytesperline[VPE_LUMA]);
1747 if (q_data->nplanes == 2)
1748 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1749 q_data->bytesperline[VPE_CHROMA]);
1754 static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1757 struct vpe_ctx *ctx = file->private_data;
1759 ret = vpe_try_fmt(file, priv, f);
1763 ret = __vpe_s_fmt(ctx, f);
1767 if (V4L2_TYPE_IS_OUTPUT(f->type))
1768 set_src_registers(ctx);
1770 set_dst_registers(ctx);
1772 return set_srcdst_params(ctx);
1775 static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1777 struct vpe_q_data *q_data;
1780 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1781 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1784 q_data = get_q_data(ctx, s->type);
1788 switch (s->target) {
1789 case V4L2_SEL_TGT_COMPOSE:
1791 * COMPOSE target is only valid for capture buffer type, return
1792 * error for output buffer type
1794 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1797 case V4L2_SEL_TGT_CROP:
1799 * CROP target is only valid for output buffer type, return
1800 * error for capture buffer type
1802 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1806 * bound and default crop/compose targets are invalid targets to
1814 * For SEQ_TB buffers, crop height should be less than the height of
1815 * the field height, not the buffer height
1817 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1818 height = q_data->height / 2;
1820 height = q_data->height;
1822 if (s->r.top < 0 || s->r.left < 0) {
1823 vpe_err(ctx->dev, "negative values for top and left\n");
1824 s->r.top = s->r.left = 0;
1827 v4l_bound_align_image(&s->r.width, MIN_W, q_data->width, 1,
1828 &s->r.height, MIN_H, height, H_ALIGN, S_ALIGN);
1830 /* adjust left/top if cropping rectangle is out of bounds */
1831 if (s->r.left + s->r.width > q_data->width)
1832 s->r.left = q_data->width - s->r.width;
1833 if (s->r.top + s->r.height > q_data->height)
1834 s->r.top = q_data->height - s->r.height;
1839 static int vpe_g_selection(struct file *file, void *fh,
1840 struct v4l2_selection *s)
1842 struct vpe_ctx *ctx = file->private_data;
1843 struct vpe_q_data *q_data;
1844 bool use_c_rect = false;
1846 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1847 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1850 q_data = get_q_data(ctx, s->type);
1854 switch (s->target) {
1855 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1856 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1857 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1860 case V4L2_SEL_TGT_CROP_BOUNDS:
1861 case V4L2_SEL_TGT_CROP_DEFAULT:
1862 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1865 case V4L2_SEL_TGT_COMPOSE:
1866 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1870 case V4L2_SEL_TGT_CROP:
1871 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1881 * for CROP/COMPOSE target type, return c_rect params from the
1882 * respective buffer type
1884 s->r = q_data->c_rect;
1887 * for DEFAULT/BOUNDS target type, return width and height from
1888 * S_FMT of the respective buffer type
1892 s->r.width = q_data->width;
1893 s->r.height = q_data->height;
1900 static int vpe_s_selection(struct file *file, void *fh,
1901 struct v4l2_selection *s)
1903 struct vpe_ctx *ctx = file->private_data;
1904 struct vpe_q_data *q_data;
1905 struct v4l2_selection sel = *s;
1908 ret = __vpe_try_selection(ctx, &sel);
1912 q_data = get_q_data(ctx, sel.type);
1916 if ((q_data->c_rect.left == sel.r.left) &&
1917 (q_data->c_rect.top == sel.r.top) &&
1918 (q_data->c_rect.width == sel.r.width) &&
1919 (q_data->c_rect.height == sel.r.height)) {
1921 "requested crop/compose values are already set\n");
1925 q_data->c_rect = sel.r;
1927 return set_srcdst_params(ctx);
1931 * defines number of buffers/frames a context can process with VPE before
1932 * switching to a different context. default value is 1 buffer per context
1934 #define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1936 static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1938 struct vpe_ctx *ctx =
1939 container_of(ctrl->handler, struct vpe_ctx, hdl);
1942 case V4L2_CID_VPE_BUFS_PER_JOB:
1943 ctx->bufs_per_job = ctrl->val;
1947 vpe_err(ctx->dev, "Invalid control\n");
1954 static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1955 .s_ctrl = vpe_s_ctrl,
1958 static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1959 .vidioc_querycap = vpe_querycap,
1961 .vidioc_enum_fmt_vid_cap = vpe_enum_fmt,
1962 .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
1963 .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
1964 .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
1966 .vidioc_enum_fmt_vid_out = vpe_enum_fmt,
1967 .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
1968 .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
1969 .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
1971 .vidioc_g_selection = vpe_g_selection,
1972 .vidioc_s_selection = vpe_s_selection,
1974 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1975 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1976 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1977 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1978 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
1979 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1980 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1982 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1983 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1989 static int vpe_queue_setup(struct vb2_queue *vq,
1990 unsigned int *nbuffers, unsigned int *nplanes,
1991 unsigned int sizes[], struct device *alloc_devs[])
1994 struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
1995 struct vpe_q_data *q_data;
1997 q_data = get_q_data(ctx, vq->type);
2001 *nplanes = q_data->nplanes;
2003 for (i = 0; i < *nplanes; i++)
2004 sizes[i] = q_data->sizeimage[i];
2006 vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
2008 if (q_data->nplanes == 2)
2009 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
2014 static int vpe_buf_prepare(struct vb2_buffer *vb)
2016 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2017 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2018 struct vpe_q_data *q_data;
2021 vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
2023 q_data = get_q_data(ctx, vb->vb2_queue->type);
2026 num_planes = q_data->nplanes;
2028 if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
2029 if (!(q_data->flags & Q_IS_INTERLACED)) {
2030 vbuf->field = V4L2_FIELD_NONE;
2032 if (vbuf->field != V4L2_FIELD_TOP &&
2033 vbuf->field != V4L2_FIELD_BOTTOM &&
2034 vbuf->field != V4L2_FIELD_SEQ_TB)
2039 for (i = 0; i < num_planes; i++) {
2040 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
2042 "data will not fit into plane (%lu < %lu)\n",
2043 vb2_plane_size(vb, i),
2044 (long) q_data->sizeimage[i]);
2049 for (i = 0; i < num_planes; i++)
2050 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
2055 static void vpe_buf_queue(struct vb2_buffer *vb)
2057 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2058 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2060 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
2063 static int check_srcdst_sizes(struct vpe_ctx *ctx)
2065 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
2066 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
2067 unsigned int src_w = s_q_data->c_rect.width;
2068 unsigned int src_h = s_q_data->c_rect.height;
2069 unsigned int dst_w = d_q_data->c_rect.width;
2070 unsigned int dst_h = d_q_data->c_rect.height;
2072 if (src_w == dst_w && src_h == dst_h)
2075 if (src_h <= SC_MAX_PIXEL_HEIGHT &&
2076 src_w <= SC_MAX_PIXEL_WIDTH &&
2077 dst_h <= SC_MAX_PIXEL_HEIGHT &&
2078 dst_w <= SC_MAX_PIXEL_WIDTH)
2084 static void vpe_return_all_buffers(struct vpe_ctx *ctx, struct vb2_queue *q,
2085 enum vb2_buffer_state state)
2087 struct vb2_v4l2_buffer *vb;
2088 unsigned long flags;
2091 if (V4L2_TYPE_IS_OUTPUT(q->type))
2092 vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
2094 vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2097 spin_lock_irqsave(&ctx->dev->lock, flags);
2098 v4l2_m2m_buf_done(vb, state);
2099 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2103 * Cleanup the in-transit vb2 buffers that have been
2104 * removed from their respective queue already but for
2105 * which procecessing has not been completed yet.
2107 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2108 spin_lock_irqsave(&ctx->dev->lock, flags);
2110 if (ctx->src_vbs[2])
2111 v4l2_m2m_buf_done(ctx->src_vbs[2], state);
2113 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
2114 v4l2_m2m_buf_done(ctx->src_vbs[1], state);
2116 if (ctx->src_vbs[0] &&
2117 (ctx->src_vbs[0] != ctx->src_vbs[1]) &&
2118 (ctx->src_vbs[0] != ctx->src_vbs[2]))
2119 v4l2_m2m_buf_done(ctx->src_vbs[0], state);
2121 ctx->src_vbs[2] = NULL;
2122 ctx->src_vbs[1] = NULL;
2123 ctx->src_vbs[0] = NULL;
2125 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2128 spin_lock_irqsave(&ctx->dev->lock, flags);
2130 v4l2_m2m_buf_done(ctx->dst_vb, state);
2132 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2137 static int vpe_start_streaming(struct vb2_queue *q, unsigned int count)
2139 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2141 /* Check any of the size exceed maximum scaling sizes */
2142 if (check_srcdst_sizes(ctx)) {
2144 "Conversion setup failed, check source and destination parameters\n"
2146 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_QUEUED);
2150 if (ctx->deinterlacing)
2151 config_edi_input_mode(ctx, 0x0);
2153 if (ctx->sequence != 0)
2154 set_srcdst_params(ctx);
2159 static void vpe_stop_streaming(struct vb2_queue *q)
2161 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2163 vpe_dump_regs(ctx->dev);
2164 vpdma_dump_regs(ctx->dev->vpdma);
2166 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_ERROR);
2169 static const struct vb2_ops vpe_qops = {
2170 .queue_setup = vpe_queue_setup,
2171 .buf_prepare = vpe_buf_prepare,
2172 .buf_queue = vpe_buf_queue,
2173 .wait_prepare = vb2_ops_wait_prepare,
2174 .wait_finish = vb2_ops_wait_finish,
2175 .start_streaming = vpe_start_streaming,
2176 .stop_streaming = vpe_stop_streaming,
2179 static int queue_init(void *priv, struct vb2_queue *src_vq,
2180 struct vb2_queue *dst_vq)
2182 struct vpe_ctx *ctx = priv;
2183 struct vpe_dev *dev = ctx->dev;
2186 memset(src_vq, 0, sizeof(*src_vq));
2187 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2188 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2189 src_vq->drv_priv = ctx;
2190 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2191 src_vq->ops = &vpe_qops;
2192 src_vq->mem_ops = &vb2_dma_contig_memops;
2193 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2194 src_vq->lock = &dev->dev_mutex;
2195 src_vq->dev = dev->v4l2_dev.dev;
2197 ret = vb2_queue_init(src_vq);
2201 memset(dst_vq, 0, sizeof(*dst_vq));
2202 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2203 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2204 dst_vq->drv_priv = ctx;
2205 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2206 dst_vq->ops = &vpe_qops;
2207 dst_vq->mem_ops = &vb2_dma_contig_memops;
2208 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2209 dst_vq->lock = &dev->dev_mutex;
2210 dst_vq->dev = dev->v4l2_dev.dev;
2212 return vb2_queue_init(dst_vq);
2215 static const struct v4l2_ctrl_config vpe_bufs_per_job = {
2216 .ops = &vpe_ctrl_ops,
2217 .id = V4L2_CID_VPE_BUFS_PER_JOB,
2218 .name = "Buffers Per Transaction",
2219 .type = V4L2_CTRL_TYPE_INTEGER,
2220 .def = VPE_DEF_BUFS_PER_JOB,
2222 .max = VIDEO_MAX_FRAME,
2229 static int vpe_open(struct file *file)
2231 struct vpe_dev *dev = video_drvdata(file);
2232 struct vpe_q_data *s_q_data;
2233 struct v4l2_ctrl_handler *hdl;
2234 struct vpe_ctx *ctx;
2237 vpe_dbg(dev, "vpe_open\n");
2239 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2245 if (mutex_lock_interruptible(&dev->dev_mutex)) {
2250 ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
2251 VPDMA_LIST_TYPE_NORMAL);
2255 ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
2257 goto free_desc_list;
2259 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
2263 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
2269 v4l2_fh_init(&ctx->fh, video_devdata(file));
2270 file->private_data = ctx;
2273 v4l2_ctrl_handler_init(hdl, 1);
2274 v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
2279 ctx->fh.ctrl_handler = hdl;
2280 v4l2_ctrl_handler_setup(hdl);
2282 s_q_data = &ctx->q_data[Q_DATA_SRC];
2283 s_q_data->fmt = &vpe_formats[2];
2284 s_q_data->width = 1920;
2285 s_q_data->height = 1080;
2286 s_q_data->nplanes = 1;
2287 s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width *
2288 s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2289 s_q_data->sizeimage[VPE_LUMA] = (s_q_data->bytesperline[VPE_LUMA] *
2291 s_q_data->colorspace = V4L2_COLORSPACE_REC709;
2292 s_q_data->field = V4L2_FIELD_NONE;
2293 s_q_data->c_rect.left = 0;
2294 s_q_data->c_rect.top = 0;
2295 s_q_data->c_rect.width = s_q_data->width;
2296 s_q_data->c_rect.height = s_q_data->height;
2297 s_q_data->flags = 0;
2299 ctx->q_data[Q_DATA_DST] = *s_q_data;
2301 set_dei_shadow_registers(ctx);
2302 set_src_registers(ctx);
2303 set_dst_registers(ctx);
2304 ret = set_srcdst_params(ctx);
2308 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2310 if (IS_ERR(ctx->fh.m2m_ctx)) {
2311 ret = PTR_ERR(ctx->fh.m2m_ctx);
2315 v4l2_fh_add(&ctx->fh);
2318 * for now, just report the creation of the first instance, we can later
2319 * optimize the driver to enable or disable clocks when the first
2320 * instance is created or the last instance released
2322 if (atomic_inc_return(&dev->num_instances) == 1)
2323 vpe_dbg(dev, "first instance created\n");
2325 ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2327 ctx->load_mmrs = true;
2329 vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2330 ctx, ctx->fh.m2m_ctx);
2332 mutex_unlock(&dev->dev_mutex);
2336 v4l2_ctrl_handler_free(hdl);
2337 v4l2_fh_exit(&ctx->fh);
2338 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2340 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2342 vpdma_free_desc_buf(&ctx->mmr_adb);
2344 vpdma_free_desc_list(&ctx->desc_list);
2346 mutex_unlock(&dev->dev_mutex);
2352 static int vpe_release(struct file *file)
2354 struct vpe_dev *dev = video_drvdata(file);
2355 struct vpe_ctx *ctx = file->private_data;
2357 vpe_dbg(dev, "releasing instance %p\n", ctx);
2359 mutex_lock(&dev->dev_mutex);
2360 free_mv_buffers(ctx);
2361 vpdma_free_desc_list(&ctx->desc_list);
2362 vpdma_free_desc_buf(&ctx->mmr_adb);
2364 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2365 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2367 v4l2_fh_del(&ctx->fh);
2368 v4l2_fh_exit(&ctx->fh);
2369 v4l2_ctrl_handler_free(&ctx->hdl);
2370 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2375 * for now, just report the release of the last instance, we can later
2376 * optimize the driver to enable or disable clocks when the first
2377 * instance is created or the last instance released
2379 if (atomic_dec_return(&dev->num_instances) == 0)
2380 vpe_dbg(dev, "last instance released\n");
2382 mutex_unlock(&dev->dev_mutex);
2387 static const struct v4l2_file_operations vpe_fops = {
2388 .owner = THIS_MODULE,
2390 .release = vpe_release,
2391 .poll = v4l2_m2m_fop_poll,
2392 .unlocked_ioctl = video_ioctl2,
2393 .mmap = v4l2_m2m_fop_mmap,
2396 static const struct video_device vpe_videodev = {
2397 .name = VPE_MODULE_NAME,
2399 .ioctl_ops = &vpe_ioctl_ops,
2401 .release = video_device_release_empty,
2402 .vfl_dir = VFL_DIR_M2M,
2403 .device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
2406 static const struct v4l2_m2m_ops m2m_ops = {
2407 .device_run = device_run,
2408 .job_ready = job_ready,
2409 .job_abort = job_abort,
2412 static int vpe_runtime_get(struct platform_device *pdev)
2416 dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2418 r = pm_runtime_get_sync(&pdev->dev);
2420 return r < 0 ? r : 0;
2423 static void vpe_runtime_put(struct platform_device *pdev)
2428 dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2430 r = pm_runtime_put_sync(&pdev->dev);
2431 WARN_ON(r < 0 && r != -ENOSYS);
2434 static void vpe_fw_cb(struct platform_device *pdev)
2436 struct vpe_dev *dev = platform_get_drvdata(pdev);
2437 struct video_device *vfd;
2441 *vfd = vpe_videodev;
2442 vfd->lock = &dev->dev_mutex;
2443 vfd->v4l2_dev = &dev->v4l2_dev;
2445 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2447 vpe_err(dev, "Failed to register video device\n");
2449 vpe_set_clock_enable(dev, 0);
2450 vpe_runtime_put(pdev);
2451 pm_runtime_disable(&pdev->dev);
2452 v4l2_m2m_release(dev->m2m_dev);
2453 v4l2_device_unregister(&dev->v4l2_dev);
2458 video_set_drvdata(vfd, dev);
2459 dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2463 static int vpe_probe(struct platform_device *pdev)
2465 struct vpe_dev *dev;
2468 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2472 spin_lock_init(&dev->lock);
2474 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2478 atomic_set(&dev->num_instances, 0);
2479 mutex_init(&dev->dev_mutex);
2481 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2484 dev_err(&pdev->dev, "missing 'vpe_top' resources data\n");
2489 * HACK: we get resource info from device tree in the form of a list of
2490 * VPE sub blocks, the driver currently uses only the base of vpe_top
2491 * for register access, the driver should be changed later to access
2492 * registers based on the sub block base addresses
2494 dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2497 goto v4l2_dev_unreg;
2500 irq = platform_get_irq(pdev, 0);
2501 ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2504 goto v4l2_dev_unreg;
2506 platform_set_drvdata(pdev, dev);
2508 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2509 if (IS_ERR(dev->m2m_dev)) {
2510 vpe_err(dev, "Failed to init mem2mem device\n");
2511 ret = PTR_ERR(dev->m2m_dev);
2512 goto v4l2_dev_unreg;
2515 pm_runtime_enable(&pdev->dev);
2517 ret = vpe_runtime_get(pdev);
2521 /* Perform clk enable followed by reset */
2522 vpe_set_clock_enable(dev, 1);
2526 func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2527 VPE_PID_FUNC_SHIFT);
2528 vpe_dbg(dev, "VPE PID function %x\n", func);
2530 vpe_top_vpdma_reset(dev);
2532 dev->sc = sc_create(pdev, "sc");
2533 if (IS_ERR(dev->sc)) {
2534 ret = PTR_ERR(dev->sc);
2538 dev->csc = csc_create(pdev, "csc");
2539 if (IS_ERR(dev->csc)) {
2540 ret = PTR_ERR(dev->csc);
2544 dev->vpdma = &dev->vpdma_data;
2545 ret = vpdma_create(pdev, dev->vpdma, vpe_fw_cb);
2552 vpe_runtime_put(pdev);
2554 pm_runtime_disable(&pdev->dev);
2555 v4l2_m2m_release(dev->m2m_dev);
2557 v4l2_device_unregister(&dev->v4l2_dev);
2562 static int vpe_remove(struct platform_device *pdev)
2564 struct vpe_dev *dev = platform_get_drvdata(pdev);
2566 v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2568 v4l2_m2m_release(dev->m2m_dev);
2569 video_unregister_device(&dev->vfd);
2570 v4l2_device_unregister(&dev->v4l2_dev);
2572 vpe_set_clock_enable(dev, 0);
2573 vpe_runtime_put(pdev);
2574 pm_runtime_disable(&pdev->dev);
2579 #if defined(CONFIG_OF)
2580 static const struct of_device_id vpe_of_match[] = {
2582 .compatible = "ti,vpe",
2586 MODULE_DEVICE_TABLE(of, vpe_of_match);
2589 static struct platform_driver vpe_pdrv = {
2591 .remove = vpe_remove,
2593 .name = VPE_MODULE_NAME,
2594 .of_match_table = of_match_ptr(vpe_of_match),
2598 module_platform_driver(vpe_pdrv);
2600 MODULE_DESCRIPTION("TI VPE driver");
2601 MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2602 MODULE_LICENSE("GPL");