1 // SPDX-License-Identifier: GPL-2.0+
3 * vsp1_drm.c -- R-Car VSP1 DRM/KMS Interface
5 * Copyright (C) 2015 Renesas Electronics Corporation
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/slab.h>
14 #include <media/media-entity.h>
15 #include <media/v4l2-subdev.h>
16 #include <media/vsp1.h>
23 #include "vsp1_pipe.h"
24 #include "vsp1_rwpf.h"
27 #define BRX_NAME(e) (e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
29 /* -----------------------------------------------------------------------------
33 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
34 unsigned int completion)
36 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
37 bool complete = completion & VSP1_DL_FRAME_END_COMPLETED;
39 if (drm_pipe->du_complete) {
40 struct vsp1_entity *uif = drm_pipe->uif;
43 crc = uif ? vsp1_uif_get_crc(to_uif(&uif->subdev)) : 0;
44 drm_pipe->du_complete(drm_pipe->du_private, complete, crc);
47 if (completion & VSP1_DL_FRAME_END_INTERNAL) {
48 drm_pipe->force_brx_release = false;
49 wake_up(&drm_pipe->wait_queue);
53 /* -----------------------------------------------------------------------------
54 * Pipeline Configuration
58 * Insert the UIF in the pipeline between the prev and next entities. If no UIF
59 * is available connect the two entities directly.
61 static int vsp1_du_insert_uif(struct vsp1_device *vsp1,
62 struct vsp1_pipeline *pipe,
63 struct vsp1_entity *uif,
64 struct vsp1_entity *prev, unsigned int prev_pad,
65 struct vsp1_entity *next, unsigned int next_pad)
67 struct v4l2_subdev_format format;
72 * If there's no UIF to be inserted, connect the previous and
73 * next entities directly.
76 prev->sink_pad = next_pad;
81 prev->sink_pad = UIF_PAD_SINK;
83 memset(&format, 0, sizeof(format));
84 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
85 format.pad = prev_pad;
87 ret = v4l2_subdev_call(&prev->subdev, pad, get_fmt, NULL, &format);
91 format.pad = UIF_PAD_SINK;
93 ret = v4l2_subdev_call(&uif->subdev, pad, set_fmt, NULL, &format);
97 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on UIF sink\n",
98 __func__, format.format.width, format.format.height,
102 * The UIF doesn't mangle the format between its sink and source pads,
103 * so there is no need to retrieve the format on its source pad.
107 uif->sink_pad = next_pad;
112 /* Setup one RPF and the connected BRx sink pad. */
113 static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
114 struct vsp1_pipeline *pipe,
115 struct vsp1_rwpf *rpf,
116 struct vsp1_entity *uif,
117 unsigned int brx_input)
119 struct v4l2_subdev_selection sel;
120 struct v4l2_subdev_format format;
121 const struct v4l2_rect *crop;
125 * Configure the format on the RPF sink pad and propagate it up to the
128 crop = &vsp1->drm->inputs[rpf->entity.index].crop;
130 memset(&format, 0, sizeof(format));
131 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
132 format.pad = RWPF_PAD_SINK;
133 format.format.width = crop->width + crop->left;
134 format.format.height = crop->height + crop->top;
135 format.format.code = rpf->fmtinfo->mbus;
136 format.format.field = V4L2_FIELD_NONE;
138 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
144 "%s: set format %ux%u (%x) on RPF%u sink\n",
145 __func__, format.format.width, format.format.height,
146 format.format.code, rpf->entity.index);
148 memset(&sel, 0, sizeof(sel));
149 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
150 sel.pad = RWPF_PAD_SINK;
151 sel.target = V4L2_SEL_TGT_CROP;
154 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
160 "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
161 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
165 * RPF source, hardcode the format to ARGB8888 to turn on format
166 * conversion if needed.
168 format.pad = RWPF_PAD_SOURCE;
170 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
176 "%s: got format %ux%u (%x) on RPF%u source\n",
177 __func__, format.format.width, format.format.height,
178 format.format.code, rpf->entity.index);
180 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
182 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
187 /* Insert and configure the UIF if available. */
188 ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE,
189 pipe->brx, brx_input);
193 /* BRx sink, propagate the format from the RPF source. */
194 format.pad = brx_input;
196 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
201 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
202 __func__, format.format.width, format.format.height,
203 format.format.code, BRX_NAME(pipe->brx), format.pad);
206 sel.target = V4L2_SEL_TGT_COMPOSE;
207 sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
209 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,
214 dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
215 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
216 BRX_NAME(pipe->brx), sel.pad);
221 /* Setup the BRx source pad. */
222 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
223 struct vsp1_pipeline *pipe);
224 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
226 static int vsp1_du_pipeline_setup_brx(struct vsp1_device *vsp1,
227 struct vsp1_pipeline *pipe)
229 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
230 struct v4l2_subdev_format format = {
231 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
233 struct vsp1_entity *brx;
238 * - If we need more than two inputs, use the BRU.
239 * - Otherwise, if we are not forced to release our BRx, keep it.
240 * - Else, use any free BRx (randomly starting with the BRU).
242 if (pipe->num_inputs > 2)
243 brx = &vsp1->bru->entity;
244 else if (pipe->brx && !drm_pipe->force_brx_release)
246 else if (!vsp1->bru->entity.pipe)
247 brx = &vsp1->bru->entity;
249 brx = &vsp1->brs->entity;
251 /* Switch BRx if needed. */
252 if (brx != pipe->brx) {
253 struct vsp1_entity *released_brx = NULL;
255 /* Release our BRx if we have one. */
257 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
258 __func__, pipe->lif->index,
259 BRX_NAME(pipe->brx));
262 * The BRx might be acquired by the other pipeline in
263 * the next step. We must thus remove it from the list
264 * of entities for this pipeline. The other pipeline's
265 * hardware configuration will reconfigure the BRx
268 * However, if the other pipeline doesn't acquire our
269 * BRx, we need to keep it in the list, otherwise the
270 * hardware configuration step won't disconnect it from
271 * the pipeline. To solve this, store the released BRx
272 * pointer to add it back to the list of entities later
273 * if it isn't acquired by the other pipeline.
275 released_brx = pipe->brx;
277 list_del(&pipe->brx->list_pipe);
278 pipe->brx->sink = NULL;
279 pipe->brx->pipe = NULL;
284 * If the BRx we need is in use, force the owner pipeline to
285 * switch to the other BRx and wait until the switch completes.
288 struct vsp1_drm_pipeline *owner_pipe;
290 dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
291 __func__, pipe->lif->index, BRX_NAME(brx));
293 owner_pipe = to_vsp1_drm_pipeline(brx->pipe);
294 owner_pipe->force_brx_release = true;
296 vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
297 vsp1_du_pipeline_configure(&owner_pipe->pipe);
299 ret = wait_event_timeout(owner_pipe->wait_queue,
300 !owner_pipe->force_brx_release,
301 msecs_to_jiffies(500));
304 "DRM pipeline %u reconfiguration timeout\n",
305 owner_pipe->pipe.lif->index);
309 * If the BRx we have released previously hasn't been acquired
310 * by the other pipeline, add it back to the entities list (with
311 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
312 * disconnect it from the hardware pipeline.
314 if (released_brx && !released_brx->pipe)
315 list_add_tail(&released_brx->list_pipe,
318 /* Add the BRx to the pipeline. */
319 dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
320 __func__, pipe->lif->index, BRX_NAME(brx));
323 pipe->brx->pipe = pipe;
324 pipe->brx->sink = &pipe->output->entity;
325 pipe->brx->sink_pad = 0;
327 list_add_tail(&pipe->brx->list_pipe, &pipe->entities);
331 * Configure the format on the BRx source and verify that it matches the
332 * requested format. We don't set the media bus code as it is configured
333 * on the BRx sink pad 0 and propagated inside the entity, not on the
336 format.pad = brx->source_pad;
337 format.format.width = drm_pipe->width;
338 format.format.height = drm_pipe->height;
339 format.format.field = V4L2_FIELD_NONE;
341 ret = v4l2_subdev_call(&brx->subdev, pad, set_fmt, NULL,
346 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
347 __func__, format.format.width, format.format.height,
348 format.format.code, BRX_NAME(brx), brx->source_pad);
350 if (format.format.width != drm_pipe->width ||
351 format.format.height != drm_pipe->height) {
352 dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
359 static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
361 return vsp1->drm->inputs[rpf->entity.index].zpos;
364 /* Setup the input side of the pipeline (RPFs and BRx). */
365 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
366 struct vsp1_pipeline *pipe)
368 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
369 struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
370 struct vsp1_entity *uif;
371 bool use_uif = false;
372 struct vsp1_brx *brx;
376 /* Count the number of enabled inputs and sort them by Z-order. */
377 pipe->num_inputs = 0;
379 for (i = 0; i < vsp1->info->rpf_count; ++i) {
380 struct vsp1_rwpf *rpf = vsp1->rpf[i];
383 if (!pipe->inputs[i])
386 /* Insert the RPF in the sorted RPFs array. */
387 for (j = pipe->num_inputs++; j > 0; --j) {
388 if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))
390 inputs[j] = inputs[j-1];
397 * Setup the BRx. This must be done before setting up the RPF input
398 * pipelines as the BRx sink compose rectangles depend on the BRx source
401 ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);
403 dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__,
404 BRX_NAME(pipe->brx));
408 brx = to_brx(&pipe->brx->subdev);
410 /* Setup the RPF input pipeline for every enabled input. */
411 for (i = 0; i < pipe->brx->source_pad; ++i) {
412 struct vsp1_rwpf *rpf = inputs[i];
415 brx->inputs[i].rpf = NULL;
419 if (!rpf->entity.pipe) {
420 rpf->entity.pipe = pipe;
421 list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
424 brx->inputs[i].rpf = rpf;
426 rpf->entity.sink = pipe->brx;
427 rpf->entity.sink_pad = i;
429 dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
430 __func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
432 uif = drm_pipe->crc.source == VSP1_DU_CRC_PLANE &&
433 drm_pipe->crc.index == i ? drm_pipe->uif : NULL;
436 ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, uif, i);
439 "%s: failed to setup RPF.%u\n",
440 __func__, rpf->entity.index);
445 /* Insert and configure the UIF at the BRx output if available. */
446 uif = drm_pipe->crc.source == VSP1_DU_CRC_OUTPUT ? drm_pipe->uif : NULL;
449 ret = vsp1_du_insert_uif(vsp1, pipe, uif,
450 pipe->brx, pipe->brx->source_pad,
451 &pipe->output->entity, 0);
453 dev_err(vsp1->dev, "%s: failed to setup UIF after %s\n",
454 __func__, BRX_NAME(pipe->brx));
457 * If the UIF is not in use schedule it for removal by setting its pipe
458 * pointer to NULL, vsp1_du_pipeline_configure() will remove it from the
459 * hardware pipeline and from the pipeline's list of entities. Otherwise
460 * make sure it is present in the pipeline's list of entities if it
464 drm_pipe->uif->pipe = NULL;
465 } else if (!drm_pipe->uif->pipe) {
466 drm_pipe->uif->pipe = pipe;
467 list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities);
473 /* Setup the output side of the pipeline (WPF and LIF). */
474 static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
475 struct vsp1_pipeline *pipe)
477 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
478 struct v4l2_subdev_format format = { 0, };
481 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
482 format.pad = RWPF_PAD_SINK;
483 format.format.width = drm_pipe->width;
484 format.format.height = drm_pipe->height;
485 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
486 format.format.field = V4L2_FIELD_NONE;
488 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
493 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
494 __func__, format.format.width, format.format.height,
495 format.format.code, pipe->output->entity.index);
497 format.pad = RWPF_PAD_SOURCE;
498 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
503 dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
504 __func__, format.format.width, format.format.height,
505 format.format.code, pipe->output->entity.index);
507 format.pad = LIF_PAD_SINK;
508 ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
513 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
514 __func__, format.format.width, format.format.height,
515 format.format.code, pipe->lif->index);
518 * Verify that the format at the output of the pipeline matches the
519 * requested frame size and media bus code.
521 if (format.format.width != drm_pipe->width ||
522 format.format.height != drm_pipe->height ||
523 format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
524 dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__,
532 /* Configure all entities in the pipeline. */
533 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
535 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
536 struct vsp1_entity *entity;
537 struct vsp1_entity *next;
538 struct vsp1_dl_list *dl;
539 struct vsp1_dl_body *dlb;
540 unsigned int dl_flags = 0;
542 if (drm_pipe->force_brx_release)
543 dl_flags |= VSP1_DL_FRAME_END_INTERNAL;
545 dl = vsp1_dl_list_get(pipe->output->dlm);
546 dlb = vsp1_dl_list_get_body0(dl);
548 list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
549 /* Disconnect unused entities from the pipeline. */
551 vsp1_dl_body_write(dlb, entity->route->reg,
552 VI6_DPR_NODE_UNUSED);
555 list_del(&entity->list_pipe);
560 vsp1_entity_route_setup(entity, pipe, dlb);
561 vsp1_entity_configure_stream(entity, pipe, dlb);
562 vsp1_entity_configure_frame(entity, pipe, dl, dlb);
563 vsp1_entity_configure_partition(entity, pipe, dl, dlb);
566 vsp1_dl_list_commit(dl, dl_flags);
569 /* -----------------------------------------------------------------------------
573 int vsp1_du_init(struct device *dev)
575 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
578 return -EPROBE_DEFER;
582 EXPORT_SYMBOL_GPL(vsp1_du_init);
585 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
586 * @dev: the VSP device
587 * @pipe_index: the DRM pipeline index
588 * @cfg: the LIF configuration
590 * Configure the output part of VSP DRM pipeline for the given frame @cfg.width
591 * and @cfg.height. This sets up formats on the BRx source pad, the WPF sink and
592 * source pads, and the LIF sink pad.
594 * The @pipe_index argument selects which DRM pipeline to setup. The number of
595 * available pipelines depend on the VSP instance.
597 * As the media bus code on the blend unit source pad is conditioned by the
598 * configuration of its sink 0 pad, we also set up the formats on all blend unit
599 * sinks, even if the configuration will be overwritten later by
600 * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is set to
601 * a well defined state.
603 * Return 0 on success or a negative error code on failure.
605 int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
606 const struct vsp1_du_lif_config *cfg)
608 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
609 struct vsp1_drm_pipeline *drm_pipe;
610 struct vsp1_pipeline *pipe;
615 if (pipe_index >= vsp1->info->lif_count)
618 drm_pipe = &vsp1->drm->pipe[pipe_index];
619 pipe = &drm_pipe->pipe;
622 struct vsp1_brx *brx;
624 mutex_lock(&vsp1->drm->lock);
626 brx = to_brx(&pipe->brx->subdev);
629 * NULL configuration means the CRTC is being disabled, stop
630 * the pipeline and turn the light off.
632 ret = vsp1_pipeline_stop(pipe);
633 if (ret == -ETIMEDOUT)
634 dev_err(vsp1->dev, "DRM pipeline stop timeout\n");
636 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
637 struct vsp1_rwpf *rpf = pipe->inputs[i];
643 * Remove the RPF from the pipe and the list of BRx
646 WARN_ON(!rpf->entity.pipe);
647 rpf->entity.pipe = NULL;
648 list_del(&rpf->entity.list_pipe);
649 pipe->inputs[i] = NULL;
651 brx->inputs[rpf->brx_input].rpf = NULL;
654 drm_pipe->du_complete = NULL;
655 pipe->num_inputs = 0;
657 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
658 __func__, pipe->lif->index,
659 BRX_NAME(pipe->brx));
661 list_del(&pipe->brx->list_pipe);
662 pipe->brx->pipe = NULL;
665 mutex_unlock(&vsp1->drm->lock);
667 vsp1_dlm_reset(pipe->output->dlm);
668 vsp1_device_put(vsp1);
670 dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);
675 drm_pipe->width = cfg->width;
676 drm_pipe->height = cfg->height;
677 pipe->interlaced = cfg->interlaced;
679 dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u%s\n",
680 __func__, pipe_index, cfg->width, cfg->height,
681 pipe->interlaced ? "i" : "");
683 mutex_lock(&vsp1->drm->lock);
685 /* Setup formats through the pipeline. */
686 ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
690 ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
694 /* Enable the VSP1. */
695 ret = vsp1_device_get(vsp1);
700 * Register a callback to allow us to notify the DRM driver of frame
703 drm_pipe->du_complete = cfg->callback;
704 drm_pipe->du_private = cfg->callback_data;
706 /* Disable the display interrupts. */
707 vsp1_write(vsp1, VI6_DISP_IRQ_STA(pipe_index), 0);
708 vsp1_write(vsp1, VI6_DISP_IRQ_ENB(pipe_index), 0);
710 /* Configure all entities in the pipeline. */
711 vsp1_du_pipeline_configure(pipe);
714 mutex_unlock(&vsp1->drm->lock);
719 /* Start the pipeline. */
720 spin_lock_irqsave(&pipe->irqlock, flags);
721 vsp1_pipeline_run(pipe);
722 spin_unlock_irqrestore(&pipe->irqlock, flags);
724 dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);
728 EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
731 * vsp1_du_atomic_begin - Prepare for an atomic update
732 * @dev: the VSP device
733 * @pipe_index: the DRM pipeline index
735 void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
738 EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
741 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
742 * @dev: the VSP device
743 * @pipe_index: the DRM pipeline index
744 * @rpf_index: index of the RPF to setup (0-based)
745 * @cfg: the RPF configuration
747 * Configure the VSP to perform image composition through RPF @rpf_index as
748 * described by the @cfg configuration. The image to compose is referenced by
749 * @cfg.mem and composed using the @cfg.src crop rectangle and the @cfg.dst
750 * composition rectangle. The Z-order is configurable with higher @zpos values
753 * If the @cfg configuration is NULL, the RPF will be disabled. Calling the
754 * function on a disabled RPF is allowed.
756 * Image format as stored in memory is expressed as a V4L2 @cfg.pixelformat
757 * value. The memory pitch is configurable to allow for padding at end of lines,
758 * or simply for images that extend beyond the crop rectangle boundaries. The
759 * @cfg.pitch value is expressed in bytes and applies to all planes for
760 * multiplanar formats.
762 * The source memory buffer is referenced by the DMA address of its planes in
763 * the @cfg.mem array. Up to two planes are supported. The second plane DMA
764 * address is ignored for formats using a single plane.
766 * This function isn't reentrant, the caller needs to serialize calls.
768 * Return 0 on success or a negative error code on failure.
770 int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
771 unsigned int rpf_index,
772 const struct vsp1_du_atomic_config *cfg)
774 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
775 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
776 const struct vsp1_format_info *fmtinfo;
777 unsigned int chroma_hsub;
778 struct vsp1_rwpf *rpf;
780 if (rpf_index >= vsp1->info->rpf_count)
783 rpf = vsp1->rpf[rpf_index];
786 dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
790 * Remove the RPF from the pipeline's inputs. Keep it in the
791 * pipeline's entity list to let vsp1_du_pipeline_configure()
792 * remove it from the hardware pipeline.
794 rpf->entity.pipe = NULL;
795 drm_pipe->pipe.inputs[rpf_index] = NULL;
800 "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad, %pad } zpos %u\n",
802 cfg->src.left, cfg->src.top, cfg->src.width, cfg->src.height,
803 cfg->dst.left, cfg->dst.top, cfg->dst.width, cfg->dst.height,
804 cfg->pixelformat, cfg->pitch, &cfg->mem[0], &cfg->mem[1],
805 &cfg->mem[2], cfg->zpos);
808 * Store the format, stride, memory buffer address, crop and compose
809 * rectangles and Z-order position and for the input.
811 fmtinfo = vsp1_get_format_info(vsp1, cfg->pixelformat);
813 dev_dbg(vsp1->dev, "Unsupported pixel format %08x for RPF\n",
819 * Only formats with three planes can affect the chroma planes pitch.
820 * All formats with two planes have a horizontal subsampling value of 2,
821 * but combine U and V in a single chroma plane, which thus results in
822 * the luma plane and chroma plane having the same pitch.
824 chroma_hsub = (fmtinfo->planes == 3) ? fmtinfo->hsub : 1;
826 rpf->fmtinfo = fmtinfo;
827 rpf->format.num_planes = fmtinfo->planes;
828 rpf->format.plane_fmt[0].bytesperline = cfg->pitch;
829 rpf->format.plane_fmt[1].bytesperline = cfg->pitch / chroma_hsub;
830 rpf->alpha = cfg->alpha;
832 rpf->mem.addr[0] = cfg->mem[0];
833 rpf->mem.addr[1] = cfg->mem[1];
834 rpf->mem.addr[2] = cfg->mem[2];
836 vsp1->drm->inputs[rpf_index].crop = cfg->src;
837 vsp1->drm->inputs[rpf_index].compose = cfg->dst;
838 vsp1->drm->inputs[rpf_index].zpos = cfg->zpos;
840 drm_pipe->pipe.inputs[rpf_index] = rpf;
844 EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
847 * vsp1_du_atomic_flush - Commit an atomic update
848 * @dev: the VSP device
849 * @pipe_index: the DRM pipeline index
850 * @cfg: atomic pipe configuration
852 void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
853 const struct vsp1_du_atomic_pipe_config *cfg)
855 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
856 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
857 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
859 drm_pipe->crc = cfg->crc;
861 mutex_lock(&vsp1->drm->lock);
862 vsp1_du_pipeline_setup_inputs(vsp1, pipe);
863 vsp1_du_pipeline_configure(pipe);
864 mutex_unlock(&vsp1->drm->lock);
866 EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
868 int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt)
870 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
873 * As all the buffers allocated by the DU driver are coherent, we can
874 * skip cache sync. This will need to be revisited when support for
875 * non-coherent buffers will be added to the DU driver.
877 return dma_map_sg_attrs(vsp1->bus_master, sgt->sgl, sgt->nents,
878 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
880 EXPORT_SYMBOL_GPL(vsp1_du_map_sg);
882 void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt)
884 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
886 dma_unmap_sg_attrs(vsp1->bus_master, sgt->sgl, sgt->nents,
887 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
889 EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg);
891 /* -----------------------------------------------------------------------------
895 int vsp1_drm_init(struct vsp1_device *vsp1)
899 vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
903 mutex_init(&vsp1->drm->lock);
905 /* Create one DRM pipeline per LIF. */
906 for (i = 0; i < vsp1->info->lif_count; ++i) {
907 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
908 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
910 init_waitqueue_head(&drm_pipe->wait_queue);
912 vsp1_pipeline_init(pipe);
914 pipe->frame_end = vsp1_du_pipeline_frame_end;
917 * The output side of the DRM pipeline is static, add the
918 * corresponding entities manually.
920 pipe->output = vsp1->wpf[i];
921 pipe->lif = &vsp1->lif[i]->entity;
923 pipe->output->entity.pipe = pipe;
924 pipe->output->entity.sink = pipe->lif;
925 pipe->output->entity.sink_pad = 0;
926 list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
928 pipe->lif->pipe = pipe;
929 list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
932 * CRC computation is initially disabled, don't add the UIF to
935 if (i < vsp1->info->uif_count)
936 drm_pipe->uif = &vsp1->uif[i]->entity;
939 /* Disable all RPFs initially. */
940 for (i = 0; i < vsp1->info->rpf_count; ++i) {
941 struct vsp1_rwpf *input = vsp1->rpf[i];
943 INIT_LIST_HEAD(&input->entity.list_pipe);
949 void vsp1_drm_cleanup(struct vsp1_device *vsp1)
951 mutex_destroy(&vsp1->drm->lock);