1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
9 #include <dt-bindings/memory/tegra124-mc.h>
13 #define MC_EMEM_ARB_CFG 0x90
14 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
15 #define MC_EMEM_ARB_TIMING_RCD 0x98
16 #define MC_EMEM_ARB_TIMING_RP 0x9c
17 #define MC_EMEM_ARB_TIMING_RC 0xa0
18 #define MC_EMEM_ARB_TIMING_RAS 0xa4
19 #define MC_EMEM_ARB_TIMING_FAW 0xa8
20 #define MC_EMEM_ARB_TIMING_RRD 0xac
21 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
22 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
23 #define MC_EMEM_ARB_TIMING_R2R 0xb8
24 #define MC_EMEM_ARB_TIMING_W2W 0xbc
25 #define MC_EMEM_ARB_TIMING_R2W 0xc0
26 #define MC_EMEM_ARB_TIMING_W2R 0xc4
27 #define MC_EMEM_ARB_DA_TURNS 0xd0
28 #define MC_EMEM_ARB_DA_COVERS 0xd4
29 #define MC_EMEM_ARB_MISC0 0xd8
30 #define MC_EMEM_ARB_MISC1 0xdc
31 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0
33 static const struct tegra_mc_client tegra124_mc_clients[] = {
37 .swgroup = TEGRA_SWGROUP_PTC,
41 .swgroup = TEGRA_SWGROUP_DC,
55 .swgroup = TEGRA_SWGROUP_DCB,
69 .swgroup = TEGRA_SWGROUP_DC,
83 .swgroup = TEGRA_SWGROUP_DCB,
97 .swgroup = TEGRA_SWGROUP_DC,
110 .name = "display0cb",
111 .swgroup = TEGRA_SWGROUP_DCB,
125 .swgroup = TEGRA_SWGROUP_AFI,
139 .swgroup = TEGRA_SWGROUP_AVPC,
153 .swgroup = TEGRA_SWGROUP_DC,
166 .name = "displayhcb",
167 .swgroup = TEGRA_SWGROUP_DCB,
181 .swgroup = TEGRA_SWGROUP_HDA,
194 .name = "host1xdmar",
195 .swgroup = TEGRA_SWGROUP_HC,
209 .swgroup = TEGRA_SWGROUP_HC,
223 .swgroup = TEGRA_SWGROUP_MSENC,
236 .name = "ppcsahbdmar",
237 .swgroup = TEGRA_SWGROUP_PPCS,
250 .name = "ppcsahbslvr",
251 .swgroup = TEGRA_SWGROUP_PPCS,
265 .swgroup = TEGRA_SWGROUP_SATA,
279 .swgroup = TEGRA_SWGROUP_VDE,
293 .swgroup = TEGRA_SWGROUP_VDE,
307 .swgroup = TEGRA_SWGROUP_VDE,
321 .swgroup = TEGRA_SWGROUP_VDE,
335 .swgroup = TEGRA_SWGROUP_MPCORELP,
345 .swgroup = TEGRA_SWGROUP_MPCORE,
355 .swgroup = TEGRA_SWGROUP_MSENC,
369 .swgroup = TEGRA_SWGROUP_AFI,
383 .swgroup = TEGRA_SWGROUP_AVPC,
397 .swgroup = TEGRA_SWGROUP_HDA,
411 .swgroup = TEGRA_SWGROUP_HC,
425 .swgroup = TEGRA_SWGROUP_MPCORELP,
435 .swgroup = TEGRA_SWGROUP_MPCORE,
444 .name = "ppcsahbdmaw",
445 .swgroup = TEGRA_SWGROUP_PPCS,
458 .name = "ppcsahbslvw",
459 .swgroup = TEGRA_SWGROUP_PPCS,
473 .swgroup = TEGRA_SWGROUP_SATA,
487 .swgroup = TEGRA_SWGROUP_VDE,
501 .swgroup = TEGRA_SWGROUP_VDE,
515 .swgroup = TEGRA_SWGROUP_VDE,
529 .swgroup = TEGRA_SWGROUP_VDE,
543 .swgroup = TEGRA_SWGROUP_ISP2,
557 .swgroup = TEGRA_SWGROUP_ISP2,
571 .swgroup = TEGRA_SWGROUP_ISP2,
584 .name = "xusb_hostr",
585 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
598 .name = "xusb_hostw",
599 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
613 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
627 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
641 .swgroup = TEGRA_SWGROUP_ISP2B,
655 .swgroup = TEGRA_SWGROUP_ISP2B,
669 .swgroup = TEGRA_SWGROUP_ISP2B,
683 .swgroup = TEGRA_SWGROUP_TSEC,
697 .swgroup = TEGRA_SWGROUP_TSEC,
711 .swgroup = TEGRA_SWGROUP_A9AVP,
725 .swgroup = TEGRA_SWGROUP_A9AVP,
739 .swgroup = TEGRA_SWGROUP_GPU,
754 .swgroup = TEGRA_SWGROUP_GPU,
769 .swgroup = TEGRA_SWGROUP_DC,
783 .swgroup = TEGRA_SWGROUP_SDMMC1A,
797 .swgroup = TEGRA_SWGROUP_SDMMC2A,
811 .swgroup = TEGRA_SWGROUP_SDMMC3A,
824 .swgroup = TEGRA_SWGROUP_SDMMC4A,
839 .swgroup = TEGRA_SWGROUP_SDMMC1A,
853 .swgroup = TEGRA_SWGROUP_SDMMC2A,
867 .swgroup = TEGRA_SWGROUP_SDMMC3A,
881 .swgroup = TEGRA_SWGROUP_SDMMC4A,
895 .swgroup = TEGRA_SWGROUP_VIC,
909 .swgroup = TEGRA_SWGROUP_VIC,
923 .swgroup = TEGRA_SWGROUP_VI,
937 .swgroup = TEGRA_SWGROUP_DC,
951 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
952 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
953 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
954 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
955 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
956 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
957 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
958 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
959 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
960 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
961 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
962 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
963 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
964 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
965 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
966 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
967 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
968 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
969 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
970 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
971 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
972 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
973 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
974 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
977 static const unsigned int tegra124_group_drm[] = {
984 static const struct tegra_smmu_group_soc tegra124_groups[] = {
987 .swgroups = tegra124_group_drm,
988 .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
992 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
995 .id = TEGRA124_MC_RESET_##_name, \
996 .control = _control, \
1001 static const struct tegra_mc_reset tegra124_mc_resets[] = {
1002 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
1003 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
1004 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
1005 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
1006 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
1007 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
1008 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
1009 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
1010 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1011 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
1012 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
1013 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1014 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1015 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1016 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1017 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1018 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1019 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1020 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1021 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1022 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1023 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1024 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1025 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1028 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1029 static const unsigned long tegra124_mc_emem_regs[] = {
1031 MC_EMEM_ARB_OUTSTANDING_REQ,
1032 MC_EMEM_ARB_TIMING_RCD,
1033 MC_EMEM_ARB_TIMING_RP,
1034 MC_EMEM_ARB_TIMING_RC,
1035 MC_EMEM_ARB_TIMING_RAS,
1036 MC_EMEM_ARB_TIMING_FAW,
1037 MC_EMEM_ARB_TIMING_RRD,
1038 MC_EMEM_ARB_TIMING_RAP2PRE,
1039 MC_EMEM_ARB_TIMING_WAP2PRE,
1040 MC_EMEM_ARB_TIMING_R2R,
1041 MC_EMEM_ARB_TIMING_W2W,
1042 MC_EMEM_ARB_TIMING_R2W,
1043 MC_EMEM_ARB_TIMING_W2R,
1044 MC_EMEM_ARB_DA_TURNS,
1045 MC_EMEM_ARB_DA_COVERS,
1048 MC_EMEM_ARB_RING1_THROTTLE
1051 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1052 .clients = tegra124_mc_clients,
1053 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1054 .swgroups = tegra124_swgroups,
1055 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1056 .groups = tegra124_groups,
1057 .num_groups = ARRAY_SIZE(tegra124_groups),
1058 .supports_round_robin_arbitration = true,
1059 .supports_request_limit = true,
1060 .num_tlb_lines = 32,
1064 const struct tegra_mc_soc tegra124_mc_soc = {
1065 .clients = tegra124_mc_clients,
1066 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1067 .num_address_bits = 34,
1069 .client_id_mask = 0x7f,
1070 .smmu = &tegra124_smmu_soc,
1071 .emem_regs = tegra124_mc_emem_regs,
1072 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1073 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1074 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1075 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1076 .reset_ops = &tegra_mc_reset_ops_common,
1077 .resets = tegra124_mc_resets,
1078 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1080 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1082 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1083 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1084 .clients = tegra124_mc_clients,
1085 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1086 .swgroups = tegra124_swgroups,
1087 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1088 .groups = tegra124_groups,
1089 .num_groups = ARRAY_SIZE(tegra124_groups),
1090 .supports_round_robin_arbitration = true,
1091 .supports_request_limit = true,
1092 .num_tlb_lines = 32,
1096 const struct tegra_mc_soc tegra132_mc_soc = {
1097 .clients = tegra124_mc_clients,
1098 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1099 .num_address_bits = 34,
1101 .client_id_mask = 0x7f,
1102 .smmu = &tegra132_smmu_soc,
1103 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1104 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1105 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1106 .reset_ops = &tegra_mc_reset_ops_common,
1107 .resets = tegra124_mc_resets,
1108 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1110 #endif /* CONFIG_ARCH_TEGRA_132_SOC */