2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #include <dt-bindings/memory/tegra124-mc.h>
16 #define MC_EMEM_ARB_CFG 0x90
17 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
18 #define MC_EMEM_ARB_TIMING_RCD 0x98
19 #define MC_EMEM_ARB_TIMING_RP 0x9c
20 #define MC_EMEM_ARB_TIMING_RC 0xa0
21 #define MC_EMEM_ARB_TIMING_RAS 0xa4
22 #define MC_EMEM_ARB_TIMING_FAW 0xa8
23 #define MC_EMEM_ARB_TIMING_RRD 0xac
24 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
25 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
26 #define MC_EMEM_ARB_TIMING_R2R 0xb8
27 #define MC_EMEM_ARB_TIMING_W2W 0xbc
28 #define MC_EMEM_ARB_TIMING_R2W 0xc0
29 #define MC_EMEM_ARB_TIMING_W2R 0xc4
30 #define MC_EMEM_ARB_DA_TURNS 0xd0
31 #define MC_EMEM_ARB_DA_COVERS 0xd4
32 #define MC_EMEM_ARB_MISC0 0xd8
33 #define MC_EMEM_ARB_MISC1 0xdc
34 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0
36 static const unsigned long tegra124_mc_emem_regs[] = {
38 MC_EMEM_ARB_OUTSTANDING_REQ,
39 MC_EMEM_ARB_TIMING_RCD,
40 MC_EMEM_ARB_TIMING_RP,
41 MC_EMEM_ARB_TIMING_RC,
42 MC_EMEM_ARB_TIMING_RAS,
43 MC_EMEM_ARB_TIMING_FAW,
44 MC_EMEM_ARB_TIMING_RRD,
45 MC_EMEM_ARB_TIMING_RAP2PRE,
46 MC_EMEM_ARB_TIMING_WAP2PRE,
47 MC_EMEM_ARB_TIMING_R2R,
48 MC_EMEM_ARB_TIMING_W2W,
49 MC_EMEM_ARB_TIMING_R2W,
50 MC_EMEM_ARB_TIMING_W2R,
52 MC_EMEM_ARB_DA_COVERS,
55 MC_EMEM_ARB_RING1_THROTTLE
58 static const struct tegra_mc_client tegra124_mc_clients[] = {
62 .swgroup = TEGRA_SWGROUP_PTC,
66 .swgroup = TEGRA_SWGROUP_DC,
80 .swgroup = TEGRA_SWGROUP_DCB,
94 .swgroup = TEGRA_SWGROUP_DC,
107 .name = "display0bb",
108 .swgroup = TEGRA_SWGROUP_DCB,
122 .swgroup = TEGRA_SWGROUP_DC,
135 .name = "display0cb",
136 .swgroup = TEGRA_SWGROUP_DCB,
150 .swgroup = TEGRA_SWGROUP_AFI,
164 .swgroup = TEGRA_SWGROUP_AVPC,
178 .swgroup = TEGRA_SWGROUP_DC,
191 .name = "displayhcb",
192 .swgroup = TEGRA_SWGROUP_DCB,
206 .swgroup = TEGRA_SWGROUP_HDA,
219 .name = "host1xdmar",
220 .swgroup = TEGRA_SWGROUP_HC,
234 .swgroup = TEGRA_SWGROUP_HC,
248 .swgroup = TEGRA_SWGROUP_MSENC,
261 .name = "ppcsahbdmar",
262 .swgroup = TEGRA_SWGROUP_PPCS,
275 .name = "ppcsahbslvr",
276 .swgroup = TEGRA_SWGROUP_PPCS,
290 .swgroup = TEGRA_SWGROUP_SATA,
304 .swgroup = TEGRA_SWGROUP_VDE,
318 .swgroup = TEGRA_SWGROUP_VDE,
332 .swgroup = TEGRA_SWGROUP_VDE,
346 .swgroup = TEGRA_SWGROUP_VDE,
360 .swgroup = TEGRA_SWGROUP_MPCORELP,
370 .swgroup = TEGRA_SWGROUP_MPCORE,
380 .swgroup = TEGRA_SWGROUP_MSENC,
394 .swgroup = TEGRA_SWGROUP_AFI,
408 .swgroup = TEGRA_SWGROUP_AVPC,
422 .swgroup = TEGRA_SWGROUP_HDA,
436 .swgroup = TEGRA_SWGROUP_HC,
450 .swgroup = TEGRA_SWGROUP_MPCORELP,
460 .swgroup = TEGRA_SWGROUP_MPCORE,
469 .name = "ppcsahbdmaw",
470 .swgroup = TEGRA_SWGROUP_PPCS,
483 .name = "ppcsahbslvw",
484 .swgroup = TEGRA_SWGROUP_PPCS,
498 .swgroup = TEGRA_SWGROUP_SATA,
512 .swgroup = TEGRA_SWGROUP_VDE,
526 .swgroup = TEGRA_SWGROUP_VDE,
540 .swgroup = TEGRA_SWGROUP_VDE,
554 .swgroup = TEGRA_SWGROUP_VDE,
568 .swgroup = TEGRA_SWGROUP_ISP2,
582 .swgroup = TEGRA_SWGROUP_ISP2,
596 .swgroup = TEGRA_SWGROUP_ISP2,
609 .name = "xusb_hostr",
610 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
623 .name = "xusb_hostw",
624 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
638 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
652 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
666 .swgroup = TEGRA_SWGROUP_ISP2B,
680 .swgroup = TEGRA_SWGROUP_ISP2B,
694 .swgroup = TEGRA_SWGROUP_ISP2B,
708 .swgroup = TEGRA_SWGROUP_TSEC,
722 .swgroup = TEGRA_SWGROUP_TSEC,
736 .swgroup = TEGRA_SWGROUP_A9AVP,
750 .swgroup = TEGRA_SWGROUP_A9AVP,
764 .swgroup = TEGRA_SWGROUP_GPU,
779 .swgroup = TEGRA_SWGROUP_GPU,
794 .swgroup = TEGRA_SWGROUP_DC,
808 .swgroup = TEGRA_SWGROUP_SDMMC1A,
822 .swgroup = TEGRA_SWGROUP_SDMMC2A,
836 .swgroup = TEGRA_SWGROUP_SDMMC3A,
849 .swgroup = TEGRA_SWGROUP_SDMMC4A,
864 .swgroup = TEGRA_SWGROUP_SDMMC1A,
878 .swgroup = TEGRA_SWGROUP_SDMMC2A,
892 .swgroup = TEGRA_SWGROUP_SDMMC3A,
906 .swgroup = TEGRA_SWGROUP_SDMMC4A,
920 .swgroup = TEGRA_SWGROUP_VIC,
934 .swgroup = TEGRA_SWGROUP_VIC,
948 .swgroup = TEGRA_SWGROUP_VI,
962 .swgroup = TEGRA_SWGROUP_DC,
976 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
977 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
978 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
979 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
980 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
981 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
982 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
983 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
984 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
985 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
986 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
987 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
988 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
989 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
990 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
991 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
992 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
993 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
994 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
995 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
996 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
997 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
998 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
999 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1002 static const unsigned int tegra124_group_display[] = {
1007 static const struct tegra_smmu_group_soc tegra124_groups[] = {
1010 .swgroups = tegra124_group_display,
1011 .num_swgroups = ARRAY_SIZE(tegra124_group_display),
1015 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
1018 .id = TEGRA124_MC_RESET_##_name, \
1019 .control = _control, \
1020 .status = _status, \
1024 static const struct tegra_mc_reset tegra124_mc_resets[] = {
1025 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
1026 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
1027 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
1028 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
1029 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
1030 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
1031 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
1032 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
1033 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1034 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
1035 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
1036 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1037 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1038 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1039 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1040 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1041 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1042 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1043 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1044 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1045 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1046 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1047 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1048 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1051 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1052 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1053 .clients = tegra124_mc_clients,
1054 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1055 .swgroups = tegra124_swgroups,
1056 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1057 .groups = tegra124_groups,
1058 .num_groups = ARRAY_SIZE(tegra124_groups),
1059 .supports_round_robin_arbitration = true,
1060 .supports_request_limit = true,
1061 .num_tlb_lines = 32,
1065 const struct tegra_mc_soc tegra124_mc_soc = {
1066 .clients = tegra124_mc_clients,
1067 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1068 .num_address_bits = 34,
1070 .client_id_mask = 0x7f,
1071 .smmu = &tegra124_smmu_soc,
1072 .emem_regs = tegra124_mc_emem_regs,
1073 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1074 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1075 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1076 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1077 .reset_ops = &terga_mc_reset_ops_common,
1078 .resets = tegra124_mc_resets,
1079 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1081 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1083 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1084 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1085 .clients = tegra124_mc_clients,
1086 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1087 .swgroups = tegra124_swgroups,
1088 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1089 .groups = tegra124_groups,
1090 .num_groups = ARRAY_SIZE(tegra124_groups),
1091 .supports_round_robin_arbitration = true,
1092 .supports_request_limit = true,
1093 .num_tlb_lines = 32,
1097 const struct tegra_mc_soc tegra132_mc_soc = {
1098 .clients = tegra124_mc_clients,
1099 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1100 .num_address_bits = 34,
1102 .client_id_mask = 0x7f,
1103 .smmu = &tegra132_smmu_soc,
1104 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1105 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1106 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1107 .reset_ops = &terga_mc_reset_ops_common,
1108 .resets = tegra124_mc_resets,
1109 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1111 #endif /* CONFIG_ARCH_TEGRA_132_SOC */