2 * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/memory/tegra210-mc.h>
13 static const struct tegra_mc_client tegra210_mc_clients[] = {
17 .swgroup = TEGRA_SWGROUP_PTC,
21 .swgroup = TEGRA_SWGROUP_DC,
35 .swgroup = TEGRA_SWGROUP_DCB,
49 .swgroup = TEGRA_SWGROUP_DC,
63 .swgroup = TEGRA_SWGROUP_DCB,
77 .swgroup = TEGRA_SWGROUP_DC,
91 .swgroup = TEGRA_SWGROUP_DCB,
105 .swgroup = TEGRA_SWGROUP_AFI,
119 .swgroup = TEGRA_SWGROUP_AVPC,
133 .swgroup = TEGRA_SWGROUP_DC,
146 .name = "displayhcb",
147 .swgroup = TEGRA_SWGROUP_DCB,
161 .swgroup = TEGRA_SWGROUP_HDA,
174 .name = "host1xdmar",
175 .swgroup = TEGRA_SWGROUP_HC,
189 .swgroup = TEGRA_SWGROUP_HC,
203 .swgroup = TEGRA_SWGROUP_NVENC,
216 .name = "ppcsahbdmar",
217 .swgroup = TEGRA_SWGROUP_PPCS,
230 .name = "ppcsahbslvr",
231 .swgroup = TEGRA_SWGROUP_PPCS,
245 .swgroup = TEGRA_SWGROUP_SATA,
259 .swgroup = TEGRA_SWGROUP_MPCORE,
269 .swgroup = TEGRA_SWGROUP_NVENC,
283 .swgroup = TEGRA_SWGROUP_AFI,
297 .swgroup = TEGRA_SWGROUP_AVPC,
311 .swgroup = TEGRA_SWGROUP_HDA,
325 .swgroup = TEGRA_SWGROUP_HC,
339 .swgroup = TEGRA_SWGROUP_MPCORE,
348 .name = "ppcsahbdmaw",
349 .swgroup = TEGRA_SWGROUP_PPCS,
362 .name = "ppcsahbslvw",
363 .swgroup = TEGRA_SWGROUP_PPCS,
377 .swgroup = TEGRA_SWGROUP_SATA,
391 .swgroup = TEGRA_SWGROUP_ISP2,
405 .swgroup = TEGRA_SWGROUP_ISP2,
419 .swgroup = TEGRA_SWGROUP_ISP2,
432 .name = "xusb_hostr",
433 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
446 .name = "xusb_hostw",
447 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
461 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
475 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
489 .swgroup = TEGRA_SWGROUP_ISP2B,
503 .swgroup = TEGRA_SWGROUP_ISP2B,
517 .swgroup = TEGRA_SWGROUP_ISP2B,
531 .swgroup = TEGRA_SWGROUP_TSEC,
545 .swgroup = TEGRA_SWGROUP_TSEC,
559 .swgroup = TEGRA_SWGROUP_A9AVP,
573 .swgroup = TEGRA_SWGROUP_A9AVP,
587 .swgroup = TEGRA_SWGROUP_GPU,
602 .swgroup = TEGRA_SWGROUP_GPU,
617 .swgroup = TEGRA_SWGROUP_DC,
631 .swgroup = TEGRA_SWGROUP_SDMMC1A,
645 .swgroup = TEGRA_SWGROUP_SDMMC2A,
659 .swgroup = TEGRA_SWGROUP_SDMMC3A,
672 .swgroup = TEGRA_SWGROUP_SDMMC4A,
687 .swgroup = TEGRA_SWGROUP_SDMMC1A,
701 .swgroup = TEGRA_SWGROUP_SDMMC2A,
715 .swgroup = TEGRA_SWGROUP_SDMMC3A,
729 .swgroup = TEGRA_SWGROUP_SDMMC4A,
743 .swgroup = TEGRA_SWGROUP_VIC,
757 .swgroup = TEGRA_SWGROUP_VIC,
771 .swgroup = TEGRA_SWGROUP_VI,
785 .swgroup = TEGRA_SWGROUP_DC,
799 .swgroup = TEGRA_SWGROUP_NVDEC,
813 .swgroup = TEGRA_SWGROUP_NVDEC,
827 .swgroup = TEGRA_SWGROUP_APE,
841 .swgroup = TEGRA_SWGROUP_APE,
855 .swgroup = TEGRA_SWGROUP_NVJPG,
869 .swgroup = TEGRA_SWGROUP_NVJPG,
883 .swgroup = TEGRA_SWGROUP_SE,
897 .swgroup = TEGRA_SWGROUP_SE,
911 .swgroup = TEGRA_SWGROUP_AXIAP,
925 .swgroup = TEGRA_SWGROUP_AXIAP,
939 .swgroup = TEGRA_SWGROUP_ETR,
953 .swgroup = TEGRA_SWGROUP_ETR,
967 .swgroup = TEGRA_SWGROUP_TSECB,
981 .swgroup = TEGRA_SWGROUP_TSECB,
995 .swgroup = TEGRA_SWGROUP_GPU,
1010 .swgroup = TEGRA_SWGROUP_GPU,
1025 static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1026 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1027 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1028 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1029 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1030 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1031 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1032 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1033 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1034 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1035 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1036 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1037 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1038 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1039 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1040 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1041 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1042 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1043 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1044 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1045 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1046 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1047 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1048 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1049 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1050 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1051 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1052 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1053 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1054 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1057 static const unsigned int tegra210_group_display[] = {
1062 static const struct tegra_smmu_group_soc tegra210_groups[] = {
1065 .swgroups = tegra210_group_display,
1066 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1070 static const struct tegra_smmu_soc tegra210_smmu_soc = {
1071 .clients = tegra210_mc_clients,
1072 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1073 .swgroups = tegra210_swgroups,
1074 .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1075 .groups = tegra210_groups,
1076 .num_groups = ARRAY_SIZE(tegra210_groups),
1077 .supports_round_robin_arbitration = true,
1078 .supports_request_limit = true,
1079 .num_tlb_lines = 32,
1083 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \
1086 .id = TEGRA210_MC_RESET_##_name, \
1087 .control = _control, \
1088 .status = _status, \
1092 static const struct tegra_mc_reset tegra210_mc_resets[] = {
1093 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1094 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1095 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1096 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1097 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1098 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1099 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1100 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1101 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1102 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1103 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1104 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1105 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1106 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1107 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1108 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1109 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1110 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1111 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1112 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1113 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1114 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1115 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1116 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1117 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1118 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1119 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1120 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1121 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1122 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1125 const struct tegra_mc_soc tegra210_mc_soc = {
1126 .clients = tegra210_mc_clients,
1127 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1128 .num_address_bits = 34,
1130 .client_id_mask = 0xff,
1131 .smmu = &tegra210_smmu_soc,
1132 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1133 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1134 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1135 .reset_ops = &terga_mc_reset_ops_common,
1136 .resets = tegra210_mc_resets,
1137 .num_resets = ARRAY_SIZE(tegra210_mc_resets),