drivers/memory/tegra/tegra30-emc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Tegra30 External Memory Controller driver
   4  *
   5  * Based on downstream driver from NVIDIA and tegra124-emc.c
   6  * Copyright (C) 2011-2014 NVIDIA Corporation
   7  *
   8  * Author: Dmitry Osipenko <digetx@gmail.com>
   9  * Copyright (C) 2019 GRATE-DRIVER project
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk/tegra.h>
  14 #include <linux/completion.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sort.h>
  26 #include <linux/types.h>
  27
  28 #include <soc/tegra/fuse.h>
  29
  30 #include "mc.h"
  31
  32 #define EMC_INTSTATUS                           0x000
  33 #define EMC_INTMASK                             0x004
  34 #define EMC_DBG                                 0x008
  35 #define EMC_CFG                                 0x00c
  36 #define EMC_REFCTRL                             0x020
  37 #define EMC_TIMING_CONTROL                      0x028
  38 #define EMC_RC                                  0x02c
  39 #define EMC_RFC                                 0x030
  40 #define EMC_RAS                                 0x034
  41 #define EMC_RP                                  0x038
  42 #define EMC_R2W                                 0x03c
  43 #define EMC_W2R                                 0x040
  44 #define EMC_R2P                                 0x044
  45 #define EMC_W2P                                 0x048
  46 #define EMC_RD_RCD                              0x04c
  47 #define EMC_WR_RCD                              0x050
  48 #define EMC_RRD                                 0x054
  49 #define EMC_REXT                                0x058
  50 #define EMC_WDV                                 0x05c
  51 #define EMC_QUSE                                0x060
  52 #define EMC_QRST                                0x064
  53 #define EMC_QSAFE                               0x068
  54 #define EMC_RDV                                 0x06c
  55 #define EMC_REFRESH                             0x070
  56 #define EMC_BURST_REFRESH_NUM                   0x074
  57 #define EMC_PDEX2WR                             0x078
  58 #define EMC_PDEX2RD                             0x07c
  59 #define EMC_PCHG2PDEN                           0x080
  60 #define EMC_ACT2PDEN                            0x084
  61 #define EMC_AR2PDEN                             0x088
  62 #define EMC_RW2PDEN                             0x08c
  63 #define EMC_TXSR                                0x090
  64 #define EMC_TCKE                                0x094
  65 #define EMC_TFAW                                0x098
  66 #define EMC_TRPAB                               0x09c
  67 #define EMC_TCLKSTABLE                          0x0a0
  68 #define EMC_TCLKSTOP                            0x0a4
  69 #define EMC_TREFBW                              0x0a8
  70 #define EMC_QUSE_EXTRA                          0x0ac
  71 #define EMC_ODT_WRITE                           0x0b0
  72 #define EMC_ODT_READ                            0x0b4
  73 #define EMC_WEXT                                0x0b8
  74 #define EMC_CTT                                 0x0bc
  75 #define EMC_MRS_WAIT_CNT                        0x0c8
  76 #define EMC_MRS                                 0x0cc
  77 #define EMC_EMRS                                0x0d0
  78 #define EMC_SELF_REF                            0x0e0
  79 #define EMC_MRW                                 0x0e8
  80 #define EMC_XM2DQSPADCTRL3                      0x0f8
  81 #define EMC_FBIO_SPARE                          0x100
  82 #define EMC_FBIO_CFG5                           0x104
  83 #define EMC_FBIO_CFG6                           0x114
  84 #define EMC_CFG_RSV                             0x120
  85 #define EMC_AUTO_CAL_CONFIG                     0x2a4
  86 #define EMC_AUTO_CAL_INTERVAL                   0x2a8
  87 #define EMC_AUTO_CAL_STATUS                     0x2ac
  88 #define EMC_STATUS                              0x2b4
  89 #define EMC_CFG_2                               0x2b8
  90 #define EMC_CFG_DIG_DLL                         0x2bc
  91 #define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
  92 #define EMC_CTT_DURATION                        0x2d8
  93 #define EMC_CTT_TERM_CTRL                       0x2dc
  94 #define EMC_ZCAL_INTERVAL                       0x2e0
  95 #define EMC_ZCAL_WAIT_CNT                       0x2e4
  96 #define EMC_ZQ_CAL                              0x2ec
  97 #define EMC_XM2CMDPADCTRL                       0x2f0
  98 #define EMC_XM2DQSPADCTRL2                      0x2fc
  99 #define EMC_XM2DQPADCTRL2                       0x304
 100 #define EMC_XM2CLKPADCTRL                       0x308
 101 #define EMC_XM2COMPPADCTRL                      0x30c
 102 #define EMC_XM2VTTGENPADCTRL                    0x310
 103 #define EMC_XM2VTTGENPADCTRL2                   0x314
 104 #define EMC_XM2QUSEPADCTRL                      0x318
 105 #define EMC_DLL_XFORM_DQS0                      0x328
 106 #define EMC_DLL_XFORM_DQS1                      0x32c
 107 #define EMC_DLL_XFORM_DQS2                      0x330
 108 #define EMC_DLL_XFORM_DQS3                      0x334
 109 #define EMC_DLL_XFORM_DQS4                      0x338
 110 #define EMC_DLL_XFORM_DQS5                      0x33c
 111 #define EMC_DLL_XFORM_DQS6                      0x340
 112 #define EMC_DLL_XFORM_DQS7                      0x344
 113 #define EMC_DLL_XFORM_QUSE0                     0x348
 114 #define EMC_DLL_XFORM_QUSE1                     0x34c
 115 #define EMC_DLL_XFORM_QUSE2                     0x350
 116 #define EMC_DLL_XFORM_QUSE3                     0x354
 117 #define EMC_DLL_XFORM_QUSE4                     0x358
 118 #define EMC_DLL_XFORM_QUSE5                     0x35c
 119 #define EMC_DLL_XFORM_QUSE6                     0x360
 120 #define EMC_DLL_XFORM_QUSE7                     0x364
 121 #define EMC_DLL_XFORM_DQ0                       0x368
 122 #define EMC_DLL_XFORM_DQ1                       0x36c
 123 #define EMC_DLL_XFORM_DQ2                       0x370
 124 #define EMC_DLL_XFORM_DQ3                       0x374
 125 #define EMC_DLI_TRIM_TXDQS0                     0x3a8
 126 #define EMC_DLI_TRIM_TXDQS1                     0x3ac
 127 #define EMC_DLI_TRIM_TXDQS2                     0x3b0
 128 #define EMC_DLI_TRIM_TXDQS3                     0x3b4
 129 #define EMC_DLI_TRIM_TXDQS4                     0x3b8
 130 #define EMC_DLI_TRIM_TXDQS5                     0x3bc
 131 #define EMC_DLI_TRIM_TXDQS6                     0x3c0
 132 #define EMC_DLI_TRIM_TXDQS7                     0x3c4
 133 #define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE     0x3c8
 134 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE      0x3cc
 135 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE          0x3d0
 136 #define EMC_SEL_DPD_CTRL                        0x3d8
 137 #define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
 138 #define EMC_DYN_SELF_REF_CONTROL                0x3e0
 139 #define EMC_TXSRDLL                             0x3e4
 140
 141 #define EMC_STATUS_TIMING_UPDATE_STALLED        BIT(23)
 142
 143 #define EMC_MODE_SET_DLL_RESET                  BIT(8)
 144 #define EMC_MODE_SET_LONG_CNT                   BIT(26)
 145
 146 #define EMC_SELF_REF_CMD_ENABLED                BIT(0)
 147
 148 #define DRAM_DEV_SEL_ALL                        (0 << 30)
 149 #define DRAM_DEV_SEL_0                          (2 << 30)
 150 #define DRAM_DEV_SEL_1                          (1 << 30)
 151 #define DRAM_BROADCAST(num) \
 152         ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
 153
 154 #define EMC_ZQ_CAL_CMD                          BIT(0)
 155 #define EMC_ZQ_CAL_LONG                         BIT(4)
 156 #define EMC_ZQ_CAL_LONG_CMD_DEV0 \
 157         (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
 158 #define EMC_ZQ_CAL_LONG_CMD_DEV1 \
 159         (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
 160
 161 #define EMC_DBG_READ_MUX_ASSEMBLY               BIT(0)
 162 #define EMC_DBG_WRITE_MUX_ACTIVE                BIT(1)
 163 #define EMC_DBG_FORCE_UPDATE                    BIT(2)
 164 #define EMC_DBG_CFG_PRIORITY                    BIT(24)
 165
 166 #define EMC_CFG5_QUSE_MODE_SHIFT                13
 167 #define EMC_CFG5_QUSE_MODE_MASK                 (7 << EMC_CFG5_QUSE_MODE_SHIFT)
 168
 169 #define EMC_CFG5_QUSE_MODE_INTERNAL_LPBK        2
 170 #define EMC_CFG5_QUSE_MODE_PULSE_INTERN         3
 171
 172 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE        BIT(9)
 173
 174 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      BIT(10)
 175
 176 #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE         BIT(4)
 177
 178 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE          BIT(5)
 179 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE          BIT(5)
 180
 181 #define EMC_AUTO_CAL_STATUS_ACTIVE              BIT(31)
 182
 183 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK            0x3
 184
 185 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        0x3ff
 186 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
 187 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
 188         (0x3ff << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
 189
 190 #define EMC_REFCTRL_DEV_SEL_MASK                0x3
 191 #define EMC_REFCTRL_ENABLE                      BIT(31)
 192 #define EMC_REFCTRL_ENABLE_ALL(num) \
 193         (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
 194 #define EMC_REFCTRL_DISABLE_ALL(num)            ((num) > 1 ? 0 : 2)
 195
 196 #define EMC_CFG_PERIODIC_QRST                   BIT(21)
 197 #define EMC_CFG_DYN_SREF_ENABLE                 BIT(28)
 198
 199 #define EMC_CLKCHANGE_REQ_ENABLE                BIT(0)
 200 #define EMC_CLKCHANGE_PD_ENABLE                 BIT(1)
 201 #define EMC_CLKCHANGE_SR_ENABLE                 BIT(2)
 202
 203 #define EMC_TIMING_UPDATE                       BIT(0)
 204
 205 #define EMC_REFRESH_OVERFLOW_INT                BIT(3)
 206 #define EMC_CLKCHANGE_COMPLETE_INT              BIT(4)
 207
 208 enum emc_dram_type {
 209         DRAM_TYPE_DDR3,
 210         DRAM_TYPE_DDR1,
 211         DRAM_TYPE_LPDDR2,
 212         DRAM_TYPE_DDR2,
 213 };
 214
 215 enum emc_dll_change {
 216         DLL_CHANGE_NONE,
 217         DLL_CHANGE_ON,
 218         DLL_CHANGE_OFF
 219 };
 220
 221 static const u16 emc_timing_registers[] = {
 222         [0] = EMC_RC,
 223         [1] = EMC_RFC,
 224         [2] = EMC_RAS,
 225         [3] = EMC_RP,
 226         [4] = EMC_R2W,
 227         [5] = EMC_W2R,
 228         [6] = EMC_R2P,
 229         [7] = EMC_W2P,
 230         [8] = EMC_RD_RCD,
 231         [9] = EMC_WR_RCD,
 232         [10] = EMC_RRD,
 233         [11] = EMC_REXT,
 234         [12] = EMC_WEXT,
 235         [13] = EMC_WDV,
 236         [14] = EMC_QUSE,
 237         [15] = EMC_QRST,
 238         [16] = EMC_QSAFE,
 239         [17] = EMC_RDV,
 240         [18] = EMC_REFRESH,
 241         [19] = EMC_BURST_REFRESH_NUM,
 242         [20] = EMC_PRE_REFRESH_REQ_CNT,
 243         [21] = EMC_PDEX2WR,
 244         [22] = EMC_PDEX2RD,
 245         [23] = EMC_PCHG2PDEN,
 246         [24] = EMC_ACT2PDEN,
 247         [25] = EMC_AR2PDEN,
 248         [26] = EMC_RW2PDEN,
 249         [27] = EMC_TXSR,
 250         [28] = EMC_TXSRDLL,
 251         [29] = EMC_TCKE,
 252         [30] = EMC_TFAW,
 253         [31] = EMC_TRPAB,
 254         [32] = EMC_TCLKSTABLE,
 255         [33] = EMC_TCLKSTOP,
 256         [34] = EMC_TREFBW,
 257         [35] = EMC_QUSE_EXTRA,
 258         [36] = EMC_FBIO_CFG6,
 259         [37] = EMC_ODT_WRITE,
 260         [38] = EMC_ODT_READ,
 261         [39] = EMC_FBIO_CFG5,
 262         [40] = EMC_CFG_DIG_DLL,
 263         [41] = EMC_CFG_DIG_DLL_PERIOD,
 264         [42] = EMC_DLL_XFORM_DQS0,
 265         [43] = EMC_DLL_XFORM_DQS1,
 266         [44] = EMC_DLL_XFORM_DQS2,
 267         [45] = EMC_DLL_XFORM_DQS3,
 268         [46] = EMC_DLL_XFORM_DQS4,
 269         [47] = EMC_DLL_XFORM_DQS5,
 270         [48] = EMC_DLL_XFORM_DQS6,
 271         [49] = EMC_DLL_XFORM_DQS7,
 272         [50] = EMC_DLL_XFORM_QUSE0,
 273         [51] = EMC_DLL_XFORM_QUSE1,
 274         [52] = EMC_DLL_XFORM_QUSE2,
 275         [53] = EMC_DLL_XFORM_QUSE3,
 276         [54] = EMC_DLL_XFORM_QUSE4,
 277         [55] = EMC_DLL_XFORM_QUSE5,
 278         [56] = EMC_DLL_XFORM_QUSE6,
 279         [57] = EMC_DLL_XFORM_QUSE7,
 280         [58] = EMC_DLI_TRIM_TXDQS0,
 281         [59] = EMC_DLI_TRIM_TXDQS1,
 282         [60] = EMC_DLI_TRIM_TXDQS2,
 283         [61] = EMC_DLI_TRIM_TXDQS3,
 284         [62] = EMC_DLI_TRIM_TXDQS4,
 285         [63] = EMC_DLI_TRIM_TXDQS5,
 286         [64] = EMC_DLI_TRIM_TXDQS6,
 287         [65] = EMC_DLI_TRIM_TXDQS7,
 288         [66] = EMC_DLL_XFORM_DQ0,
 289         [67] = EMC_DLL_XFORM_DQ1,
 290         [68] = EMC_DLL_XFORM_DQ2,
 291         [69] = EMC_DLL_XFORM_DQ3,
 292         [70] = EMC_XM2CMDPADCTRL,
 293         [71] = EMC_XM2DQSPADCTRL2,
 294         [72] = EMC_XM2DQPADCTRL2,
 295         [73] = EMC_XM2CLKPADCTRL,
 296         [74] = EMC_XM2COMPPADCTRL,
 297         [75] = EMC_XM2VTTGENPADCTRL,
 298         [76] = EMC_XM2VTTGENPADCTRL2,
 299         [77] = EMC_XM2QUSEPADCTRL,
 300         [78] = EMC_XM2DQSPADCTRL3,
 301         [79] = EMC_CTT_TERM_CTRL,
 302         [80] = EMC_ZCAL_INTERVAL,
 303         [81] = EMC_ZCAL_WAIT_CNT,
 304         [82] = EMC_MRS_WAIT_CNT,
 305         [83] = EMC_AUTO_CAL_CONFIG,
 306         [84] = EMC_CTT,
 307         [85] = EMC_CTT_DURATION,
 308         [86] = EMC_DYN_SELF_REF_CONTROL,
 309         [87] = EMC_FBIO_SPARE,
 310         [88] = EMC_CFG_RSV,
 311 };
 312
 313 struct emc_timing {
 314         unsigned long rate;
 315
 316         u32 data[ARRAY_SIZE(emc_timing_registers)];
 317
 318         u32 emc_auto_cal_interval;
 319         u32 emc_mode_1;
 320         u32 emc_mode_2;
 321         u32 emc_mode_reset;
 322         u32 emc_zcal_cnt_long;
 323         bool emc_cfg_periodic_qrst;
 324         bool emc_cfg_dyn_self_ref;
 325 };
 326
 327 struct tegra_emc {
 328         struct device *dev;
 329         struct tegra_mc *mc;
 330         struct completion clk_handshake_complete;
 331         struct notifier_block clk_nb;
 332         struct clk *clk;
 333         void __iomem *regs;
 334         unsigned int irq;
 335         bool bad_state;
 336
 337         struct emc_timing *new_timing;
 338         struct emc_timing *timings;
 339         unsigned int num_timings;
 340
 341         u32 mc_override;
 342         u32 emc_cfg;
 343
 344         u32 emc_mode_1;
 345         u32 emc_mode_2;
 346         u32 emc_mode_reset;
 347
 348         bool vref_cal_toggle : 1;
 349         bool zcal_long : 1;
 350         bool dll_on : 1;
 351
 352         struct {
 353                 struct dentry *root;
 354                 unsigned long min_rate;
 355                 unsigned long max_rate;
 356         } debugfs;
 357 };
 358
 359 static int emc_seq_update_timing(struct tegra_emc *emc)
 360 {
 361         u32 val;
 362         int err;
 363
 364         writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
 365
 366         err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val,
 367                                 !(val & EMC_STATUS_TIMING_UPDATE_STALLED),
 368                                 1, 200);
 369         if (err) {
 370                 dev_err(emc->dev, "failed to update timing: %d\n", err);
 371                 return err;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static void emc_complete_clk_change(struct tegra_emc *emc)
 378 {
 379         struct emc_timing *timing = emc->new_timing;
 380         unsigned int dram_num;
 381         bool failed = false;
 382         int err;
 383
 384         /* re-enable auto-refresh */
 385         dram_num = tegra_mc_get_emem_device_count(emc->mc);
 386         writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num),
 387                        emc->regs + EMC_REFCTRL);
 388
 389         /* restore auto-calibration */
 390         if (emc->vref_cal_toggle)
 391                 writel_relaxed(timing->emc_auto_cal_interval,
 392                                emc->regs + EMC_AUTO_CAL_INTERVAL);
 393
 394         /* restore dynamic self-refresh */
 395         if (timing->emc_cfg_dyn_self_ref) {
 396                 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
 397                 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
 398         }
 399
 400         /* set number of clocks to wait after each ZQ command */
 401         if (emc->zcal_long)
 402                 writel_relaxed(timing->emc_zcal_cnt_long,
 403                                emc->regs + EMC_ZCAL_WAIT_CNT);
 404
 405         /* wait for writes to settle */
 406         udelay(2);
 407
 408         /* update restored timing */
 409         err = emc_seq_update_timing(emc);
 410         if (err)
 411                 failed = true;
 412
 413         /* restore early ACK */
 414         mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
 415
 416         WRITE_ONCE(emc->bad_state, failed);
 417 }
 418
 419 static irqreturn_t tegra_emc_isr(int irq, void *data)
 420 {
 421         struct tegra_emc *emc = data;
 422         u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
 423         u32 status;
 424
 425         status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
 426         if (!status)
 427                 return IRQ_NONE;
 428
 429         /* notify about HW problem */
 430         if (status & EMC_REFRESH_OVERFLOW_INT)
 431                 dev_err_ratelimited(emc->dev,
 432                                     "refresh request overflow timeout\n");
 433
 434         /* clear interrupts */
 435         writel_relaxed(status, emc->regs + EMC_INTSTATUS);
 436
 437         /* notify about EMC-CAR handshake completion */
 438         if (status & EMC_CLKCHANGE_COMPLETE_INT) {
 439                 if (completion_done(&emc->clk_handshake_complete)) {
 440                         dev_err_ratelimited(emc->dev,
 441                                             "bogus handshake interrupt\n");
 442                         return IRQ_NONE;
 443                 }
 444
 445                 emc_complete_clk_change(emc);
 446                 complete(&emc->clk_handshake_complete);
 447         }
 448
 449         return IRQ_HANDLED;
 450 }
 451
 452 static struct emc_timing *emc_find_timing(struct tegra_emc *emc,
 453                                           unsigned long rate)
 454 {
 455         struct emc_timing *timing = NULL;
 456         unsigned int i;
 457
 458         for (i = 0; i < emc->num_timings; i++) {
 459                 if (emc->timings[i].rate >= rate) {
 460                         timing = &emc->timings[i];
 461                         break;
 462                 }
 463         }
 464
 465         if (!timing) {
 466                 dev_err(emc->dev, "no timing for rate %lu\n", rate);
 467                 return NULL;
 468         }
 469
 470         return timing;
 471 }
 472
 473 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
 474                            bool *schmitt_to_vref)
 475 {
 476         bool preset = false;
 477         u32 val;
 478
 479         if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) {
 480                 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2);
 481
 482                 if (!(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
 483                         val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
 484                         writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
 485
 486                         preset = true;
 487                 }
 488         }
 489
 490         if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) {
 491                 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3);
 492
 493                 if (!(val & EMC_XM2DQSPADCTRL3_VREF_ENABLE)) {
 494                         val |= EMC_XM2DQSPADCTRL3_VREF_ENABLE;
 495                         writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
 496
 497                         preset = true;
 498                 }
 499         }
 500
 501         if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) {
 502                 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL);
 503
 504                 if (!(val & EMC_XM2QUSEPADCTRL_IVREF_ENABLE)) {
 505                         val |= EMC_XM2QUSEPADCTRL_IVREF_ENABLE;
 506                         writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
 507
 508                         *schmitt_to_vref = true;
 509                         preset = true;
 510                 }
 511         }
 512
 513         return preset;
 514 }
 515
 516 static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate)
 517 {
 518         struct tegra_mc *mc = emc->mc;
 519         unsigned int misc0_index = 16;
 520         unsigned int i;
 521         bool same;
 522
 523         for (i = 0; i < mc->num_timings; i++) {
 524                 if (mc->timings[i].rate != rate)
 525                         continue;
 526
 527                 if (mc->timings[i].emem_data[misc0_index] & BIT(27))
 528                         same = true;
 529                 else
 530                         same = false;
 531
 532                 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same);
 533         }
 534
 535         return -EINVAL;
 536 }
 537
 538 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
 539 {
 540         struct emc_timing *timing = emc_find_timing(emc, rate);
 541         enum emc_dll_change dll_change;
 542         enum emc_dram_type dram_type;
 543         bool schmitt_to_vref = false;
 544         unsigned int pre_wait = 0;
 545         bool qrst_used = false;
 546         unsigned int dram_num;
 547         unsigned int i;
 548         u32 fbio_cfg5;
 549         u32 emc_dbg;
 550         u32 val;
 551         int err;
 552
 553         if (!timing || emc->bad_state)
 554                 return -EINVAL;
 555
 556         dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
 557                 __func__, timing->rate, rate);
 558
 559         emc->bad_state = true;
 560
 561         err = emc_prepare_mc_clk_cfg(emc, rate);
 562         if (err) {
 563                 dev_err(emc->dev, "mc clock preparation failed: %d\n", err);
 564                 return err;
 565         }
 566
 567         emc->vref_cal_toggle = false;
 568         emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
 569         emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG);
 570         emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
 571
 572         if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
 573                 dll_change = DLL_CHANGE_NONE;
 574         else if (timing->emc_mode_1 & 0x1)
 575                 dll_change = DLL_CHANGE_ON;
 576         else
 577                 dll_change = DLL_CHANGE_OFF;
 578
 579         emc->dll_on = !!(timing->emc_mode_1 & 0x1);
 580
 581         if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
 582                 emc->zcal_long = true;
 583         else
 584                 emc->zcal_long = false;
 585
 586         fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
 587         dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
 588
 589         dram_num = tegra_mc_get_emem_device_count(emc->mc);
 590
 591         /* disable dynamic self-refresh */
 592         if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
 593                 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE;
 594                 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
 595
 596                 pre_wait = 5;
 597         }
 598
 599         /* update MC arbiter settings */
 600         val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ);
 601         if (!(val & MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE) ||
 602             ((val & MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK) > 0x50)) {
 603
 604                 val = MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE |
 605                       MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE | 0x50;
 606                 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ);
 607                 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
 608         }
 609
 610         if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK)
 611                 mc_writel(emc->mc,
 612                           emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK,
 613                           MC_EMEM_ARB_OVERRIDE);
 614
 615         /* check DQ/DQS VREF delay */
 616         if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
 617                 if (pre_wait < 3)
 618                         pre_wait = 3;
 619         }
 620
 621         if (pre_wait) {
 622                 err = emc_seq_update_timing(emc);
 623                 if (err)
 624                         return err;
 625
 626                 udelay(pre_wait);
 627         }
 628
 629         /* disable auto-calibration if VREF mode is switching */
 630         if (timing->emc_auto_cal_interval) {
 631                 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL);
 632                 val ^= timing->data[74];
 633
 634                 if (val & EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE) {
 635                         writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
 636
 637                         err = readl_relaxed_poll_timeout_atomic(
 638                                 emc->regs + EMC_AUTO_CAL_STATUS, val,
 639                                 !(val & EMC_AUTO_CAL_STATUS_ACTIVE), 1, 300);
 640                         if (err) {
 641                                 dev_err(emc->dev,
 642                                         "auto-cal finish timeout: %d\n", err);
 643                                 return err;
 644                         }
 645
 646                         emc->vref_cal_toggle = true;
 647                 }
 648         }
 649
 650         /* program shadow registers */
 651         for (i = 0; i < ARRAY_SIZE(timing->data); i++) {
 652                 /* EMC_XM2CLKPADCTRL should be programmed separately */
 653                 if (i != 73)
 654                         writel_relaxed(timing->data[i],
 655                                        emc->regs + emc_timing_registers[i]);
 656         }
 657
 658         err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
 659         if (err)
 660                 return err;
 661
 662         /* DDR3: predict MRS long wait count */
 663         if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) {
 664                 u32 cnt = 512;
 665
 666                 if (emc->zcal_long)
 667                         cnt -= dram_num * 256;
 668
 669                 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK;
 670                 if (cnt < val)
 671                         cnt = val;
 672
 673                 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
 674                 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) &
 675                         EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
 676
 677                 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
 678         }
 679
 680         /* this read also completes the writes */
 681         val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL);
 682
 683         if (!(val & EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE) && schmitt_to_vref) {
 684                 u32 cur_mode, new_mode;
 685
 686                 cur_mode = fbio_cfg5 & EMC_CFG5_QUSE_MODE_MASK;
 687                 cur_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
 688
 689                 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK;
 690                 new_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
 691
 692                 if ((cur_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
 693                      cur_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK) ||
 694                     (new_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
 695                      new_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK))
 696                         qrst_used = true;
 697         }
 698
 699         /* flow control marker 1 */
 700         writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE);
 701
 702         /* enable periodic reset */
 703         if (qrst_used) {
 704                 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
 705                                emc->regs + EMC_DBG);
 706                 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,
 707                                emc->regs + EMC_CFG);
 708                 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
 709         }
 710
 711         /* disable auto-refresh to save time after clock change */
 712         writel_relaxed(EMC_REFCTRL_DISABLE_ALL(dram_num),
 713                        emc->regs + EMC_REFCTRL);
 714
 715         /* turn off DLL and enter self-refresh on DDR3 */
 716         if (dram_type == DRAM_TYPE_DDR3) {
 717                 if (dll_change == DLL_CHANGE_OFF)
 718                         writel_relaxed(timing->emc_mode_1,
 719                                        emc->regs + EMC_EMRS);
 720
 721                 writel_relaxed(DRAM_BROADCAST(dram_num) |
 722                                EMC_SELF_REF_CMD_ENABLED,
 723                                emc->regs + EMC_SELF_REF);
 724         }
 725
 726         /* flow control marker 2 */
 727         writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
 728
 729         /* enable write-active MUX, update unshadowed pad control */
 730         writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG);
 731         writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
 732
 733         /* restore periodic QRST and disable write-active MUX */
 734         val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST);
 735         if (qrst_used || timing->emc_cfg_periodic_qrst != val) {
 736                 if (timing->emc_cfg_periodic_qrst)
 737                         emc->emc_cfg |= EMC_CFG_PERIODIC_QRST;
 738                 else
 739                         emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST;
 740
 741                 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
 742         }
 743         writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
 744
 745         /* exit self-refresh on DDR3 */
 746         if (dram_type == DRAM_TYPE_DDR3)
 747                 writel_relaxed(DRAM_BROADCAST(dram_num),
 748                                emc->regs + EMC_SELF_REF);
 749
 750         /* set DRAM-mode registers */
 751         if (dram_type == DRAM_TYPE_DDR3) {
 752                 if (timing->emc_mode_1 != emc->emc_mode_1)
 753                         writel_relaxed(timing->emc_mode_1,
 754                                        emc->regs + EMC_EMRS);
 755
 756                 if (timing->emc_mode_2 != emc->emc_mode_2)
 757                         writel_relaxed(timing->emc_mode_2,
 758                                        emc->regs + EMC_EMRS);
 759
 760                 if (timing->emc_mode_reset != emc->emc_mode_reset ||
 761                     dll_change == DLL_CHANGE_ON) {
 762                         val = timing->emc_mode_reset;
 763                         if (dll_change == DLL_CHANGE_ON) {
 764                                 val |= EMC_MODE_SET_DLL_RESET;
 765                                 val |= EMC_MODE_SET_LONG_CNT;
 766                         } else {
 767                                 val &= ~EMC_MODE_SET_DLL_RESET;
 768                         }
 769                         writel_relaxed(val, emc->regs + EMC_MRS);
 770                 }
 771         } else {
 772                 if (timing->emc_mode_2 != emc->emc_mode_2)
 773                         writel_relaxed(timing->emc_mode_2,
 774                                        emc->regs + EMC_MRW);
 775
 776                 if (timing->emc_mode_1 != emc->emc_mode_1)
 777                         writel_relaxed(timing->emc_mode_1,
 778                                        emc->regs + EMC_MRW);
 779         }
 780
 781         emc->emc_mode_1 = timing->emc_mode_1;
 782         emc->emc_mode_2 = timing->emc_mode_2;
 783         emc->emc_mode_reset = timing->emc_mode_reset;
 784
 785         /* issue ZCAL command if turning ZCAL on */
 786         if (emc->zcal_long) {
 787                 writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV0,
 788                                emc->regs + EMC_ZQ_CAL);
 789
 790                 if (dram_num > 1)
 791                         writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV1,
 792                                        emc->regs + EMC_ZQ_CAL);
 793         }
 794
 795         /* flow control marker 3 */
 796         writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE);
 797
 798         /*
 799          * Read and discard an arbitrary MC register (Note: EMC registers
 800          * can't be used) to ensure the register writes are completed.
 801          */
 802         mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
 803
 804         reinit_completion(&emc->clk_handshake_complete);
 805
 806         emc->new_timing = timing;
 807
 808         return 0;
 809 }
 810
 811 static int emc_complete_timing_change(struct tegra_emc *emc,
 812                                       unsigned long rate)
 813 {
 814         unsigned long timeout;
 815
 816         timeout = wait_for_completion_timeout(&emc->clk_handshake_complete,
 817                                               msecs_to_jiffies(100));
 818         if (timeout == 0) {
 819                 dev_err(emc->dev, "emc-car handshake failed\n");
 820                 return -EIO;
 821         }
 822
 823         if (READ_ONCE(emc->bad_state))
 824                 return -EIO;
 825
 826         return 0;
 827 }
 828
 829 static int emc_unprepare_timing_change(struct tegra_emc *emc,
 830                                        unsigned long rate)
 831 {
 832         if (!emc->bad_state) {
 833                 /* shouldn't ever happen in practice */
 834                 dev_err(emc->dev, "timing configuration can't be reverted\n");
 835                 emc->bad_state = true;
 836         }
 837
 838         return 0;
 839 }
 840
 841 static int emc_clk_change_notify(struct notifier_block *nb,
 842                                  unsigned long msg, void *data)
 843 {
 844         struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
 845         struct clk_notifier_data *cnd = data;
 846         int err;
 847
 848         switch (msg) {
 849         case PRE_RATE_CHANGE:
 850                 /*
 851                  * Disable interrupt since read accesses are prohibited after
 852                  * stalling.
 853                  */
 854                 disable_irq(emc->irq);
 855                 err = emc_prepare_timing_change(emc, cnd->new_rate);
 856                 enable_irq(emc->irq);
 857                 break;
 858
 859         case ABORT_RATE_CHANGE:
 860                 err = emc_unprepare_timing_change(emc, cnd->old_rate);
 861                 break;
 862
 863         case POST_RATE_CHANGE:
 864                 err = emc_complete_timing_change(emc, cnd->new_rate);
 865                 break;
 866
 867         default:
 868                 return NOTIFY_DONE;
 869         }
 870
 871         return notifier_from_errno(err);
 872 }
 873
 874 static int load_one_timing_from_dt(struct tegra_emc *emc,
 875                                    struct emc_timing *timing,
 876                                    struct device_node *node)
 877 {
 878         u32 value;
 879         int err;
 880
 881         err = of_property_read_u32(node, "clock-frequency", &value);
 882         if (err) {
 883                 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
 884                         node, err);
 885                 return err;
 886         }
 887
 888         timing->rate = value;
 889
 890         err = of_property_read_u32_array(node, "nvidia,emc-configuration",
 891                                          timing->data,
 892                                          ARRAY_SIZE(emc_timing_registers));
 893         if (err) {
 894                 dev_err(emc->dev,
 895                         "timing %pOF: failed to read emc timing data: %d\n",
 896                         node, err);
 897                 return err;
 898         }
 899
 900 #define EMC_READ_BOOL(prop, dtprop) \
 901         timing->prop = of_property_read_bool(node, dtprop);
 902
 903 #define EMC_READ_U32(prop, dtprop) \
 904         err = of_property_read_u32(node, dtprop, &timing->prop); \
 905         if (err) { \
 906                 dev_err(emc->dev, \
 907                         "timing %pOFn: failed to read " #prop ": %d\n", \
 908                         node, err); \
 909                 return err; \
 910         }
 911
 912         EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
 913         EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1")
 914         EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2")
 915         EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset")
 916         EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
 917         EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref")
 918         EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst")
 919
 920 #undef EMC_READ_U32
 921 #undef EMC_READ_BOOL
 922
 923         dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
 924
 925         return 0;
 926 }
 927
 928 static int cmp_timings(const void *_a, const void *_b)
 929 {
 930         const struct emc_timing *a = _a;
 931         const struct emc_timing *b = _b;
 932
 933         if (a->rate < b->rate)
 934                 return -1;
 935
 936         if (a->rate > b->rate)
 937                 return 1;
 938
 939         return 0;
 940 }
 941
 942 static int emc_check_mc_timings(struct tegra_emc *emc)
 943 {
 944         struct tegra_mc *mc = emc->mc;
 945         unsigned int i;
 946
 947         if (emc->num_timings != mc->num_timings) {
 948                 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
 949                         emc->num_timings, mc->num_timings);
 950                 return -EINVAL;
 951         }
 952
 953         for (i = 0; i < mc->num_timings; i++) {
 954                 if (emc->timings[i].rate != mc->timings[i].rate) {
 955                         dev_err(emc->dev,
 956                                 "emc/mc timing rate mismatch: %lu %lu\n",
 957                                 emc->timings[i].rate, mc->timings[i].rate);
 958                         return -EINVAL;
 959                 }
 960         }
 961
 962         return 0;
 963 }
 964
 965 static int emc_load_timings_from_dt(struct tegra_emc *emc,
 966                                     struct device_node *node)
 967 {
 968         struct device_node *child;
 969         struct emc_timing *timing;
 970         int child_count;
 971         int err;
 972
 973         child_count = of_get_child_count(node);
 974         if (!child_count) {
 975                 dev_err(emc->dev, "no memory timings in: %pOF\n", node);
 976                 return -EINVAL;
 977         }
 978
 979         emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
 980                                     GFP_KERNEL);
 981         if (!emc->timings)
 982                 return -ENOMEM;
 983
 984         emc->num_timings = child_count;
 985         timing = emc->timings;
 986
 987         for_each_child_of_node(node, child) {
 988                 err = load_one_timing_from_dt(emc, timing++, child);
 989                 if (err) {
 990                         of_node_put(child);
 991                         return err;
 992                 }
 993         }
 994
 995         sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
 996              NULL);
 997
 998         err = emc_check_mc_timings(emc);
 999         if (err)
1000                 return err;
1001
1002         dev_info(emc->dev,
1003                  "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
1004                  emc->num_timings,
1005                  tegra_read_ram_code(),
1006                  emc->timings[0].rate / 1000000,
1007                  emc->timings[emc->num_timings - 1].rate / 1000000);
1008
1009         return 0;
1010 }
1011
1012 static struct device_node *emc_find_node_by_ram_code(struct device *dev)
1013 {
1014         struct device_node *np;
1015         u32 value, ram_code;
1016         int err;
1017
1018         ram_code = tegra_read_ram_code();
1019
1020         for_each_child_of_node(dev->of_node, np) {
1021                 err = of_property_read_u32(np, "nvidia,ram-code", &value);
1022                 if (err || value != ram_code)
1023                         continue;
1024
1025                 return np;
1026         }
1027
1028         dev_err(dev, "no memory timings for RAM code %u found in device-tree\n",
1029                 ram_code);
1030
1031         return NULL;
1032 }
1033
1034 static int emc_setup_hw(struct tegra_emc *emc)
1035 {
1036         u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
1037         u32 fbio_cfg5, emc_cfg, emc_dbg;
1038         enum emc_dram_type dram_type;
1039
1040         fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
1041         dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
1042
1043         emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
1044
1045         /* enable EMC and CAR to handshake on PLL divider/source changes */
1046         emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
1047
1048         /* configure clock change mode accordingly to DRAM type */
1049         switch (dram_type) {
1050         case DRAM_TYPE_LPDDR2:
1051                 emc_cfg |= EMC_CLKCHANGE_PD_ENABLE;
1052                 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
1053                 break;
1054
1055         default:
1056                 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
1057                 emc_cfg &= ~EMC_CLKCHANGE_PD_ENABLE;
1058                 break;
1059         }
1060
1061         writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
1062
1063         /* initialize interrupt */
1064         writel_relaxed(intmask, emc->regs + EMC_INTMASK);
1065         writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
1066
1067         /* ensure that unwanted debug features are disabled */
1068         emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
1069         emc_dbg |= EMC_DBG_CFG_PRIORITY;
1070         emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
1071         emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
1072         emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
1073         writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
1074
1075         return 0;
1076 }
1077
1078 static long emc_round_rate(unsigned long rate,
1079                            unsigned long min_rate,
1080                            unsigned long max_rate,
1081                            void *arg)
1082 {
1083         struct emc_timing *timing = NULL;
1084         struct tegra_emc *emc = arg;
1085         unsigned int i;
1086
1087         min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
1088
1089         for (i = 0; i < emc->num_timings; i++) {
1090                 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
1091                         continue;
1092
1093                 if (emc->timings[i].rate > max_rate) {
1094                         i = max(i, 1u) - 1;
1095
1096                         if (emc->timings[i].rate < min_rate)
1097                                 break;
1098                 }
1099
1100                 if (emc->timings[i].rate < min_rate)
1101                         continue;
1102
1103                 timing = &emc->timings[i];
1104                 break;
1105         }
1106
1107         if (!timing) {
1108                 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
1109                         rate, min_rate, max_rate);
1110                 return -EINVAL;
1111         }
1112
1113         return timing->rate;
1114 }
1115
1116 /*
1117  * debugfs interface
1118  *
1119  * The memory controller driver exposes some files in debugfs that can be used
1120  * to control the EMC frequency. The top-level directory can be found here:
1121  *
1122  *   /sys/kernel/debug/emc
1123  *
1124  * It contains the following files:
1125  *
1126  *   - available_rates: This file contains a list of valid, space-separated
1127  *     EMC frequencies.
1128  *
1129  *   - min_rate: Writing a value to this file sets the given frequency as the
1130  *       floor of the permitted range. If this is higher than the currently
1131  *       configured EMC frequency, this will cause the frequency to be
1132  *       increased so that it stays within the valid range.
1133  *
1134  *   - max_rate: Similarily to the min_rate file, writing a value to this file
1135  *       sets the given frequency as the ceiling of the permitted range. If
1136  *       the value is lower than the currently configured EMC frequency, this
1137  *       will cause the frequency to be decreased so that it stays within the
1138  *       valid range.
1139  */
1140
1141 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1142 {
1143         unsigned int i;
1144
1145         for (i = 0; i < emc->num_timings; i++)
1146                 if (rate == emc->timings[i].rate)
1147                         return true;
1148
1149         return false;
1150 }
1151
1152 static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
1153 {
1154         struct tegra_emc *emc = s->private;
1155         const char *prefix = "";
1156         unsigned int i;
1157
1158         for (i = 0; i < emc->num_timings; i++) {
1159                 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1160                 prefix = " ";
1161         }
1162
1163         seq_puts(s, "\n");
1164
1165         return 0;
1166 }
1167
1168 static int tegra_emc_debug_available_rates_open(struct inode *inode,
1169                                                 struct file *file)
1170 {
1171         return single_open(file, tegra_emc_debug_available_rates_show,
1172                            inode->i_private);
1173 }
1174
1175 static const struct file_operations tegra_emc_debug_available_rates_fops = {
1176         .open = tegra_emc_debug_available_rates_open,
1177         .read = seq_read,
1178         .llseek = seq_lseek,
1179         .release = single_release,
1180 };
1181
1182 static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
1183 {
1184         struct tegra_emc *emc = data;
1185
1186         *rate = emc->debugfs.min_rate;
1187
1188         return 0;
1189 }
1190
1191 static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
1192 {
1193         struct tegra_emc *emc = data;
1194         int err;
1195
1196         if (!tegra_emc_validate_rate(emc, rate))
1197                 return -EINVAL;
1198
1199         err = clk_set_min_rate(emc->clk, rate);
1200         if (err < 0)
1201                 return err;
1202
1203         emc->debugfs.min_rate = rate;
1204
1205         return 0;
1206 }
1207
1208 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
1209                         tegra_emc_debug_min_rate_get,
1210                         tegra_emc_debug_min_rate_set, "%llu\n");
1211
1212 static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
1213 {
1214         struct tegra_emc *emc = data;
1215
1216         *rate = emc->debugfs.max_rate;
1217
1218         return 0;
1219 }
1220
1221 static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
1222 {
1223         struct tegra_emc *emc = data;
1224         int err;
1225
1226         if (!tegra_emc_validate_rate(emc, rate))
1227                 return -EINVAL;
1228
1229         err = clk_set_max_rate(emc->clk, rate);
1230         if (err < 0)
1231                 return err;
1232
1233         emc->debugfs.max_rate = rate;
1234
1235         return 0;
1236 }
1237
1238 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
1239                         tegra_emc_debug_max_rate_get,
1240                         tegra_emc_debug_max_rate_set, "%llu\n");
1241
1242 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
1243 {
1244         struct device *dev = emc->dev;
1245         unsigned int i;
1246         int err;
1247
1248         emc->debugfs.min_rate = ULONG_MAX;
1249         emc->debugfs.max_rate = 0;
1250
1251         for (i = 0; i < emc->num_timings; i++) {
1252                 if (emc->timings[i].rate < emc->debugfs.min_rate)
1253                         emc->debugfs.min_rate = emc->timings[i].rate;
1254
1255                 if (emc->timings[i].rate > emc->debugfs.max_rate)
1256                         emc->debugfs.max_rate = emc->timings[i].rate;
1257         }
1258
1259         err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
1260                                  emc->debugfs.max_rate);
1261         if (err < 0) {
1262                 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
1263                         emc->debugfs.min_rate, emc->debugfs.max_rate,
1264                         emc->clk);
1265         }
1266
1267         emc->debugfs.root = debugfs_create_dir("emc", NULL);
1268         if (!emc->debugfs.root) {
1269                 dev_err(emc->dev, "failed to create debugfs directory\n");
1270                 return;
1271         }
1272
1273         debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root,
1274                             emc, &tegra_emc_debug_available_rates_fops);
1275         debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
1276                             emc, &tegra_emc_debug_min_rate_fops);
1277         debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
1278                             emc, &tegra_emc_debug_max_rate_fops);
1279 }
1280
1281 static int tegra_emc_probe(struct platform_device *pdev)
1282 {
1283         struct platform_device *mc;
1284         struct device_node *np;
1285         struct tegra_emc *emc;
1286         int err;
1287
1288         if (of_get_child_count(pdev->dev.of_node) == 0) {
1289                 dev_info(&pdev->dev,
1290                          "device-tree node doesn't have memory timings\n");
1291                 return -ENODEV;
1292         }
1293
1294         np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0);
1295         if (!np) {
1296                 dev_err(&pdev->dev, "could not get memory controller node\n");
1297                 return -ENOENT;
1298         }
1299
1300         mc = of_find_device_by_node(np);
1301         of_node_put(np);
1302         if (!mc)
1303                 return -ENOENT;
1304
1305         np = emc_find_node_by_ram_code(&pdev->dev);
1306         if (!np)
1307                 return -EINVAL;
1308
1309         emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1310         if (!emc) {
1311                 of_node_put(np);
1312                 return -ENOMEM;
1313         }
1314
1315         emc->mc = platform_get_drvdata(mc);
1316         if (!emc->mc)
1317                 return -EPROBE_DEFER;
1318
1319         init_completion(&emc->clk_handshake_complete);
1320         emc->clk_nb.notifier_call = emc_clk_change_notify;
1321         emc->dev = &pdev->dev;
1322
1323         err = emc_load_timings_from_dt(emc, np);
1324         of_node_put(np);
1325         if (err)
1326                 return err;
1327
1328         emc->regs = devm_platform_ioremap_resource(pdev, 0);
1329         if (IS_ERR(emc->regs))
1330                 return PTR_ERR(emc->regs);
1331
1332         err = emc_setup_hw(emc);
1333         if (err)
1334                 return err;
1335
1336         err = platform_get_irq(pdev, 0);
1337         if (err < 0) {
1338                 dev_err(&pdev->dev, "interrupt not specified: %d\n", err);
1339                 return err;
1340         }
1341         emc->irq = err;
1342
1343         err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
1344                                dev_name(&pdev->dev), emc);
1345         if (err) {
1346                 dev_err(&pdev->dev, "failed to request irq: %d\n", err);
1347                 return err;
1348         }
1349
1350         tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
1351
1352         emc->clk = devm_clk_get(&pdev->dev, "emc");
1353         if (IS_ERR(emc->clk)) {
1354                 err = PTR_ERR(emc->clk);
1355                 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
1356                 goto unset_cb;
1357         }
1358
1359         err = clk_notifier_register(emc->clk, &emc->clk_nb);
1360         if (err) {
1361                 dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
1362                         err);
1363                 goto unset_cb;
1364         }
1365
1366         platform_set_drvdata(pdev, emc);
1367         tegra_emc_debugfs_init(emc);
1368
1369         return 0;
1370
1371 unset_cb:
1372         tegra20_clk_set_emc_round_callback(NULL, NULL);
1373
1374         return err;
1375 }
1376
1377 static int tegra_emc_suspend(struct device *dev)
1378 {
1379         struct tegra_emc *emc = dev_get_drvdata(dev);
1380         int err;
1381
1382         /* take exclusive control over the clock's rate */
1383         err = clk_rate_exclusive_get(emc->clk);
1384         if (err) {
1385                 dev_err(emc->dev, "failed to acquire clk: %d\n", err);
1386                 return err;
1387         }
1388
1389         /* suspending in a bad state will hang machine */
1390         if (WARN(emc->bad_state, "hardware in a bad state\n"))
1391                 return -EINVAL;
1392
1393         emc->bad_state = true;
1394
1395         return 0;
1396 }
1397
1398 static int tegra_emc_resume(struct device *dev)
1399 {
1400         struct tegra_emc *emc = dev_get_drvdata(dev);
1401
1402         emc_setup_hw(emc);
1403         emc->bad_state = false;
1404
1405         clk_rate_exclusive_put(emc->clk);
1406
1407         return 0;
1408 }
1409
1410 static const struct dev_pm_ops tegra_emc_pm_ops = {
1411         .suspend = tegra_emc_suspend,
1412         .resume = tegra_emc_resume,
1413 };
1414
1415 static const struct of_device_id tegra_emc_of_match[] = {
1416         { .compatible = "nvidia,tegra30-emc", },
1417         {},
1418 };
1419
1420 static struct platform_driver tegra_emc_driver = {
1421         .probe = tegra_emc_probe,
1422         .driver = {
1423                 .name = "tegra30-emc",
1424                 .of_match_table = tegra_emc_of_match,
1425                 .pm = &tegra_emc_pm_ops,
1426                 .suppress_bind_attrs = true,
1427         },
1428 };
1429
1430 static int __init tegra_emc_init(void)
1431 {
1432         return platform_driver_register(&tegra_emc_driver);
1433 }
1434 subsys_initcall(tegra_emc_init);