drivers/memory/tegra/tegra30.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/of.h>
   7 #include <linux/mm.h>
   8
   9 #include <dt-bindings/memory/tegra30-mc.h>
  10
  11 #include "mc.h"
  12
  13 static const struct tegra_mc_client tegra30_mc_clients[] = {
  14         {
  15                 .id = 0x00,
  16                 .name = "ptcr",
  17                 .swgroup = TEGRA_SWGROUP_PTC,
  18         }, {
  19                 .id = 0x01,
  20                 .name = "display0a",
  21                 .swgroup = TEGRA_SWGROUP_DC,
  22                 .smmu = {
  23                         .reg = 0x228,
  24                         .bit = 1,
  25                 },
  26                 .la = {
  27                         .reg = 0x2e8,
  28                         .shift = 0,
  29                         .mask = 0xff,
  30                         .def = 0x4e,
  31                 },
  32         }, {
  33                 .id = 0x02,
  34                 .name = "display0ab",
  35                 .swgroup = TEGRA_SWGROUP_DCB,
  36                 .smmu = {
  37                         .reg = 0x228,
  38                         .bit = 2,
  39                 },
  40                 .la = {
  41                         .reg = 0x2f4,
  42                         .shift = 0,
  43                         .mask = 0xff,
  44                         .def = 0x4e,
  45                 },
  46         }, {
  47                 .id = 0x03,
  48                 .name = "display0b",
  49                 .swgroup = TEGRA_SWGROUP_DC,
  50                 .smmu = {
  51                         .reg = 0x228,
  52                         .bit = 3,
  53                 },
  54                 .la = {
  55                         .reg = 0x2e8,
  56                         .shift = 16,
  57                         .mask = 0xff,
  58                         .def = 0x4e,
  59                 },
  60         }, {
  61                 .id = 0x04,
  62                 .name = "display0bb",
  63                 .swgroup = TEGRA_SWGROUP_DCB,
  64                 .smmu = {
  65                         .reg = 0x228,
  66                         .bit = 4,
  67                 },
  68                 .la = {
  69                         .reg = 0x2f4,
  70                         .shift = 16,
  71                         .mask = 0xff,
  72                         .def = 0x4e,
  73                 },
  74         }, {
  75                 .id = 0x05,
  76                 .name = "display0c",
  77                 .swgroup = TEGRA_SWGROUP_DC,
  78                 .smmu = {
  79                         .reg = 0x228,
  80                         .bit = 5,
  81                 },
  82                 .la = {
  83                         .reg = 0x2ec,
  84                         .shift = 0,
  85                         .mask = 0xff,
  86                         .def = 0x4e,
  87                 },
  88         }, {
  89                 .id = 0x06,
  90                 .name = "display0cb",
  91                 .swgroup = TEGRA_SWGROUP_DCB,
  92                 .smmu = {
  93                         .reg = 0x228,
  94                         .bit = 6,
  95                 },
  96                 .la = {
  97                         .reg = 0x2f8,
  98                         .shift = 0,
  99                         .mask = 0xff,
 100                         .def = 0x4e,
 101                 },
 102         }, {
 103                 .id = 0x07,
 104                 .name = "display1b",
 105                 .swgroup = TEGRA_SWGROUP_DC,
 106                 .smmu = {
 107                         .reg = 0x228,
 108                         .bit = 7,
 109                 },
 110                 .la = {
 111                         .reg = 0x2ec,
 112                         .shift = 16,
 113                         .mask = 0xff,
 114                         .def = 0x4e,
 115                 },
 116         }, {
 117                 .id = 0x08,
 118                 .name = "display1bb",
 119                 .swgroup = TEGRA_SWGROUP_DCB,
 120                 .smmu = {
 121                         .reg = 0x228,
 122                         .bit = 8,
 123                 },
 124                 .la = {
 125                         .reg = 0x2f8,
 126                         .shift = 16,
 127                         .mask = 0xff,
 128                         .def = 0x4e,
 129                 },
 130         }, {
 131                 .id = 0x09,
 132                 .name = "eppup",
 133                 .swgroup = TEGRA_SWGROUP_EPP,
 134                 .smmu = {
 135                         .reg = 0x228,
 136                         .bit = 9,
 137                 },
 138                 .la = {
 139                         .reg = 0x300,
 140                         .shift = 0,
 141                         .mask = 0xff,
 142                         .def = 0x17,
 143                 },
 144         }, {
 145                 .id = 0x0a,
 146                 .name = "g2pr",
 147                 .swgroup = TEGRA_SWGROUP_G2,
 148                 .smmu = {
 149                         .reg = 0x228,
 150                         .bit = 10,
 151                 },
 152                 .la = {
 153                         .reg = 0x308,
 154                         .shift = 0,
 155                         .mask = 0xff,
 156                         .def = 0x09,
 157                 },
 158         }, {
 159                 .id = 0x0b,
 160                 .name = "g2sr",
 161                 .swgroup = TEGRA_SWGROUP_G2,
 162                 .smmu = {
 163                         .reg = 0x228,
 164                         .bit = 11,
 165                 },
 166                 .la = {
 167                         .reg = 0x308,
 168                         .shift = 16,
 169                         .mask = 0xff,
 170                         .def = 0x09,
 171                 },
 172         }, {
 173                 .id = 0x0c,
 174                 .name = "mpeunifbr",
 175                 .swgroup = TEGRA_SWGROUP_MPE,
 176                 .smmu = {
 177                         .reg = 0x228,
 178                         .bit = 12,
 179                 },
 180                 .la = {
 181                         .reg = 0x328,
 182                         .shift = 0,
 183                         .mask = 0xff,
 184                         .def = 0x50,
 185                 },
 186         }, {
 187                 .id = 0x0d,
 188                 .name = "viruv",
 189                 .swgroup = TEGRA_SWGROUP_VI,
 190                 .smmu = {
 191                         .reg = 0x228,
 192                         .bit = 13,
 193                 },
 194                 .la = {
 195                         .reg = 0x364,
 196                         .shift = 0,
 197                         .mask = 0xff,
 198                         .def = 0x2c,
 199                 },
 200         }, {
 201                 .id = 0x0e,
 202                 .name = "afir",
 203                 .swgroup = TEGRA_SWGROUP_AFI,
 204                 .smmu = {
 205                         .reg = 0x228,
 206                         .bit = 14,
 207                 },
 208                 .la = {
 209                         .reg = 0x2e0,
 210                         .shift = 0,
 211                         .mask = 0xff,
 212                         .def = 0x10,
 213                 },
 214         }, {
 215                 .id = 0x0f,
 216                 .name = "avpcarm7r",
 217                 .swgroup = TEGRA_SWGROUP_AVPC,
 218                 .smmu = {
 219                         .reg = 0x228,
 220                         .bit = 15,
 221                 },
 222                 .la = {
 223                         .reg = 0x2e4,
 224                         .shift = 0,
 225                         .mask = 0xff,
 226                         .def = 0x04,
 227                 },
 228         }, {
 229                 .id = 0x10,
 230                 .name = "displayhc",
 231                 .swgroup = TEGRA_SWGROUP_DC,
 232                 .smmu = {
 233                         .reg = 0x228,
 234                         .bit = 16,
 235                 },
 236                 .la = {
 237                         .reg = 0x2f0,
 238                         .shift = 0,
 239                         .mask = 0xff,
 240                         .def = 0xff,
 241                 },
 242         }, {
 243                 .id = 0x11,
 244                 .name = "displayhcb",
 245                 .swgroup = TEGRA_SWGROUP_DCB,
 246                 .smmu = {
 247                         .reg = 0x228,
 248                         .bit = 17,
 249                 },
 250                 .la = {
 251                         .reg = 0x2fc,
 252                         .shift = 0,
 253                         .mask = 0xff,
 254                         .def = 0xff,
 255                 },
 256         }, {
 257                 .id = 0x12,
 258                 .name = "fdcdrd",
 259                 .swgroup = TEGRA_SWGROUP_NV,
 260                 .smmu = {
 261                         .reg = 0x228,
 262                         .bit = 18,
 263                 },
 264                 .la = {
 265                         .reg = 0x334,
 266                         .shift = 0,
 267                         .mask = 0xff,
 268                         .def = 0x0a,
 269                 },
 270         }, {
 271                 .id = 0x13,
 272                 .name = "fdcdrd2",
 273                 .swgroup = TEGRA_SWGROUP_NV2,
 274                 .smmu = {
 275                         .reg = 0x228,
 276                         .bit = 19,
 277                 },
 278                 .la = {
 279                         .reg = 0x33c,
 280                         .shift = 0,
 281                         .mask = 0xff,
 282                         .def = 0x0a,
 283                 },
 284         }, {
 285                 .id = 0x14,
 286                 .name = "g2dr",
 287                 .swgroup = TEGRA_SWGROUP_G2,
 288                 .smmu = {
 289                         .reg = 0x228,
 290                         .bit = 20,
 291                 },
 292                 .la = {
 293                         .reg = 0x30c,
 294                         .shift = 0,
 295                         .mask = 0xff,
 296                         .def = 0x0a,
 297                 },
 298         }, {
 299                 .id = 0x15,
 300                 .name = "hdar",
 301                 .swgroup = TEGRA_SWGROUP_HDA,
 302                 .smmu = {
 303                         .reg = 0x228,
 304                         .bit = 21,
 305                 },
 306                 .la = {
 307                         .reg = 0x318,
 308                         .shift = 0,
 309                         .mask = 0xff,
 310                         .def = 0xff,
 311                 },
 312         }, {
 313                 .id = 0x16,
 314                 .name = "host1xdmar",
 315                 .swgroup = TEGRA_SWGROUP_HC,
 316                 .smmu = {
 317                         .reg = 0x228,
 318                         .bit = 22,
 319                 },
 320                 .la = {
 321                         .reg = 0x310,
 322                         .shift = 0,
 323                         .mask = 0xff,
 324                         .def = 0x05,
 325                 },
 326         }, {
 327                 .id = 0x17,
 328                 .name = "host1xr",
 329                 .swgroup = TEGRA_SWGROUP_HC,
 330                 .smmu = {
 331                         .reg = 0x228,
 332                         .bit = 23,
 333                 },
 334                 .la = {
 335                         .reg = 0x310,
 336                         .shift = 16,
 337                         .mask = 0xff,
 338                         .def = 0x50,
 339                 },
 340         }, {
 341                 .id = 0x18,
 342                 .name = "idxsrd",
 343                 .swgroup = TEGRA_SWGROUP_NV,
 344                 .smmu = {
 345                         .reg = 0x228,
 346                         .bit = 24,
 347                 },
 348                 .la = {
 349                         .reg = 0x334,
 350                         .shift = 16,
 351                         .mask = 0xff,
 352                         .def = 0x13,
 353                 },
 354         }, {
 355                 .id = 0x19,
 356                 .name = "idxsrd2",
 357                 .swgroup = TEGRA_SWGROUP_NV2,
 358                 .smmu = {
 359                         .reg = 0x228,
 360                         .bit = 25,
 361                 },
 362                 .la = {
 363                         .reg = 0x33c,
 364                         .shift = 16,
 365                         .mask = 0xff,
 366                         .def = 0x13,
 367                 },
 368         }, {
 369                 .id = 0x1a,
 370                 .name = "mpe_ipred",
 371                 .swgroup = TEGRA_SWGROUP_MPE,
 372                 .smmu = {
 373                         .reg = 0x228,
 374                         .bit = 26,
 375                 },
 376                 .la = {
 377                         .reg = 0x328,
 378                         .shift = 16,
 379                         .mask = 0xff,
 380                         .def = 0x80,
 381                 },
 382         }, {
 383                 .id = 0x1b,
 384                 .name = "mpeamemrd",
 385                 .swgroup = TEGRA_SWGROUP_MPE,
 386                 .smmu = {
 387                         .reg = 0x228,
 388                         .bit = 27,
 389                 },
 390                 .la = {
 391                         .reg = 0x32c,
 392                         .shift = 0,
 393                         .mask = 0xff,
 394                         .def = 0x42,
 395                 },
 396         }, {
 397                 .id = 0x1c,
 398                 .name = "mpecsrd",
 399                 .swgroup = TEGRA_SWGROUP_MPE,
 400                 .smmu = {
 401                         .reg = 0x228,
 402                         .bit = 28,
 403                 },
 404                 .la = {
 405                         .reg = 0x32c,
 406                         .shift = 16,
 407                         .mask = 0xff,
 408                         .def = 0xff,
 409                 },
 410         }, {
 411                 .id = 0x1d,
 412                 .name = "ppcsahbdmar",
 413                 .swgroup = TEGRA_SWGROUP_PPCS,
 414                 .smmu = {
 415                         .reg = 0x228,
 416                         .bit = 29,
 417                 },
 418                 .la = {
 419                         .reg = 0x344,
 420                         .shift = 0,
 421                         .mask = 0xff,
 422                         .def = 0x10,
 423                 },
 424         }, {
 425                 .id = 0x1e,
 426                 .name = "ppcsahbslvr",
 427                 .swgroup = TEGRA_SWGROUP_PPCS,
 428                 .smmu = {
 429                         .reg = 0x228,
 430                         .bit = 30,
 431                 },
 432                 .la = {
 433                         .reg = 0x344,
 434                         .shift = 16,
 435                         .mask = 0xff,
 436                         .def = 0x12,
 437                 },
 438         }, {
 439                 .id = 0x1f,
 440                 .name = "satar",
 441                 .swgroup = TEGRA_SWGROUP_SATA,
 442                 .smmu = {
 443                         .reg = 0x228,
 444                         .bit = 31,
 445                 },
 446                 .la = {
 447                         .reg = 0x350,
 448                         .shift = 0,
 449                         .mask = 0xff,
 450                         .def = 0x33,
 451                 },
 452         }, {
 453                 .id = 0x20,
 454                 .name = "texsrd",
 455                 .swgroup = TEGRA_SWGROUP_NV,
 456                 .smmu = {
 457                         .reg = 0x22c,
 458                         .bit = 0,
 459                 },
 460                 .la = {
 461                         .reg = 0x338,
 462                         .shift = 0,
 463                         .mask = 0xff,
 464                         .def = 0x13,
 465                 },
 466         }, {
 467                 .id = 0x21,
 468                 .name = "texsrd2",
 469                 .swgroup = TEGRA_SWGROUP_NV2,
 470                 .smmu = {
 471                         .reg = 0x22c,
 472                         .bit = 1,
 473                 },
 474                 .la = {
 475                         .reg = 0x340,
 476                         .shift = 0,
 477                         .mask = 0xff,
 478                         .def = 0x13,
 479                 },
 480         }, {
 481                 .id = 0x22,
 482                 .name = "vdebsevr",
 483                 .swgroup = TEGRA_SWGROUP_VDE,
 484                 .smmu = {
 485                         .reg = 0x22c,
 486                         .bit = 2,
 487                 },
 488                 .la = {
 489                         .reg = 0x354,
 490                         .shift = 0,
 491                         .mask = 0xff,
 492                         .def = 0xff,
 493                 },
 494         }, {
 495                 .id = 0x23,
 496                 .name = "vdember",
 497                 .swgroup = TEGRA_SWGROUP_VDE,
 498                 .smmu = {
 499                         .reg = 0x22c,
 500                         .bit = 3,
 501                 },
 502                 .la = {
 503                         .reg = 0x354,
 504                         .shift = 16,
 505                         .mask = 0xff,
 506                         .def = 0xd0,
 507                 },
 508         }, {
 509                 .id = 0x24,
 510                 .name = "vdemcer",
 511                 .swgroup = TEGRA_SWGROUP_VDE,
 512                 .smmu = {
 513                         .reg = 0x22c,
 514                         .bit = 4,
 515                 },
 516                 .la = {
 517                         .reg = 0x358,
 518                         .shift = 0,
 519                         .mask = 0xff,
 520                         .def = 0x2a,
 521                 },
 522         }, {
 523                 .id = 0x25,
 524                 .name = "vdetper",
 525                 .swgroup = TEGRA_SWGROUP_VDE,
 526                 .smmu = {
 527                         .reg = 0x22c,
 528                         .bit = 5,
 529                 },
 530                 .la = {
 531                         .reg = 0x358,
 532                         .shift = 16,
 533                         .mask = 0xff,
 534                         .def = 0x74,
 535                 },
 536         }, {
 537                 .id = 0x26,
 538                 .name = "mpcorelpr",
 539                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 540                 .la = {
 541                         .reg = 0x324,
 542                         .shift = 0,
 543                         .mask = 0xff,
 544                         .def = 0x04,
 545                 },
 546         }, {
 547                 .id = 0x27,
 548                 .name = "mpcorer",
 549                 .swgroup = TEGRA_SWGROUP_MPCORE,
 550                 .la = {
 551                         .reg = 0x320,
 552                         .shift = 0,
 553                         .mask = 0xff,
 554                         .def = 0x04,
 555                 },
 556         }, {
 557                 .id = 0x28,
 558                 .name = "eppu",
 559                 .swgroup = TEGRA_SWGROUP_EPP,
 560                 .smmu = {
 561                         .reg = 0x22c,
 562                         .bit = 8,
 563                 },
 564                 .la = {
 565                         .reg = 0x300,
 566                         .shift = 16,
 567                         .mask = 0xff,
 568                         .def = 0x6c,
 569                 },
 570         }, {
 571                 .id = 0x29,
 572                 .name = "eppv",
 573                 .swgroup = TEGRA_SWGROUP_EPP,
 574                 .smmu = {
 575                         .reg = 0x22c,
 576                         .bit = 9,
 577                 },
 578                 .la = {
 579                         .reg = 0x304,
 580                         .shift = 0,
 581                         .mask = 0xff,
 582                         .def = 0x6c,
 583                 },
 584         }, {
 585                 .id = 0x2a,
 586                 .name = "eppy",
 587                 .swgroup = TEGRA_SWGROUP_EPP,
 588                 .smmu = {
 589                         .reg = 0x22c,
 590                         .bit = 10,
 591                 },
 592                 .la = {
 593                         .reg = 0x304,
 594                         .shift = 16,
 595                         .mask = 0xff,
 596                         .def = 0x6c,
 597                 },
 598         }, {
 599                 .id = 0x2b,
 600                 .name = "mpeunifbw",
 601                 .swgroup = TEGRA_SWGROUP_MPE,
 602                 .smmu = {
 603                         .reg = 0x22c,
 604                         .bit = 11,
 605                 },
 606                 .la = {
 607                         .reg = 0x330,
 608                         .shift = 0,
 609                         .mask = 0xff,
 610                         .def = 0x13,
 611                 },
 612         }, {
 613                 .id = 0x2c,
 614                 .name = "viwsb",
 615                 .swgroup = TEGRA_SWGROUP_VI,
 616                 .smmu = {
 617                         .reg = 0x22c,
 618                         .bit = 12,
 619                 },
 620                 .la = {
 621                         .reg = 0x364,
 622                         .shift = 16,
 623                         .mask = 0xff,
 624                         .def = 0x12,
 625                 },
 626         }, {
 627                 .id = 0x2d,
 628                 .name = "viwu",
 629                 .swgroup = TEGRA_SWGROUP_VI,
 630                 .smmu = {
 631                         .reg = 0x22c,
 632                         .bit = 13,
 633                 },
 634                 .la = {
 635                         .reg = 0x368,
 636                         .shift = 0,
 637                         .mask = 0xff,
 638                         .def = 0xb2,
 639                 },
 640         }, {
 641                 .id = 0x2e,
 642                 .name = "viwv",
 643                 .swgroup = TEGRA_SWGROUP_VI,
 644                 .smmu = {
 645                         .reg = 0x22c,
 646                         .bit = 14,
 647                 },
 648                 .la = {
 649                         .reg = 0x368,
 650                         .shift = 16,
 651                         .mask = 0xff,
 652                         .def = 0xb2,
 653                 },
 654         }, {
 655                 .id = 0x2f,
 656                 .name = "viwy",
 657                 .swgroup = TEGRA_SWGROUP_VI,
 658                 .smmu = {
 659                         .reg = 0x22c,
 660                         .bit = 15,
 661                 },
 662                 .la = {
 663                         .reg = 0x36c,
 664                         .shift = 0,
 665                         .mask = 0xff,
 666                         .def = 0x12,
 667                 },
 668         }, {
 669                 .id = 0x30,
 670                 .name = "g2dw",
 671                 .swgroup = TEGRA_SWGROUP_G2,
 672                 .smmu = {
 673                         .reg = 0x22c,
 674                         .bit = 16,
 675                 },
 676                 .la = {
 677                         .reg = 0x30c,
 678                         .shift = 16,
 679                         .mask = 0xff,
 680                         .def = 0x9,
 681                 },
 682         }, {
 683                 .id = 0x31,
 684                 .name = "afiw",
 685                 .swgroup = TEGRA_SWGROUP_AFI,
 686                 .smmu = {
 687                         .reg = 0x22c,
 688                         .bit = 17,
 689                 },
 690                 .la = {
 691                         .reg = 0x2e0,
 692                         .shift = 16,
 693                         .mask = 0xff,
 694                         .def = 0x0c,
 695                 },
 696         }, {
 697                 .id = 0x32,
 698                 .name = "avpcarm7w",
 699                 .swgroup = TEGRA_SWGROUP_AVPC,
 700                 .smmu = {
 701                         .reg = 0x22c,
 702                         .bit = 18,
 703                 },
 704                 .la = {
 705                         .reg = 0x2e4,
 706                         .shift = 16,
 707                         .mask = 0xff,
 708                         .def = 0x0e,
 709                 },
 710         }, {
 711                 .id = 0x33,
 712                 .name = "fdcdwr",
 713                 .swgroup = TEGRA_SWGROUP_NV,
 714                 .smmu = {
 715                         .reg = 0x22c,
 716                         .bit = 19,
 717                 },
 718                 .la = {
 719                         .reg = 0x338,
 720                         .shift = 16,
 721                         .mask = 0xff,
 722                         .def = 0x0a,
 723                 },
 724         }, {
 725                 .id = 0x34,
 726                 .name = "fdcdwr2",
 727                 .swgroup = TEGRA_SWGROUP_NV2,
 728                 .smmu = {
 729                         .reg = 0x22c,
 730                         .bit = 20,
 731                 },
 732                 .la = {
 733                         .reg = 0x340,
 734                         .shift = 16,
 735                         .mask = 0xff,
 736                         .def = 0x0a,
 737                 },
 738         }, {
 739                 .id = 0x35,
 740                 .name = "hdaw",
 741                 .swgroup = TEGRA_SWGROUP_HDA,
 742                 .smmu = {
 743                         .reg = 0x22c,
 744                         .bit = 21,
 745                 },
 746                 .la = {
 747                         .reg = 0x318,
 748                         .shift = 16,
 749                         .mask = 0xff,
 750                         .def = 0xff,
 751                 },
 752         }, {
 753                 .id = 0x36,
 754                 .name = "host1xw",
 755                 .swgroup = TEGRA_SWGROUP_HC,
 756                 .smmu = {
 757                         .reg = 0x22c,
 758                         .bit = 22,
 759                 },
 760                 .la = {
 761                         .reg = 0x314,
 762                         .shift = 0,
 763                         .mask = 0xff,
 764                         .def = 0x10,
 765                 },
 766         }, {
 767                 .id = 0x37,
 768                 .name = "ispw",
 769                 .swgroup = TEGRA_SWGROUP_ISP,
 770                 .smmu = {
 771                         .reg = 0x22c,
 772                         .bit = 23,
 773                 },
 774                 .la = {
 775                         .reg = 0x31c,
 776                         .shift = 0,
 777                         .mask = 0xff,
 778                         .def = 0xff,
 779                 },
 780         }, {
 781                 .id = 0x38,
 782                 .name = "mpcorelpw",
 783                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 784                 .la = {
 785                         .reg = 0x324,
 786                         .shift = 16,
 787                         .mask = 0xff,
 788                         .def = 0x0e,
 789                 },
 790         }, {
 791                 .id = 0x39,
 792                 .name = "mpcorew",
 793                 .swgroup = TEGRA_SWGROUP_MPCORE,
 794                 .la = {
 795                         .reg = 0x320,
 796                         .shift = 16,
 797                         .mask = 0xff,
 798                         .def = 0x0e,
 799                 },
 800         }, {
 801                 .id = 0x3a,
 802                 .name = "mpecswr",
 803                 .swgroup = TEGRA_SWGROUP_MPE,
 804                 .smmu = {
 805                         .reg = 0x22c,
 806                         .bit = 26,
 807                 },
 808                 .la = {
 809                         .reg = 0x330,
 810                         .shift = 16,
 811                         .mask = 0xff,
 812                         .def = 0xff,
 813                 },
 814         }, {
 815                 .id = 0x3b,
 816                 .name = "ppcsahbdmaw",
 817                 .swgroup = TEGRA_SWGROUP_PPCS,
 818                 .smmu = {
 819                         .reg = 0x22c,
 820                         .bit = 27,
 821                 },
 822                 .la = {
 823                         .reg = 0x348,
 824                         .shift = 0,
 825                         .mask = 0xff,
 826                         .def = 0x10,
 827                 },
 828         }, {
 829                 .id = 0x3c,
 830                 .name = "ppcsahbslvw",
 831                 .swgroup = TEGRA_SWGROUP_PPCS,
 832                 .smmu = {
 833                         .reg = 0x22c,
 834                         .bit = 28,
 835                 },
 836                 .la = {
 837                         .reg = 0x348,
 838                         .shift = 16,
 839                         .mask = 0xff,
 840                         .def = 0x06,
 841                 },
 842         }, {
 843                 .id = 0x3d,
 844                 .name = "sataw",
 845                 .swgroup = TEGRA_SWGROUP_SATA,
 846                 .smmu = {
 847                         .reg = 0x22c,
 848                         .bit = 29,
 849                 },
 850                 .la = {
 851                         .reg = 0x350,
 852                         .shift = 16,
 853                         .mask = 0xff,
 854                         .def = 0x33,
 855                 },
 856         }, {
 857                 .id = 0x3e,
 858                 .name = "vdebsevw",
 859                 .swgroup = TEGRA_SWGROUP_VDE,
 860                 .smmu = {
 861                         .reg = 0x22c,
 862                         .bit = 30,
 863                 },
 864                 .la = {
 865                         .reg = 0x35c,
 866                         .shift = 0,
 867                         .mask = 0xff,
 868                         .def = 0xff,
 869                 },
 870         }, {
 871                 .id = 0x3f,
 872                 .name = "vdedbgw",
 873                 .swgroup = TEGRA_SWGROUP_VDE,
 874                 .smmu = {
 875                         .reg = 0x22c,
 876                         .bit = 31,
 877                 },
 878                 .la = {
 879                         .reg = 0x35c,
 880                         .shift = 16,
 881                         .mask = 0xff,
 882                         .def = 0xff,
 883                 },
 884         }, {
 885                 .id = 0x40,
 886                 .name = "vdembew",
 887                 .swgroup = TEGRA_SWGROUP_VDE,
 888                 .smmu = {
 889                         .reg = 0x230,
 890                         .bit = 0,
 891                 },
 892                 .la = {
 893                         .reg = 0x360,
 894                         .shift = 0,
 895                         .mask = 0xff,
 896                         .def = 0x42,
 897                 },
 898         }, {
 899                 .id = 0x41,
 900                 .name = "vdetpmw",
 901                 .swgroup = TEGRA_SWGROUP_VDE,
 902                 .smmu = {
 903                         .reg = 0x230,
 904                         .bit = 1,
 905                 },
 906                 .la = {
 907                         .reg = 0x360,
 908                         .shift = 16,
 909                         .mask = 0xff,
 910                         .def = 0x2a,
 911                 },
 912         },
 913 };
 914
 915 static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
 916         { .name = "dc",   .swgroup = TEGRA_SWGROUP_DC,   .reg = 0x240 },
 917         { .name = "dcb",  .swgroup = TEGRA_SWGROUP_DCB,  .reg = 0x244 },
 918         { .name = "epp",  .swgroup = TEGRA_SWGROUP_EPP,  .reg = 0x248 },
 919         { .name = "g2",   .swgroup = TEGRA_SWGROUP_G2,   .reg = 0x24c },
 920         { .name = "mpe",  .swgroup = TEGRA_SWGROUP_MPE,  .reg = 0x264 },
 921         { .name = "vi",   .swgroup = TEGRA_SWGROUP_VI,   .reg = 0x280 },
 922         { .name = "afi",  .swgroup = TEGRA_SWGROUP_AFI,  .reg = 0x238 },
 923         { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
 924         { .name = "nv",   .swgroup = TEGRA_SWGROUP_NV,   .reg = 0x268 },
 925         { .name = "nv2",  .swgroup = TEGRA_SWGROUP_NV2,  .reg = 0x26c },
 926         { .name = "hda",  .swgroup = TEGRA_SWGROUP_HDA,  .reg = 0x254 },
 927         { .name = "hc",   .swgroup = TEGRA_SWGROUP_HC,   .reg = 0x250 },
 928         { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
 929         { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
 930         { .name = "vde",  .swgroup = TEGRA_SWGROUP_VDE,  .reg = 0x27c },
 931         { .name = "isp",  .swgroup = TEGRA_SWGROUP_ISP,  .reg = 0x258 },
 932 };
 933
 934 static const unsigned int tegra30_group_drm[] = {
 935         TEGRA_SWGROUP_DC,
 936         TEGRA_SWGROUP_DCB,
 937         TEGRA_SWGROUP_G2,
 938         TEGRA_SWGROUP_NV,
 939         TEGRA_SWGROUP_NV2,
 940 };
 941
 942 static const struct tegra_smmu_group_soc tegra30_groups[] = {
 943         {
 944                 .name = "drm",
 945                 .swgroups = tegra30_group_drm,
 946                 .num_swgroups = ARRAY_SIZE(tegra30_group_drm),
 947         },
 948 };
 949
 950 static const struct tegra_smmu_soc tegra30_smmu_soc = {
 951         .clients = tegra30_mc_clients,
 952         .num_clients = ARRAY_SIZE(tegra30_mc_clients),
 953         .swgroups = tegra30_swgroups,
 954         .num_swgroups = ARRAY_SIZE(tegra30_swgroups),
 955         .groups = tegra30_groups,
 956         .num_groups = ARRAY_SIZE(tegra30_groups),
 957         .supports_round_robin_arbitration = false,
 958         .supports_request_limit = false,
 959         .num_tlb_lines = 16,
 960         .num_asids = 4,
 961 };
 962
 963 #define TEGRA30_MC_RESET(_name, _control, _status, _bit)        \
 964         {                                                       \
 965                 .name = #_name,                                 \
 966                 .id = TEGRA30_MC_RESET_##_name,                 \
 967                 .control = _control,                            \
 968                 .status = _status,                              \
 969                 .bit = _bit,                                    \
 970         }
 971
 972 static const struct tegra_mc_reset tegra30_mc_resets[] = {
 973         TEGRA30_MC_RESET(AFI,      0x200, 0x204,  0),
 974         TEGRA30_MC_RESET(AVPC,     0x200, 0x204,  1),
 975         TEGRA30_MC_RESET(DC,       0x200, 0x204,  2),
 976         TEGRA30_MC_RESET(DCB,      0x200, 0x204,  3),
 977         TEGRA30_MC_RESET(EPP,      0x200, 0x204,  4),
 978         TEGRA30_MC_RESET(2D,       0x200, 0x204,  5),
 979         TEGRA30_MC_RESET(HC,       0x200, 0x204,  6),
 980         TEGRA30_MC_RESET(HDA,      0x200, 0x204,  7),
 981         TEGRA30_MC_RESET(ISP,      0x200, 0x204,  8),
 982         TEGRA30_MC_RESET(MPCORE,   0x200, 0x204,  9),
 983         TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
 984         TEGRA30_MC_RESET(MPE,      0x200, 0x204, 11),
 985         TEGRA30_MC_RESET(3D,       0x200, 0x204, 12),
 986         TEGRA30_MC_RESET(3D2,      0x200, 0x204, 13),
 987         TEGRA30_MC_RESET(PPCS,     0x200, 0x204, 14),
 988         TEGRA30_MC_RESET(SATA,     0x200, 0x204, 15),
 989         TEGRA30_MC_RESET(VDE,      0x200, 0x204, 16),
 990         TEGRA30_MC_RESET(VI,       0x200, 0x204, 17),
 991 };
 992
 993 const struct tegra_mc_soc tegra30_mc_soc = {
 994         .clients = tegra30_mc_clients,
 995         .num_clients = ARRAY_SIZE(tegra30_mc_clients),
 996         .num_address_bits = 32,
 997         .atom_size = 16,
 998         .client_id_mask = 0x7f,
 999         .smmu = &tegra30_smmu_soc,
1000         .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1001                    MC_INT_DECERR_EMEM,
1002         .reset_ops = &tegra_mc_reset_ops_common,
1003         .resets = tegra30_mc_resets,
1004         .num_resets = ARRAY_SIZE(tegra30_mc_resets),
1005 };