2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #include <dt-bindings/memory/tegra30-mc.h>
16 static const struct tegra_mc_client tegra30_mc_clients[] = {
20 .swgroup = TEGRA_SWGROUP_PTC,
24 .swgroup = TEGRA_SWGROUP_DC,
38 .swgroup = TEGRA_SWGROUP_DCB,
52 .swgroup = TEGRA_SWGROUP_DC,
66 .swgroup = TEGRA_SWGROUP_DCB,
80 .swgroup = TEGRA_SWGROUP_DC,
94 .swgroup = TEGRA_SWGROUP_DCB,
108 .swgroup = TEGRA_SWGROUP_DC,
121 .name = "display1bb",
122 .swgroup = TEGRA_SWGROUP_DCB,
136 .swgroup = TEGRA_SWGROUP_EPP,
150 .swgroup = TEGRA_SWGROUP_G2,
164 .swgroup = TEGRA_SWGROUP_G2,
178 .swgroup = TEGRA_SWGROUP_MPE,
192 .swgroup = TEGRA_SWGROUP_VI,
206 .swgroup = TEGRA_SWGROUP_AFI,
220 .swgroup = TEGRA_SWGROUP_AVPC,
234 .swgroup = TEGRA_SWGROUP_DC,
247 .name = "displayhcb",
248 .swgroup = TEGRA_SWGROUP_DCB,
262 .swgroup = TEGRA_SWGROUP_NV,
276 .swgroup = TEGRA_SWGROUP_NV2,
290 .swgroup = TEGRA_SWGROUP_G2,
304 .swgroup = TEGRA_SWGROUP_HDA,
317 .name = "host1xdmar",
318 .swgroup = TEGRA_SWGROUP_HC,
332 .swgroup = TEGRA_SWGROUP_HC,
346 .swgroup = TEGRA_SWGROUP_NV,
360 .swgroup = TEGRA_SWGROUP_NV2,
374 .swgroup = TEGRA_SWGROUP_MPE,
388 .swgroup = TEGRA_SWGROUP_MPE,
402 .swgroup = TEGRA_SWGROUP_MPE,
415 .name = "ppcsahbdmar",
416 .swgroup = TEGRA_SWGROUP_PPCS,
429 .name = "ppcsahbslvr",
430 .swgroup = TEGRA_SWGROUP_PPCS,
444 .swgroup = TEGRA_SWGROUP_SATA,
458 .swgroup = TEGRA_SWGROUP_NV,
472 .swgroup = TEGRA_SWGROUP_NV2,
486 .swgroup = TEGRA_SWGROUP_VDE,
500 .swgroup = TEGRA_SWGROUP_VDE,
514 .swgroup = TEGRA_SWGROUP_VDE,
528 .swgroup = TEGRA_SWGROUP_VDE,
542 .swgroup = TEGRA_SWGROUP_MPCORELP,
552 .swgroup = TEGRA_SWGROUP_MPCORE,
562 .swgroup = TEGRA_SWGROUP_EPP,
576 .swgroup = TEGRA_SWGROUP_EPP,
590 .swgroup = TEGRA_SWGROUP_EPP,
604 .swgroup = TEGRA_SWGROUP_MPE,
618 .swgroup = TEGRA_SWGROUP_VI,
632 .swgroup = TEGRA_SWGROUP_VI,
646 .swgroup = TEGRA_SWGROUP_VI,
660 .swgroup = TEGRA_SWGROUP_VI,
674 .swgroup = TEGRA_SWGROUP_G2,
688 .swgroup = TEGRA_SWGROUP_AFI,
702 .swgroup = TEGRA_SWGROUP_AVPC,
716 .swgroup = TEGRA_SWGROUP_NV,
730 .swgroup = TEGRA_SWGROUP_NV2,
744 .swgroup = TEGRA_SWGROUP_HDA,
758 .swgroup = TEGRA_SWGROUP_HC,
772 .swgroup = TEGRA_SWGROUP_ISP,
786 .swgroup = TEGRA_SWGROUP_MPCORELP,
796 .swgroup = TEGRA_SWGROUP_MPCORE,
806 .swgroup = TEGRA_SWGROUP_MPE,
819 .name = "ppcsahbdmaw",
820 .swgroup = TEGRA_SWGROUP_PPCS,
833 .name = "ppcsahbslvw",
834 .swgroup = TEGRA_SWGROUP_PPCS,
848 .swgroup = TEGRA_SWGROUP_SATA,
862 .swgroup = TEGRA_SWGROUP_VDE,
876 .swgroup = TEGRA_SWGROUP_VDE,
890 .swgroup = TEGRA_SWGROUP_VDE,
904 .swgroup = TEGRA_SWGROUP_VDE,
918 static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
919 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
920 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
921 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
922 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
923 { .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 },
924 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
925 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
926 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
927 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
928 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
929 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
930 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
931 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
932 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },
933 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
934 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
937 static const unsigned int tegra30_group_display[] = {
942 static const struct tegra_smmu_group_soc tegra30_groups[] = {
945 .swgroups = tegra30_group_display,
946 .num_swgroups = ARRAY_SIZE(tegra30_group_display),
950 static const struct tegra_smmu_soc tegra30_smmu_soc = {
951 .clients = tegra30_mc_clients,
952 .num_clients = ARRAY_SIZE(tegra30_mc_clients),
953 .swgroups = tegra30_swgroups,
954 .num_swgroups = ARRAY_SIZE(tegra30_swgroups),
955 .groups = tegra30_groups,
956 .num_groups = ARRAY_SIZE(tegra30_groups),
957 .supports_round_robin_arbitration = false,
958 .supports_request_limit = false,
963 #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \
966 .id = TEGRA30_MC_RESET_##_name, \
967 .control = _control, \
972 static const struct tegra_mc_reset tegra30_mc_resets[] = {
973 TEGRA30_MC_RESET(AFI, 0x200, 0x204, 0),
974 TEGRA30_MC_RESET(AVPC, 0x200, 0x204, 1),
975 TEGRA30_MC_RESET(DC, 0x200, 0x204, 2),
976 TEGRA30_MC_RESET(DCB, 0x200, 0x204, 3),
977 TEGRA30_MC_RESET(EPP, 0x200, 0x204, 4),
978 TEGRA30_MC_RESET(2D, 0x200, 0x204, 5),
979 TEGRA30_MC_RESET(HC, 0x200, 0x204, 6),
980 TEGRA30_MC_RESET(HDA, 0x200, 0x204, 7),
981 TEGRA30_MC_RESET(ISP, 0x200, 0x204, 8),
982 TEGRA30_MC_RESET(MPCORE, 0x200, 0x204, 9),
983 TEGRA30_MC_RESET(MPCORELP, 0x200, 0x204, 10),
984 TEGRA30_MC_RESET(MPE, 0x200, 0x204, 11),
985 TEGRA30_MC_RESET(3D, 0x200, 0x204, 12),
986 TEGRA30_MC_RESET(3D2, 0x200, 0x204, 13),
987 TEGRA30_MC_RESET(PPCS, 0x200, 0x204, 14),
988 TEGRA30_MC_RESET(SATA, 0x200, 0x204, 15),
989 TEGRA30_MC_RESET(VDE, 0x200, 0x204, 16),
990 TEGRA30_MC_RESET(VI, 0x200, 0x204, 17),
993 const struct tegra_mc_soc tegra30_mc_soc = {
994 .clients = tegra30_mc_clients,
995 .num_clients = ARRAY_SIZE(tegra30_mc_clients),
996 .num_address_bits = 32,
998 .client_id_mask = 0x7f,
999 .smmu = &tegra30_smmu_soc,
1000 .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1002 .reset_ops = &terga_mc_reset_ops_common,
1003 .resets = tegra30_mc_resets,
1004 .num_resets = ARRAY_SIZE(tegra30_mc_resets),