1 // SPDX-License-Identifier: GPL-2.0-only
3 * DB8500 PRCM Unit driver
5 * Copyright (C) STMicroelectronics 2009
6 * Copyright (C) ST-Ericsson SA 2010
8 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
9 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
10 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
12 * U8500 PRCM Unit interface driver
14 #include <linux/init.h>
15 #include <linux/export.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/spinlock.h>
22 #include <linux/slab.h>
23 #include <linux/mutex.h>
24 #include <linux/completion.h>
25 #include <linux/irq.h>
26 #include <linux/jiffies.h>
27 #include <linux/bitops.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/uaccess.h>
33 #include <linux/mfd/core.h>
34 #include <linux/mfd/dbx500-prcmu.h>
35 #include <linux/mfd/abx500/ab8500.h>
36 #include <linux/regulator/db8500-prcmu.h>
37 #include <linux/regulator/machine.h>
38 #include <linux/platform_data/ux500_wdt.h>
39 #include <linux/platform_data/db8500_thermal.h>
40 #include "dbx500-prcmu-regs.h"
42 /* Index of different voltages to be used when accessing AVSData */
43 #define PRCM_AVS_BASE 0x2FC
44 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
45 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
46 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
47 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
48 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
49 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
50 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
51 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
52 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
53 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
54 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
55 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
56 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
58 #define PRCM_AVS_VOLTAGE 0
59 #define PRCM_AVS_VOLTAGE_MASK 0x3f
60 #define PRCM_AVS_ISSLOWSTARTUP 6
61 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
62 #define PRCM_AVS_ISMODEENABLE 7
63 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
65 #define PRCM_BOOT_STATUS 0xFFF
66 #define PRCM_ROMCODE_A2P 0xFFE
67 #define PRCM_ROMCODE_P2A 0xFFD
68 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
70 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
72 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
73 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
74 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
75 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
76 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
77 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
78 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
79 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
82 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
83 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
84 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
85 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
86 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
87 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
90 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
91 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
92 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
93 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
94 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
95 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
97 /* Mailbox 0 headers */
98 #define MB0H_POWER_STATE_TRANS 0
99 #define MB0H_CONFIG_WAKEUPS_EXE 1
100 #define MB0H_READ_WAKEUP_ACK 3
101 #define MB0H_CONFIG_WAKEUPS_SLEEP 4
103 #define MB0H_WAKEUP_EXE 2
104 #define MB0H_WAKEUP_SLEEP 5
107 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
108 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
109 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
110 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
111 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
112 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
115 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
116 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
117 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
118 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
119 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
120 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
121 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
123 /* Mailbox 1 headers */
124 #define MB1H_ARM_APE_OPP 0x0
125 #define MB1H_RESET_MODEM 0x2
126 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
127 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
128 #define MB1H_RELEASE_USB_WAKEUP 0x5
129 #define MB1H_PLL_ON_OFF 0x6
131 /* Mailbox 1 Requests */
132 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
133 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
134 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
135 #define PLL_SOC0_OFF 0x1
136 #define PLL_SOC0_ON 0x2
137 #define PLL_SOC1_OFF 0x4
138 #define PLL_SOC1_ON 0x8
141 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
142 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
143 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
144 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
146 /* Mailbox 2 headers */
148 #define MB2H_AUTO_PWR 0x1
151 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
152 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
153 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
154 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
155 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
156 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
157 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
158 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
159 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
160 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
163 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
164 #define HWACC_PWR_ST_OK 0xFE
166 /* Mailbox 3 headers */
168 #define MB3H_SIDETONE 0x1
169 #define MB3H_SYSCLK 0xE
171 /* Mailbox 3 Requests */
172 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
173 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
174 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
175 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
176 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
177 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
178 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
180 /* Mailbox 4 headers */
181 #define MB4H_DDR_INIT 0x0
182 #define MB4H_MEM_ST 0x1
183 #define MB4H_HOTDOG 0x12
184 #define MB4H_HOTMON 0x13
185 #define MB4H_HOT_PERIOD 0x14
186 #define MB4H_A9WDOG_CONF 0x16
187 #define MB4H_A9WDOG_EN 0x17
188 #define MB4H_A9WDOG_DIS 0x18
189 #define MB4H_A9WDOG_LOAD 0x19
190 #define MB4H_A9WDOG_KICK 0x20
192 /* Mailbox 4 Requests */
193 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
194 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
195 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
196 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
197 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
198 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
199 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
200 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
201 #define HOTMON_CONFIG_LOW BIT(0)
202 #define HOTMON_CONFIG_HIGH BIT(1)
203 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
204 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
205 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
206 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
207 #define A9WDOG_AUTO_OFF_EN BIT(7)
208 #define A9WDOG_AUTO_OFF_DIS 0
209 #define A9WDOG_ID_MASK 0xf
211 /* Mailbox 5 Requests */
212 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
213 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
214 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
215 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
216 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
217 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
218 #define PRCMU_I2C_STOP_EN BIT(3)
221 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
222 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
223 #define I2C_WR_OK 0x1
224 #define I2C_RD_OK 0x2
228 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
234 #define WAKEUP_BIT_RTC BIT(0)
235 #define WAKEUP_BIT_RTT0 BIT(1)
236 #define WAKEUP_BIT_RTT1 BIT(2)
237 #define WAKEUP_BIT_HSI0 BIT(3)
238 #define WAKEUP_BIT_HSI1 BIT(4)
239 #define WAKEUP_BIT_CA_WAKE BIT(5)
240 #define WAKEUP_BIT_USB BIT(6)
241 #define WAKEUP_BIT_ABB BIT(7)
242 #define WAKEUP_BIT_ABB_FIFO BIT(8)
243 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
244 #define WAKEUP_BIT_CA_SLEEP BIT(10)
245 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
246 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
247 #define WAKEUP_BIT_ANC_OK BIT(13)
248 #define WAKEUP_BIT_SW_ERROR BIT(14)
249 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
250 #define WAKEUP_BIT_ARM BIT(17)
251 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
252 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
253 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
254 #define WAKEUP_BIT_GPIO0 BIT(23)
255 #define WAKEUP_BIT_GPIO1 BIT(24)
256 #define WAKEUP_BIT_GPIO2 BIT(25)
257 #define WAKEUP_BIT_GPIO3 BIT(26)
258 #define WAKEUP_BIT_GPIO4 BIT(27)
259 #define WAKEUP_BIT_GPIO5 BIT(28)
260 #define WAKEUP_BIT_GPIO6 BIT(29)
261 #define WAKEUP_BIT_GPIO7 BIT(30)
262 #define WAKEUP_BIT_GPIO8 BIT(31)
266 struct prcmu_fw_version version;
269 static struct irq_domain *db8500_irq_domain;
272 * This vector maps irq numbers to the bits in the bit field used in
273 * communication with the PRCMU firmware.
275 * The reason for having this is to keep the irq numbers contiguous even though
276 * the bits in the bit field are not. (The bits also have a tendency to move
277 * around, to further complicate matters.)
279 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
280 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
282 #define IRQ_PRCMU_RTC 0
283 #define IRQ_PRCMU_RTT0 1
284 #define IRQ_PRCMU_RTT1 2
285 #define IRQ_PRCMU_HSI0 3
286 #define IRQ_PRCMU_HSI1 4
287 #define IRQ_PRCMU_CA_WAKE 5
288 #define IRQ_PRCMU_USB 6
289 #define IRQ_PRCMU_ABB 7
290 #define IRQ_PRCMU_ABB_FIFO 8
291 #define IRQ_PRCMU_ARM 9
292 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
293 #define IRQ_PRCMU_GPIO0 11
294 #define IRQ_PRCMU_GPIO1 12
295 #define IRQ_PRCMU_GPIO2 13
296 #define IRQ_PRCMU_GPIO3 14
297 #define IRQ_PRCMU_GPIO4 15
298 #define IRQ_PRCMU_GPIO5 16
299 #define IRQ_PRCMU_GPIO6 17
300 #define IRQ_PRCMU_GPIO7 18
301 #define IRQ_PRCMU_GPIO8 19
302 #define IRQ_PRCMU_CA_SLEEP 20
303 #define IRQ_PRCMU_HOTMON_LOW 21
304 #define IRQ_PRCMU_HOTMON_HIGH 22
305 #define NUM_PRCMU_WAKEUPS 23
307 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
319 IRQ_ENTRY(HOTMON_LOW),
320 IRQ_ENTRY(HOTMON_HIGH),
321 IRQ_ENTRY(MODEM_SW_RESET_REQ),
333 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
334 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
335 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
343 WAKEUP_ENTRY(ABB_FIFO),
348 * mb0_transfer - state needed for mailbox 0 communication.
349 * @lock: The transaction lock.
350 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
352 * @mask_work: Work structure used for (un)masking wakeup interrupts.
353 * @req: Request data that need to persist between requests.
357 spinlock_t dbb_irqs_lock;
358 struct work_struct mask_work;
359 struct mutex ac_wake_lock;
360 struct completion ac_wake_work;
369 * mb1_transfer - state needed for mailbox 1 communication.
370 * @lock: The transaction lock.
371 * @work: The transaction completion structure.
372 * @ape_opp: The current APE OPP.
373 * @ack: Reply ("acknowledge") data.
377 struct completion work;
383 u8 ape_voltage_status;
388 * mb2_transfer - state needed for mailbox 2 communication.
389 * @lock: The transaction lock.
390 * @work: The transaction completion structure.
391 * @auto_pm_lock: The autonomous power management configuration lock.
392 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
393 * @req: Request data that need to persist between requests.
394 * @ack: Reply ("acknowledge") data.
398 struct completion work;
399 spinlock_t auto_pm_lock;
400 bool auto_pm_enabled;
407 * mb3_transfer - state needed for mailbox 3 communication.
408 * @lock: The request lock.
409 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
410 * @sysclk_work: Work structure used for sysclk requests.
414 struct mutex sysclk_lock;
415 struct completion sysclk_work;
419 * mb4_transfer - state needed for mailbox 4 communication.
420 * @lock: The transaction lock.
421 * @work: The transaction completion structure.
425 struct completion work;
429 * mb5_transfer - state needed for mailbox 5 communication.
430 * @lock: The transaction lock.
431 * @work: The transaction completion structure.
432 * @ack: Reply ("acknowledge") data.
436 struct completion work;
443 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
446 static DEFINE_SPINLOCK(prcmu_lock);
447 static DEFINE_SPINLOCK(clkout_lock);
449 /* Global var to runtime determine TCDM base for v2 or v1 */
450 static __iomem void *tcdm_base;
451 static __iomem void *prcmu_base;
466 static DEFINE_SPINLOCK(clk_mgt_lock);
468 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
469 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
470 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
471 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
472 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
474 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
475 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
476 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
477 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
478 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
483 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
485 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
486 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
487 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
488 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
489 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
490 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
491 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
492 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
493 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
494 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
495 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
496 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
497 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
498 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
499 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
508 static struct dsiclk dsiclk[2] = {
510 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
511 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
512 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
515 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
516 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
517 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
527 static struct dsiescclk dsiescclk[3] = {
529 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
530 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
531 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
534 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
535 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
536 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
539 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
540 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
541 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
547 * Used by MCDE to setup all necessary PRCMU registers
549 #define PRCMU_RESET_DSIPLL 0x00004000
550 #define PRCMU_UNCLAMP_DSIPLL 0x00400800
552 #define PRCMU_CLK_PLL_DIV_SHIFT 0
553 #define PRCMU_CLK_PLL_SW_SHIFT 5
554 #define PRCMU_CLK_38 (1 << 9)
555 #define PRCMU_CLK_38_SRC (1 << 10)
556 #define PRCMU_CLK_38_DIV (1 << 11)
558 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
559 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C
561 /* DPI 50000000 Hz */
562 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
563 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
564 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
566 /* D=101, N=1, R=4, SELDIV2=0 */
567 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
569 #define PRCMU_ENABLE_PLLDSI 0x00000001
570 #define PRCMU_DISABLE_PLLDSI 0x00000000
571 #define PRCMU_RELEASE_RESET_DSS 0x0000400C
572 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
573 /* ESC clk, div0=1, div1=1, div2=3 */
574 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
575 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
576 #define PRCMU_DSI_RESET_SW 0x00000007
578 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
580 int db8500_prcmu_enable_dsipll(void)
584 /* Clear DSIPLL_RESETN */
585 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
586 /* Unclamp DSIPLL in/out */
587 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
589 /* Set DSI PLL FREQ */
590 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
591 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
592 /* Enable Escape clocks */
593 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
596 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
598 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
599 for (i = 0; i < 10; i++) {
600 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
601 == PRCMU_PLLDSI_LOCKP_LOCKED)
605 /* Set DSIPLL_RESETN */
606 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
610 int db8500_prcmu_disable_dsipll(void)
612 /* Disable dsi pll */
613 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
614 /* Disable escapeclock */
615 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
619 int db8500_prcmu_set_display_clocks(void)
623 spin_lock_irqsave(&clk_mgt_lock, flags);
625 /* Grab the HW semaphore. */
626 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
629 writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
630 writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
631 writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
633 /* Release the HW semaphore. */
636 spin_unlock_irqrestore(&clk_mgt_lock, flags);
641 u32 db8500_prcmu_read(unsigned int reg)
643 return readl(prcmu_base + reg);
646 void db8500_prcmu_write(unsigned int reg, u32 value)
650 spin_lock_irqsave(&prcmu_lock, flags);
651 writel(value, (prcmu_base + reg));
652 spin_unlock_irqrestore(&prcmu_lock, flags);
655 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
660 spin_lock_irqsave(&prcmu_lock, flags);
661 val = readl(prcmu_base + reg);
662 val = ((val & ~mask) | (value & mask));
663 writel(val, (prcmu_base + reg));
664 spin_unlock_irqrestore(&prcmu_lock, flags);
667 struct prcmu_fw_version *prcmu_get_fw_version(void)
669 return fw_info.valid ? &fw_info.version : NULL;
672 bool prcmu_has_arm_maxopp(void)
674 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
675 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
679 * prcmu_set_rc_a2p - This function is used to run few power state sequences
680 * @val: Value to be set, i.e. transition requested
681 * Returns: 0 on success, -EINVAL on invalid argument
683 * This function is used to run the following power state sequences -
684 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
686 int prcmu_set_rc_a2p(enum romcode_write val)
688 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
690 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
695 * prcmu_get_rc_p2a - This function is used to get power state sequences
696 * Returns: the power transition that has last happened
698 * This function can return the following transitions-
699 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
701 enum romcode_read prcmu_get_rc_p2a(void)
703 return readb(tcdm_base + PRCM_ROMCODE_P2A);
707 * prcmu_get_current_mode - Return the current XP70 power mode
708 * Returns: Returns the current AP(ARM) power mode: init,
709 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
711 enum ap_pwrst prcmu_get_xp70_current_state(void)
713 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
717 * prcmu_config_clkout - Configure one of the programmable clock outputs.
718 * @clkout: The CLKOUT number (0 or 1).
719 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
720 * @div: The divider to be applied.
722 * Configures one of the programmable clock outputs (CLKOUTs).
723 * @div should be in the range [1,63] to request a configuration, or 0 to
724 * inform that the configuration is no longer requested.
726 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
728 static int requests[2];
738 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
740 if (!div && !requests[clkout])
744 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
745 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
746 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
747 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
749 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
750 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
751 PRCM_CLKOCR_CLK1TYPE);
752 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
753 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
757 spin_lock_irqsave(&clkout_lock, flags);
759 val = readl(PRCM_CLKOCR);
760 if (val & div_mask) {
762 if ((val & mask) != bits) {
764 goto unlock_and_return;
767 if ((val & mask & ~div_mask) != bits) {
769 goto unlock_and_return;
773 writel((bits | (val & ~mask)), PRCM_CLKOCR);
774 requests[clkout] += (div ? 1 : -1);
777 spin_unlock_irqrestore(&clkout_lock, flags);
782 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
786 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
788 spin_lock_irqsave(&mb0_transfer.lock, flags);
790 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
793 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
794 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
795 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
796 writeb((keep_ulp_clk ? 1 : 0),
797 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
798 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
799 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
801 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
806 u8 db8500_prcmu_get_power_state_result(void)
808 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
811 /* This function should only be called while mb0_transfer.lock is held. */
812 static void config_wakeups(void)
814 const u8 header[2] = {
815 MB0H_CONFIG_WAKEUPS_EXE,
816 MB0H_CONFIG_WAKEUPS_SLEEP
818 static u32 last_dbb_events;
819 static u32 last_abb_events;
824 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
825 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
827 abb_events = mb0_transfer.req.abb_events;
829 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
832 for (i = 0; i < 2; i++) {
833 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
835 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
836 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
837 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
838 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
840 last_dbb_events = dbb_events;
841 last_abb_events = abb_events;
844 void db8500_prcmu_enable_wakeups(u32 wakeups)
850 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
852 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
853 if (wakeups & BIT(i))
854 bits |= prcmu_wakeup_bit[i];
857 spin_lock_irqsave(&mb0_transfer.lock, flags);
859 mb0_transfer.req.dbb_wakeups = bits;
862 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
865 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
869 spin_lock_irqsave(&mb0_transfer.lock, flags);
871 mb0_transfer.req.abb_events = abb_events;
874 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
877 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
879 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
880 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
882 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
886 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
887 * @opp: The new ARM operating point to which transition is to be made
888 * Returns: 0 on success, non-zero on failure
890 * This function sets the the operating point of the ARM.
892 int db8500_prcmu_set_arm_opp(u8 opp)
896 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
901 mutex_lock(&mb1_transfer.lock);
903 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
906 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
907 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
908 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
910 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
911 wait_for_completion(&mb1_transfer.work);
913 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
914 (mb1_transfer.ack.arm_opp != opp))
917 mutex_unlock(&mb1_transfer.lock);
923 * db8500_prcmu_get_arm_opp - get the current ARM OPP
925 * Returns: the current ARM OPP
927 int db8500_prcmu_get_arm_opp(void)
929 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
933 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
935 * Returns: the current DDR OPP
937 int db8500_prcmu_get_ddr_opp(void)
939 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
942 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
943 static void request_even_slower_clocks(bool enable)
952 spin_lock_irqsave(&clk_mgt_lock, flags);
954 /* Grab the HW semaphore. */
955 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
958 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
962 val = readl(prcmu_base + clock_reg[i]);
963 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
965 if ((div <= 1) || (div > 15)) {
966 pr_err("prcmu: Bad clock divider %d in %s\n",
968 goto unlock_and_return;
973 goto unlock_and_return;
976 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
977 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
978 writel(val, prcmu_base + clock_reg[i]);
982 /* Release the HW semaphore. */
985 spin_unlock_irqrestore(&clk_mgt_lock, flags);
989 * db8500_set_ape_opp - set the appropriate APE OPP
990 * @opp: The new APE operating point to which transition is to be made
991 * Returns: 0 on success, non-zero on failure
993 * This function sets the operating point of the APE.
995 int db8500_prcmu_set_ape_opp(u8 opp)
999 if (opp == mb1_transfer.ape_opp)
1002 mutex_lock(&mb1_transfer.lock);
1004 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1005 request_even_slower_clocks(false);
1007 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1010 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1013 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1014 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1015 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1016 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1018 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1019 wait_for_completion(&mb1_transfer.work);
1021 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1022 (mb1_transfer.ack.ape_opp != opp))
1026 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1027 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1028 request_even_slower_clocks(true);
1030 mb1_transfer.ape_opp = opp;
1032 mutex_unlock(&mb1_transfer.lock);
1038 * db8500_prcmu_get_ape_opp - get the current APE OPP
1040 * Returns: the current APE OPP
1042 int db8500_prcmu_get_ape_opp(void)
1044 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1048 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1049 * @enable: true to request the higher voltage, false to drop a request.
1051 * Calls to this function to enable and disable requests must be balanced.
1053 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1057 static unsigned int requests;
1059 mutex_lock(&mb1_transfer.lock);
1062 if (0 != requests++)
1063 goto unlock_and_return;
1064 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1066 if (requests == 0) {
1068 goto unlock_and_return;
1069 } else if (1 != requests--) {
1070 goto unlock_and_return;
1072 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1075 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1078 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1080 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1081 wait_for_completion(&mb1_transfer.work);
1083 if ((mb1_transfer.ack.header != header) ||
1084 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1088 mutex_unlock(&mb1_transfer.lock);
1094 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1096 * This function releases the power state requirements of a USB wakeup.
1098 int prcmu_release_usb_wakeup_state(void)
1102 mutex_lock(&mb1_transfer.lock);
1104 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1107 writeb(MB1H_RELEASE_USB_WAKEUP,
1108 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1110 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1111 wait_for_completion(&mb1_transfer.work);
1113 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1114 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1117 mutex_unlock(&mb1_transfer.lock);
1122 static int request_pll(u8 clock, bool enable)
1126 if (clock == PRCMU_PLLSOC0)
1127 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1128 else if (clock == PRCMU_PLLSOC1)
1129 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1133 mutex_lock(&mb1_transfer.lock);
1135 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1138 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1139 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1141 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1142 wait_for_completion(&mb1_transfer.work);
1144 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1147 mutex_unlock(&mb1_transfer.lock);
1153 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1154 * @epod_id: The EPOD to set
1155 * @epod_state: The new EPOD state
1157 * This function sets the state of a EPOD (power domain). It may not be called
1158 * from interrupt context.
1160 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1163 bool ram_retention = false;
1166 /* check argument */
1167 BUG_ON(epod_id >= NUM_EPOD_ID);
1169 /* set flag if retention is possible */
1171 case EPOD_ID_SVAMMDSP:
1172 case EPOD_ID_SIAMMDSP:
1173 case EPOD_ID_ESRAM12:
1174 case EPOD_ID_ESRAM34:
1175 ram_retention = true;
1179 /* check argument */
1180 BUG_ON(epod_state > EPOD_STATE_ON);
1181 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1184 mutex_lock(&mb2_transfer.lock);
1186 /* wait for mailbox */
1187 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1190 /* fill in mailbox */
1191 for (i = 0; i < NUM_EPOD_ID; i++)
1192 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1193 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1195 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1197 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1200 * The current firmware version does not handle errors correctly,
1201 * and we cannot recover if there is an error.
1202 * This is expected to change when the firmware is updated.
1204 if (!wait_for_completion_timeout(&mb2_transfer.work,
1205 msecs_to_jiffies(20000))) {
1206 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1209 goto unlock_and_return;
1212 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1216 mutex_unlock(&mb2_transfer.lock);
1221 * prcmu_configure_auto_pm - Configure autonomous power management.
1222 * @sleep: Configuration for ApSleep.
1223 * @idle: Configuration for ApIdle.
1225 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1226 struct prcmu_auto_pm_config *idle)
1230 unsigned long flags;
1232 BUG_ON((sleep == NULL) || (idle == NULL));
1234 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1235 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1236 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1237 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1238 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1239 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1241 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1242 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1243 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1244 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1245 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1246 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1248 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1251 * The autonomous power management configuration is done through
1252 * fields in mailbox 2, but these fields are only used as shared
1253 * variables - i.e. there is no need to send a message.
1255 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1256 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1258 mb2_transfer.auto_pm_enabled =
1259 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1260 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1261 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1262 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1264 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1266 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1268 bool prcmu_is_auto_pm_enabled(void)
1270 return mb2_transfer.auto_pm_enabled;
1273 static int request_sysclk(bool enable)
1276 unsigned long flags;
1280 mutex_lock(&mb3_transfer.sysclk_lock);
1282 spin_lock_irqsave(&mb3_transfer.lock, flags);
1284 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1287 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1289 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1290 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1292 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1295 * The firmware only sends an ACK if we want to enable the
1296 * SysClk, and it succeeds.
1298 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1299 msecs_to_jiffies(20000))) {
1300 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1305 mutex_unlock(&mb3_transfer.sysclk_lock);
1310 static int request_timclk(bool enable)
1312 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1315 val |= PRCM_TCR_STOP_TIMERS;
1316 writel(val, PRCM_TCR);
1321 static int request_clock(u8 clock, bool enable)
1324 unsigned long flags;
1326 spin_lock_irqsave(&clk_mgt_lock, flags);
1328 /* Grab the HW semaphore. */
1329 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1332 val = readl(prcmu_base + clk_mgt[clock].offset);
1334 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1336 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1337 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1339 writel(val, prcmu_base + clk_mgt[clock].offset);
1341 /* Release the HW semaphore. */
1342 writel(0, PRCM_SEM);
1344 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1349 static int request_sga_clock(u8 clock, bool enable)
1355 val = readl(PRCM_CGATING_BYPASS);
1356 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1359 ret = request_clock(clock, enable);
1361 if (!ret && !enable) {
1362 val = readl(PRCM_CGATING_BYPASS);
1363 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1369 static inline bool plldsi_locked(void)
1371 return (readl(PRCM_PLLDSI_LOCKP) &
1372 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1373 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1374 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1375 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1378 static int request_plldsi(bool enable)
1383 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1384 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1385 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1387 val = readl(PRCM_PLLDSI_ENABLE);
1389 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1391 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1392 writel(val, PRCM_PLLDSI_ENABLE);
1396 bool locked = plldsi_locked();
1398 for (i = 10; !locked && (i > 0); --i) {
1400 locked = plldsi_locked();
1403 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1404 PRCM_APE_RESETN_SET);
1406 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1407 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1408 PRCM_MMIP_LS_CLAMP_SET);
1409 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1410 writel(val, PRCM_PLLDSI_ENABLE);
1414 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1419 static int request_dsiclk(u8 n, bool enable)
1423 val = readl(PRCM_DSI_PLLOUT_SEL);
1424 val &= ~dsiclk[n].divsel_mask;
1425 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1426 dsiclk[n].divsel_shift);
1427 writel(val, PRCM_DSI_PLLOUT_SEL);
1431 static int request_dsiescclk(u8 n, bool enable)
1435 val = readl(PRCM_DSITVCLK_DIV);
1436 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1437 writel(val, PRCM_DSITVCLK_DIV);
1442 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1443 * @clock: The clock for which the request is made.
1444 * @enable: Whether the clock should be enabled (true) or disabled (false).
1446 * This function should only be used by the clock implementation.
1447 * Do not use it from any other place!
1449 int db8500_prcmu_request_clock(u8 clock, bool enable)
1451 if (clock == PRCMU_SGACLK)
1452 return request_sga_clock(clock, enable);
1453 else if (clock < PRCMU_NUM_REG_CLOCKS)
1454 return request_clock(clock, enable);
1455 else if (clock == PRCMU_TIMCLK)
1456 return request_timclk(enable);
1457 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1458 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1459 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1460 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1461 else if (clock == PRCMU_PLLDSI)
1462 return request_plldsi(enable);
1463 else if (clock == PRCMU_SYSCLK)
1464 return request_sysclk(enable);
1465 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1466 return request_pll(clock, enable);
1471 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1482 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1484 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1488 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1492 if (val & PRCM_PLL_FREQ_SELDIV2)
1495 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1496 (val & PRCM_PLL_FREQ_DIV2EN) &&
1497 ((reg == PRCM_PLLSOC0_FREQ) ||
1498 (reg == PRCM_PLLARM_FREQ) ||
1499 (reg == PRCM_PLLDDR_FREQ))))
1502 (void)do_div(rate, div);
1504 return (unsigned long)rate;
1507 #define ROOT_CLOCK_RATE 38400000
1509 static unsigned long clock_rate(u8 clock)
1513 unsigned long rate = ROOT_CLOCK_RATE;
1515 val = readl(prcmu_base + clk_mgt[clock].offset);
1517 if (val & PRCM_CLK_MGT_CLK38) {
1518 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1523 val |= clk_mgt[clock].pllsw;
1524 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1526 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1527 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1528 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1529 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1530 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1531 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1535 if ((clock == PRCMU_SGACLK) &&
1536 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1537 u64 r = (rate * 10);
1539 (void)do_div(r, 25);
1540 return (unsigned long)r;
1542 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1549 static unsigned long armss_rate(void)
1554 r = readl(PRCM_ARM_CHGCLKREQ);
1556 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1557 /* External ARMCLKFIX clock */
1559 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1561 /* Check PRCM_ARM_CHGCLKREQ divider */
1562 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1565 /* Check PRCM_ARMCLKFIX_MGT divider */
1566 r = readl(PRCM_ARMCLKFIX_MGT);
1567 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1570 } else {/* ARM PLL */
1571 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1577 static unsigned long dsiclk_rate(u8 n)
1582 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1583 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1585 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1586 divsel = dsiclk[n].divsel;
1588 dsiclk[n].divsel = divsel;
1591 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1594 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1597 case PRCM_DSI_PLLOUT_SEL_PHI:
1598 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1605 static unsigned long dsiescclk_rate(u8 n)
1609 div = readl(PRCM_DSITVCLK_DIV);
1610 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1611 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1614 unsigned long prcmu_clock_rate(u8 clock)
1616 if (clock < PRCMU_NUM_REG_CLOCKS)
1617 return clock_rate(clock);
1618 else if (clock == PRCMU_TIMCLK)
1619 return ROOT_CLOCK_RATE / 16;
1620 else if (clock == PRCMU_SYSCLK)
1621 return ROOT_CLOCK_RATE;
1622 else if (clock == PRCMU_PLLSOC0)
1623 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1624 else if (clock == PRCMU_PLLSOC1)
1625 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1626 else if (clock == PRCMU_ARMSS)
1627 return armss_rate();
1628 else if (clock == PRCMU_PLLDDR)
1629 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1630 else if (clock == PRCMU_PLLDSI)
1631 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1633 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1634 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1635 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1636 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1641 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1643 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1644 return ROOT_CLOCK_RATE;
1645 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1646 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1647 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1648 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1649 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1650 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1651 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1656 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1660 div = (src_rate / rate);
1663 if (rate < (src_rate / div))
1668 static long round_clock_rate(u8 clock, unsigned long rate)
1672 unsigned long src_rate;
1675 val = readl(prcmu_base + clk_mgt[clock].offset);
1676 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1677 clk_mgt[clock].branch);
1678 div = clock_divider(src_rate, rate);
1679 if (val & PRCM_CLK_MGT_CLK38) {
1680 if (clk_mgt[clock].clk38div) {
1686 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1687 u64 r = (src_rate * 10);
1689 (void)do_div(r, 25);
1691 return (unsigned long)r;
1693 rounded_rate = (src_rate / min(div, (u32)31));
1695 return rounded_rate;
1698 static const unsigned long db8500_armss_freqs[] = {
1705 /* The DB8520 has slightly higher ARMSS max frequency */
1706 static const unsigned long db8520_armss_freqs[] = {
1715 static long round_armss_rate(unsigned long rate)
1717 unsigned long freq = 0;
1718 const unsigned long *freqs;
1722 if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1723 freqs = db8520_armss_freqs;
1724 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1726 freqs = db8500_armss_freqs;
1727 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1730 /* Find the corresponding arm opp from the cpufreq table. */
1731 for (i = 0; i < nfreqs; i++) {
1737 /* Return the last valid value, even if a match was not found. */
1741 #define MIN_PLL_VCO_RATE 600000000ULL
1742 #define MAX_PLL_VCO_RATE 1680640000ULL
1744 static long round_plldsi_rate(unsigned long rate)
1746 long rounded_rate = 0;
1747 unsigned long src_rate;
1751 src_rate = clock_rate(PRCMU_HDMICLK);
1754 for (r = 7; (rem > 0) && (r > 0); r--) {
1758 (void)do_div(d, src_rate);
1764 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1765 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1769 if (rounded_rate == 0)
1770 rounded_rate = (long)d;
1773 if ((rate - d) < rem) {
1775 rounded_rate = (long)d;
1778 return rounded_rate;
1781 static long round_dsiclk_rate(unsigned long rate)
1784 unsigned long src_rate;
1787 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1789 div = clock_divider(src_rate, rate);
1790 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1792 return rounded_rate;
1795 static long round_dsiescclk_rate(unsigned long rate)
1798 unsigned long src_rate;
1801 src_rate = clock_rate(PRCMU_TVCLK);
1802 div = clock_divider(src_rate, rate);
1803 rounded_rate = (src_rate / min(div, (u32)255));
1805 return rounded_rate;
1808 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1810 if (clock < PRCMU_NUM_REG_CLOCKS)
1811 return round_clock_rate(clock, rate);
1812 else if (clock == PRCMU_ARMSS)
1813 return round_armss_rate(rate);
1814 else if (clock == PRCMU_PLLDSI)
1815 return round_plldsi_rate(rate);
1816 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1817 return round_dsiclk_rate(rate);
1818 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1819 return round_dsiescclk_rate(rate);
1821 return (long)prcmu_clock_rate(clock);
1824 static void set_clock_rate(u8 clock, unsigned long rate)
1828 unsigned long src_rate;
1829 unsigned long flags;
1831 spin_lock_irqsave(&clk_mgt_lock, flags);
1833 /* Grab the HW semaphore. */
1834 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1837 val = readl(prcmu_base + clk_mgt[clock].offset);
1838 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1839 clk_mgt[clock].branch);
1840 div = clock_divider(src_rate, rate);
1841 if (val & PRCM_CLK_MGT_CLK38) {
1842 if (clk_mgt[clock].clk38div) {
1844 val |= PRCM_CLK_MGT_CLK38DIV;
1846 val &= ~PRCM_CLK_MGT_CLK38DIV;
1848 } else if (clock == PRCMU_SGACLK) {
1849 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1850 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1852 u64 r = (src_rate * 10);
1854 (void)do_div(r, 25);
1856 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1860 val |= min(div, (u32)31);
1862 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1863 val |= min(div, (u32)31);
1865 writel(val, prcmu_base + clk_mgt[clock].offset);
1867 /* Release the HW semaphore. */
1868 writel(0, PRCM_SEM);
1870 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1873 static int set_armss_rate(unsigned long rate)
1876 u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
1877 const unsigned long *freqs;
1881 if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1882 freqs = db8520_armss_freqs;
1883 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1885 freqs = db8500_armss_freqs;
1886 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1889 /* Find the corresponding arm opp from the cpufreq table. */
1890 for (i = 0; i < nfreqs; i++) {
1899 /* Set the new arm opp. */
1900 pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
1901 return db8500_prcmu_set_arm_opp(opps[i]);
1904 static int set_plldsi_rate(unsigned long rate)
1906 unsigned long src_rate;
1911 src_rate = clock_rate(PRCMU_HDMICLK);
1914 for (r = 7; (rem > 0) && (r > 0); r--) {
1919 (void)do_div(d, src_rate);
1924 hwrate = (d * src_rate);
1925 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1926 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1928 (void)do_div(hwrate, r);
1929 if (rate < hwrate) {
1931 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1932 (r << PRCM_PLL_FREQ_R_SHIFT));
1935 if ((rate - hwrate) < rem) {
1936 rem = (rate - hwrate);
1937 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1938 (r << PRCM_PLL_FREQ_R_SHIFT));
1944 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1945 writel(pll_freq, PRCM_PLLDSI_FREQ);
1950 static void set_dsiclk_rate(u8 n, unsigned long rate)
1955 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1956 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1958 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1959 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1960 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1962 val = readl(PRCM_DSI_PLLOUT_SEL);
1963 val &= ~dsiclk[n].divsel_mask;
1964 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1965 writel(val, PRCM_DSI_PLLOUT_SEL);
1968 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1973 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1974 val = readl(PRCM_DSITVCLK_DIV);
1975 val &= ~dsiescclk[n].div_mask;
1976 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1977 writel(val, PRCM_DSITVCLK_DIV);
1980 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1982 if (clock < PRCMU_NUM_REG_CLOCKS)
1983 set_clock_rate(clock, rate);
1984 else if (clock == PRCMU_ARMSS)
1985 return set_armss_rate(rate);
1986 else if (clock == PRCMU_PLLDSI)
1987 return set_plldsi_rate(rate);
1988 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1989 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1990 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1991 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1995 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1997 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1998 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2001 mutex_lock(&mb4_transfer.lock);
2003 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2006 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2007 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2008 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2009 writeb(DDR_PWR_STATE_ON,
2010 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2011 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2013 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2014 wait_for_completion(&mb4_transfer.work);
2016 mutex_unlock(&mb4_transfer.lock);
2021 int db8500_prcmu_config_hotdog(u8 threshold)
2023 mutex_lock(&mb4_transfer.lock);
2025 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2028 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2029 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2031 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2032 wait_for_completion(&mb4_transfer.work);
2034 mutex_unlock(&mb4_transfer.lock);
2039 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2041 mutex_lock(&mb4_transfer.lock);
2043 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2046 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2047 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2048 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2049 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2050 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2052 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2053 wait_for_completion(&mb4_transfer.work);
2055 mutex_unlock(&mb4_transfer.lock);
2059 EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
2061 static int config_hot_period(u16 val)
2063 mutex_lock(&mb4_transfer.lock);
2065 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2068 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2069 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2071 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2072 wait_for_completion(&mb4_transfer.work);
2074 mutex_unlock(&mb4_transfer.lock);
2079 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2081 if (cycles32k == 0xFFFF)
2084 return config_hot_period(cycles32k);
2086 EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
2088 int db8500_prcmu_stop_temp_sense(void)
2090 return config_hot_period(0xFFFF);
2092 EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
2094 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2097 mutex_lock(&mb4_transfer.lock);
2099 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2102 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2103 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2104 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2105 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2107 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2109 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2110 wait_for_completion(&mb4_transfer.work);
2112 mutex_unlock(&mb4_transfer.lock);
2118 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2120 BUG_ON(num == 0 || num > 0xf);
2121 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2122 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2123 A9WDOG_AUTO_OFF_DIS);
2125 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2127 int db8500_prcmu_enable_a9wdog(u8 id)
2129 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2131 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2133 int db8500_prcmu_disable_a9wdog(u8 id)
2135 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2137 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2139 int db8500_prcmu_kick_a9wdog(u8 id)
2141 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2143 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2146 * timeout is 28 bit, in ms.
2148 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2150 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2151 (id & A9WDOG_ID_MASK) |
2153 * Put the lowest 28 bits of timeout at
2154 * offset 4. Four first bits are used for id.
2156 (u8)((timeout << 4) & 0xf0),
2157 (u8)((timeout >> 4) & 0xff),
2158 (u8)((timeout >> 12) & 0xff),
2159 (u8)((timeout >> 20) & 0xff));
2161 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2164 * prcmu_abb_read() - Read register value(s) from the ABB.
2165 * @slave: The I2C slave address.
2166 * @reg: The (start) register address.
2167 * @value: The read out value(s).
2168 * @size: The number of registers to read.
2170 * Reads register value(s) from the ABB.
2171 * @size has to be 1 for the current firmware version.
2173 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2180 mutex_lock(&mb5_transfer.lock);
2182 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2185 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2186 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2187 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2188 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2189 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2191 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2193 if (!wait_for_completion_timeout(&mb5_transfer.work,
2194 msecs_to_jiffies(20000))) {
2195 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2199 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2203 *value = mb5_transfer.ack.value;
2205 mutex_unlock(&mb5_transfer.lock);
2211 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2212 * @slave: The I2C slave address.
2213 * @reg: The (start) register address.
2214 * @value: The value(s) to write.
2215 * @mask: The mask(s) to use.
2216 * @size: The number of registers to write.
2218 * Writes masked register value(s) to the ABB.
2219 * For each @value, only the bits set to 1 in the corresponding @mask
2220 * will be written. The other bits are not changed.
2221 * @size has to be 1 for the current firmware version.
2223 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2230 mutex_lock(&mb5_transfer.lock);
2232 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2235 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2236 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2237 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2238 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2239 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2241 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2243 if (!wait_for_completion_timeout(&mb5_transfer.work,
2244 msecs_to_jiffies(20000))) {
2245 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2249 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2252 mutex_unlock(&mb5_transfer.lock);
2258 * prcmu_abb_write() - Write register value(s) to the ABB.
2259 * @slave: The I2C slave address.
2260 * @reg: The (start) register address.
2261 * @value: The value(s) to write.
2262 * @size: The number of registers to write.
2264 * Writes register value(s) to the ABB.
2265 * @size has to be 1 for the current firmware version.
2267 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2271 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2275 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2277 int prcmu_ac_wake_req(void)
2282 mutex_lock(&mb0_transfer.ac_wake_lock);
2284 val = readl(PRCM_HOSTACCESS_REQ);
2285 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2286 goto unlock_and_return;
2288 atomic_set(&ac_wake_req_state, 1);
2291 * Force Modem Wake-up before hostaccess_req ping-pong.
2292 * It prevents Modem to enter in Sleep while acking the hostaccess
2293 * request. The 31us delay has been calculated by HWI.
2295 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2296 writel(val, PRCM_HOSTACCESS_REQ);
2300 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2301 writel(val, PRCM_HOSTACCESS_REQ);
2303 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2304 msecs_to_jiffies(5000))) {
2305 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2311 mutex_unlock(&mb0_transfer.ac_wake_lock);
2316 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2318 void prcmu_ac_sleep_req(void)
2322 mutex_lock(&mb0_transfer.ac_wake_lock);
2324 val = readl(PRCM_HOSTACCESS_REQ);
2325 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2326 goto unlock_and_return;
2328 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2329 PRCM_HOSTACCESS_REQ);
2331 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2332 msecs_to_jiffies(5000))) {
2333 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2337 atomic_set(&ac_wake_req_state, 0);
2340 mutex_unlock(&mb0_transfer.ac_wake_lock);
2343 bool db8500_prcmu_is_ac_wake_requested(void)
2345 return (atomic_read(&ac_wake_req_state) != 0);
2349 * db8500_prcmu_system_reset - System reset
2351 * Saves the reset reason code and then sets the APE_SOFTRST register which
2352 * fires interrupt to fw
2354 void db8500_prcmu_system_reset(u16 reset_code)
2356 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2357 writel(1, PRCM_APE_SOFTRST);
2361 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2363 * Retrieves the reset reason code stored by prcmu_system_reset() before
2366 u16 db8500_prcmu_get_reset_code(void)
2368 return readw(tcdm_base + PRCM_SW_RST_REASON);
2372 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2374 void db8500_prcmu_modem_reset(void)
2376 mutex_lock(&mb1_transfer.lock);
2378 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2381 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2382 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2383 wait_for_completion(&mb1_transfer.work);
2386 * No need to check return from PRCMU as modem should go in reset state
2387 * This state is already managed by upper layer
2390 mutex_unlock(&mb1_transfer.lock);
2393 static void ack_dbb_wakeup(void)
2395 unsigned long flags;
2397 spin_lock_irqsave(&mb0_transfer.lock, flags);
2399 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2402 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2403 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2405 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2408 static inline void print_unknown_header_warning(u8 n, u8 header)
2410 pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
2414 static bool read_mailbox_0(void)
2421 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2423 case MB0H_WAKEUP_EXE:
2424 case MB0H_WAKEUP_SLEEP:
2425 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2426 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2428 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2430 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2431 complete(&mb0_transfer.ac_wake_work);
2432 if (ev & WAKEUP_BIT_SYSCLK_OK)
2433 complete(&mb3_transfer.sysclk_work);
2435 ev &= mb0_transfer.req.dbb_irqs;
2437 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2438 if (ev & prcmu_irq_bit[n])
2439 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2444 print_unknown_header_warning(0, header);
2448 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2452 static bool read_mailbox_1(void)
2454 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2455 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2456 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2457 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2458 PRCM_ACK_MB1_CURRENT_APE_OPP);
2459 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2460 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2461 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2462 complete(&mb1_transfer.work);
2466 static bool read_mailbox_2(void)
2468 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2469 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2470 complete(&mb2_transfer.work);
2474 static bool read_mailbox_3(void)
2476 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2480 static bool read_mailbox_4(void)
2483 bool do_complete = true;
2485 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2490 case MB4H_HOT_PERIOD:
2491 case MB4H_A9WDOG_CONF:
2492 case MB4H_A9WDOG_EN:
2493 case MB4H_A9WDOG_DIS:
2494 case MB4H_A9WDOG_LOAD:
2495 case MB4H_A9WDOG_KICK:
2498 print_unknown_header_warning(4, header);
2499 do_complete = false;
2503 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2506 complete(&mb4_transfer.work);
2511 static bool read_mailbox_5(void)
2513 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2514 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2515 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2516 complete(&mb5_transfer.work);
2520 static bool read_mailbox_6(void)
2522 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2526 static bool read_mailbox_7(void)
2528 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2532 static bool (* const read_mailbox[NUM_MB])(void) = {
2543 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2549 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2550 if (unlikely(!bits))
2554 for (n = 0; bits; n++) {
2555 if (bits & MBOX_BIT(n)) {
2556 bits -= MBOX_BIT(n);
2557 if (read_mailbox[n]())
2558 r = IRQ_WAKE_THREAD;
2564 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2570 static void prcmu_mask_work(struct work_struct *work)
2572 unsigned long flags;
2574 spin_lock_irqsave(&mb0_transfer.lock, flags);
2578 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2581 static void prcmu_irq_mask(struct irq_data *d)
2583 unsigned long flags;
2585 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2587 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2589 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2591 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2592 schedule_work(&mb0_transfer.mask_work);
2595 static void prcmu_irq_unmask(struct irq_data *d)
2597 unsigned long flags;
2599 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2601 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2603 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2605 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2606 schedule_work(&mb0_transfer.mask_work);
2609 static void noop(struct irq_data *d)
2613 static struct irq_chip prcmu_irq_chip = {
2615 .irq_disable = prcmu_irq_mask,
2617 .irq_mask = prcmu_irq_mask,
2618 .irq_unmask = prcmu_irq_unmask,
2621 static char *fw_project_name(u32 project)
2624 case PRCMU_FW_PROJECT_U8500:
2626 case PRCMU_FW_PROJECT_U8400:
2628 case PRCMU_FW_PROJECT_U9500:
2630 case PRCMU_FW_PROJECT_U8500_MBB:
2632 case PRCMU_FW_PROJECT_U8500_C1:
2634 case PRCMU_FW_PROJECT_U8500_C2:
2636 case PRCMU_FW_PROJECT_U8500_C3:
2638 case PRCMU_FW_PROJECT_U8500_C4:
2640 case PRCMU_FW_PROJECT_U9500_MBL:
2642 case PRCMU_FW_PROJECT_U8500_MBL:
2644 case PRCMU_FW_PROJECT_U8500_MBL2:
2645 return "U8500 MBL2";
2646 case PRCMU_FW_PROJECT_U8520:
2648 case PRCMU_FW_PROJECT_U8420:
2650 case PRCMU_FW_PROJECT_U9540:
2652 case PRCMU_FW_PROJECT_A9420:
2654 case PRCMU_FW_PROJECT_L8540:
2656 case PRCMU_FW_PROJECT_L8580:
2663 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2664 irq_hw_number_t hwirq)
2666 irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2672 static const struct irq_domain_ops db8500_irq_ops = {
2673 .map = db8500_irq_map,
2674 .xlate = irq_domain_xlate_twocell,
2677 static int db8500_irq_init(struct device_node *np)
2681 db8500_irq_domain = irq_domain_add_simple(
2682 np, NUM_PRCMU_WAKEUPS, 0,
2683 &db8500_irq_ops, NULL);
2685 if (!db8500_irq_domain) {
2686 pr_err("Failed to create irqdomain\n");
2690 /* All wakeups will be used, so create mappings for all */
2691 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2692 irq_create_mapping(db8500_irq_domain, i);
2697 static void dbx500_fw_version_init(struct platform_device *pdev,
2700 struct resource *res;
2701 void __iomem *tcpm_base;
2704 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2708 "Error: no prcmu tcpm memory region provided\n");
2711 tcpm_base = ioremap(res->start, resource_size(res));
2713 dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
2717 version = readl(tcpm_base + version_offset);
2718 fw_info.version.project = (version & 0xFF);
2719 fw_info.version.api_version = (version >> 8) & 0xFF;
2720 fw_info.version.func_version = (version >> 16) & 0xFF;
2721 fw_info.version.errata = (version >> 24) & 0xFF;
2722 strncpy(fw_info.version.project_name,
2723 fw_project_name(fw_info.version.project),
2724 PRCMU_FW_PROJECT_NAME_LEN);
2725 fw_info.valid = true;
2726 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2727 fw_info.version.project_name,
2728 fw_info.version.project,
2729 fw_info.version.api_version,
2730 fw_info.version.func_version,
2731 fw_info.version.errata);
2735 void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2738 * This is a temporary remap to bring up the clocks. It is
2739 * subsequently replaces with a real remap. After the merge of
2740 * the mailbox subsystem all of this early code goes away, and the
2741 * clock driver can probe independently. An early initcall will
2742 * still be needed, but it can be diverted into drivers/clk/ux500.
2744 prcmu_base = ioremap(phy_base, size);
2746 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2748 spin_lock_init(&mb0_transfer.lock);
2749 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2750 mutex_init(&mb0_transfer.ac_wake_lock);
2751 init_completion(&mb0_transfer.ac_wake_work);
2752 mutex_init(&mb1_transfer.lock);
2753 init_completion(&mb1_transfer.work);
2754 mb1_transfer.ape_opp = APE_NO_CHANGE;
2755 mutex_init(&mb2_transfer.lock);
2756 init_completion(&mb2_transfer.work);
2757 spin_lock_init(&mb2_transfer.auto_pm_lock);
2758 spin_lock_init(&mb3_transfer.lock);
2759 mutex_init(&mb3_transfer.sysclk_lock);
2760 init_completion(&mb3_transfer.sysclk_work);
2761 mutex_init(&mb4_transfer.lock);
2762 init_completion(&mb4_transfer.work);
2763 mutex_init(&mb5_transfer.lock);
2764 init_completion(&mb5_transfer.work);
2766 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2769 static void init_prcm_registers(void)
2773 val = readl(PRCM_A9PL_FORCE_CLKEN);
2774 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2775 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2776 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2780 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2782 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2783 REGULATOR_SUPPLY("v-ape", NULL),
2784 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2785 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2786 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2787 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2788 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2789 /* "v-mmc" changed to "vcore" in the mainline kernel */
2790 REGULATOR_SUPPLY("vcore", "sdi0"),
2791 REGULATOR_SUPPLY("vcore", "sdi1"),
2792 REGULATOR_SUPPLY("vcore", "sdi2"),
2793 REGULATOR_SUPPLY("vcore", "sdi3"),
2794 REGULATOR_SUPPLY("vcore", "sdi4"),
2795 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2796 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2797 /* "v-uart" changed to "vcore" in the mainline kernel */
2798 REGULATOR_SUPPLY("vcore", "uart0"),
2799 REGULATOR_SUPPLY("vcore", "uart1"),
2800 REGULATOR_SUPPLY("vcore", "uart2"),
2801 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2802 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2803 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2806 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2807 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2808 /* AV8100 regulator */
2809 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2812 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2813 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2814 REGULATOR_SUPPLY("vsupply", "mcde"),
2817 /* SVA MMDSP regulator switch */
2818 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2819 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2822 /* SVA pipe regulator switch */
2823 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2824 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2827 /* SIA MMDSP regulator switch */
2828 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2829 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2832 /* SIA pipe regulator switch */
2833 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2834 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2837 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2838 REGULATOR_SUPPLY("v-mali", NULL),
2841 /* ESRAM1 and 2 regulator switch */
2842 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2843 REGULATOR_SUPPLY("esram12", "cm_control"),
2846 /* ESRAM3 and 4 regulator switch */
2847 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2848 REGULATOR_SUPPLY("v-esram34", "mcde"),
2849 REGULATOR_SUPPLY("esram34", "cm_control"),
2850 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2853 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2854 [DB8500_REGULATOR_VAPE] = {
2856 .name = "db8500-vape",
2857 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2860 .consumer_supplies = db8500_vape_consumers,
2861 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2863 [DB8500_REGULATOR_VARM] = {
2865 .name = "db8500-varm",
2866 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2869 [DB8500_REGULATOR_VMODEM] = {
2871 .name = "db8500-vmodem",
2872 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2875 [DB8500_REGULATOR_VPLL] = {
2877 .name = "db8500-vpll",
2878 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2881 [DB8500_REGULATOR_VSMPS1] = {
2883 .name = "db8500-vsmps1",
2884 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2887 [DB8500_REGULATOR_VSMPS2] = {
2889 .name = "db8500-vsmps2",
2890 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2892 .consumer_supplies = db8500_vsmps2_consumers,
2893 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2895 [DB8500_REGULATOR_VSMPS3] = {
2897 .name = "db8500-vsmps3",
2898 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2901 [DB8500_REGULATOR_VRF1] = {
2903 .name = "db8500-vrf1",
2904 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2907 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2908 /* dependency to u8500-vape is handled outside regulator framework */
2910 .name = "db8500-sva-mmdsp",
2911 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2913 .consumer_supplies = db8500_svammdsp_consumers,
2914 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2916 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2918 /* "ret" means "retention" */
2919 .name = "db8500-sva-mmdsp-ret",
2920 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2923 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2924 /* dependency to u8500-vape is handled outside regulator framework */
2926 .name = "db8500-sva-pipe",
2927 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2929 .consumer_supplies = db8500_svapipe_consumers,
2930 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2932 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2933 /* dependency to u8500-vape is handled outside regulator framework */
2935 .name = "db8500-sia-mmdsp",
2936 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2938 .consumer_supplies = db8500_siammdsp_consumers,
2939 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2941 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2943 .name = "db8500-sia-mmdsp-ret",
2944 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2947 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2948 /* dependency to u8500-vape is handled outside regulator framework */
2950 .name = "db8500-sia-pipe",
2951 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2953 .consumer_supplies = db8500_siapipe_consumers,
2954 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2956 [DB8500_REGULATOR_SWITCH_SGA] = {
2957 .supply_regulator = "db8500-vape",
2959 .name = "db8500-sga",
2960 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2962 .consumer_supplies = db8500_sga_consumers,
2963 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2966 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2967 .supply_regulator = "db8500-vape",
2969 .name = "db8500-b2r2-mcde",
2970 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2972 .consumer_supplies = db8500_b2r2_mcde_consumers,
2973 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2975 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2977 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2978 * no need to hold Vape
2981 .name = "db8500-esram12",
2982 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2984 .consumer_supplies = db8500_esram12_consumers,
2985 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2987 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2989 .name = "db8500-esram12-ret",
2990 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2993 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2995 * esram34 is set in retention and supplied by Vsafe when Vape is off,
2996 * no need to hold Vape
2999 .name = "db8500-esram34",
3000 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3002 .consumer_supplies = db8500_esram34_consumers,
3003 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3005 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3007 .name = "db8500-esram34-ret",
3008 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3013 static struct ux500_wdt_data db8500_wdt_pdata = {
3014 .timeout = 600, /* 10 minutes */
3015 .has_28_bits_resolution = true,
3021 static struct resource db8500_thsens_resources[] = {
3023 .name = "IRQ_HOTMON_LOW",
3024 .start = IRQ_PRCMU_HOTMON_LOW,
3025 .end = IRQ_PRCMU_HOTMON_LOW,
3026 .flags = IORESOURCE_IRQ,
3029 .name = "IRQ_HOTMON_HIGH",
3030 .start = IRQ_PRCMU_HOTMON_HIGH,
3031 .end = IRQ_PRCMU_HOTMON_HIGH,
3032 .flags = IORESOURCE_IRQ,
3036 static struct db8500_thsens_platform_data db8500_thsens_data = {
3039 .type = THERMAL_TRIP_ACTIVE,
3041 [0] = "thermal-cpufreq-0",
3046 .type = THERMAL_TRIP_ACTIVE,
3048 [0] = "thermal-cpufreq-0",
3053 .type = THERMAL_TRIP_ACTIVE,
3055 [0] = "thermal-cpufreq-0",
3060 .type = THERMAL_TRIP_CRITICAL,
3065 static const struct mfd_cell common_prcmu_devs[] = {
3067 .name = "ux500_wdt",
3068 .platform_data = &db8500_wdt_pdata,
3069 .pdata_size = sizeof(db8500_wdt_pdata),
3074 static const struct mfd_cell db8500_prcmu_devs[] = {
3076 .name = "db8500-prcmu-regulators",
3077 .of_compatible = "stericsson,db8500-prcmu-regulator",
3078 .platform_data = &db8500_regulators,
3079 .pdata_size = sizeof(db8500_regulators),
3082 .name = "cpuidle-dbx500",
3083 .of_compatible = "stericsson,cpuidle-dbx500",
3086 .name = "db8500-thermal",
3087 .num_resources = ARRAY_SIZE(db8500_thsens_resources),
3088 .resources = db8500_thsens_resources,
3089 .platform_data = &db8500_thsens_data,
3090 .pdata_size = sizeof(db8500_thsens_data),
3094 static int db8500_prcmu_register_ab8500(struct device *parent)
3096 struct device_node *np;
3097 struct resource ab8500_resource;
3098 const struct mfd_cell ab8500_cell = {
3099 .name = "ab8500-core",
3100 .of_compatible = "stericsson,ab8500",
3101 .id = AB8500_VERSION_AB8500,
3102 .resources = &ab8500_resource,
3106 if (!parent->of_node)
3109 /* Look up the device node, sneak the IRQ out of it */
3110 for_each_child_of_node(parent->of_node, np) {
3111 if (of_device_is_compatible(np, ab8500_cell.of_compatible))
3115 dev_info(parent, "could not find AB8500 node in the device tree\n");
3118 of_irq_to_resource_table(np, &ab8500_resource, 1);
3120 return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3124 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3127 static int db8500_prcmu_probe(struct platform_device *pdev)
3129 struct device_node *np = pdev->dev.of_node;
3130 int irq = 0, err = 0;
3131 struct resource *res;
3133 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3135 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3138 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3141 "failed to ioremap prcmu register memory\n");
3144 init_prcm_registers();
3145 dbx500_fw_version_init(pdev, DB8500_PRCMU_FW_VERSION_OFFSET);
3146 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3148 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3151 tcdm_base = devm_ioremap(&pdev->dev, res->start,
3152 resource_size(res));
3155 "failed to ioremap prcmu-tcdm register memory\n");
3159 /* Clean up the mailbox interrupts after pre-kernel code. */
3160 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3162 irq = platform_get_irq(pdev, 0);
3166 err = request_threaded_irq(irq, prcmu_irq_handler,
3167 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3169 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3173 db8500_irq_init(np);
3175 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3177 err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3178 ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3180 pr_err("prcmu: Failed to add subdevices\n");
3184 /* TODO: Remove restriction when clk definitions are available. */
3185 if (!of_machine_is_compatible("st-ericsson,u8540")) {
3186 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3187 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3190 mfd_remove_devices(&pdev->dev);
3191 pr_err("prcmu: Failed to add subdevices\n");
3196 err = db8500_prcmu_register_ab8500(&pdev->dev);
3198 mfd_remove_devices(&pdev->dev);
3199 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3203 pr_info("DB8500 PRCMU initialized\n");
3206 static const struct of_device_id db8500_prcmu_match[] = {
3207 { .compatible = "stericsson,db8500-prcmu"},
3211 static struct platform_driver db8500_prcmu_driver = {
3213 .name = "db8500-prcmu",
3214 .of_match_table = db8500_prcmu_match,
3216 .probe = db8500_prcmu_probe,
3219 static int __init db8500_prcmu_init(void)
3221 return platform_driver_register(&db8500_prcmu_driver);
3223 core_initcall(db8500_prcmu_init);