1 // SPDX-License-Identifier: GPL-2.0-only
3 * DB8500 PRCM Unit driver
5 * Copyright (C) STMicroelectronics 2009
6 * Copyright (C) ST-Ericsson SA 2010
8 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
9 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
10 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
12 * U8500 PRCM Unit interface driver
14 #include <linux/init.h>
15 #include <linux/export.h>
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/spinlock.h>
22 #include <linux/slab.h>
23 #include <linux/mutex.h>
24 #include <linux/completion.h>
25 #include <linux/irq.h>
26 #include <linux/jiffies.h>
27 #include <linux/bitops.h>
30 #include <linux/of_address.h>
31 #include <linux/of_irq.h>
32 #include <linux/platform_device.h>
33 #include <linux/uaccess.h>
34 #include <linux/mfd/core.h>
35 #include <linux/mfd/dbx500-prcmu.h>
36 #include <linux/mfd/abx500/ab8500.h>
37 #include <linux/regulator/db8500-prcmu.h>
38 #include <linux/regulator/machine.h>
39 #include <linux/platform_data/ux500_wdt.h>
40 #include "dbx500-prcmu-regs.h"
42 /* Index of different voltages to be used when accessing AVSData */
43 #define PRCM_AVS_BASE 0x2FC
44 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
45 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
46 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
47 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
48 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
49 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
50 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
51 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
52 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
53 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
54 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
55 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
56 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
58 #define PRCM_AVS_VOLTAGE 0
59 #define PRCM_AVS_VOLTAGE_MASK 0x3f
60 #define PRCM_AVS_ISSLOWSTARTUP 6
61 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
62 #define PRCM_AVS_ISMODEENABLE 7
63 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
65 #define PRCM_BOOT_STATUS 0xFFF
66 #define PRCM_ROMCODE_A2P 0xFFE
67 #define PRCM_ROMCODE_P2A 0xFFD
68 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
70 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
72 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
73 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
74 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
75 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
76 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
77 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
78 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
79 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
82 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
83 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
84 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
85 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
86 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
87 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
90 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
91 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
92 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
93 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
94 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
95 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
97 /* Mailbox 0 headers */
98 #define MB0H_POWER_STATE_TRANS 0
99 #define MB0H_CONFIG_WAKEUPS_EXE 1
100 #define MB0H_READ_WAKEUP_ACK 3
101 #define MB0H_CONFIG_WAKEUPS_SLEEP 4
103 #define MB0H_WAKEUP_EXE 2
104 #define MB0H_WAKEUP_SLEEP 5
107 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
108 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
109 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
110 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
111 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
112 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
115 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
116 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
117 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
118 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
119 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
120 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
121 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
123 /* Mailbox 1 headers */
124 #define MB1H_ARM_APE_OPP 0x0
125 #define MB1H_RESET_MODEM 0x2
126 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
127 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
128 #define MB1H_RELEASE_USB_WAKEUP 0x5
129 #define MB1H_PLL_ON_OFF 0x6
131 /* Mailbox 1 Requests */
132 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
133 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
134 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
135 #define PLL_SOC0_OFF 0x1
136 #define PLL_SOC0_ON 0x2
137 #define PLL_SOC1_OFF 0x4
138 #define PLL_SOC1_ON 0x8
141 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
142 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
143 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
144 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
146 /* Mailbox 2 headers */
148 #define MB2H_AUTO_PWR 0x1
151 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
152 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
153 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
154 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
155 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
156 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
157 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
158 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
159 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
160 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
163 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
164 #define HWACC_PWR_ST_OK 0xFE
166 /* Mailbox 3 headers */
168 #define MB3H_SIDETONE 0x1
169 #define MB3H_SYSCLK 0xE
171 /* Mailbox 3 Requests */
172 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
173 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
174 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
175 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
176 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
177 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
178 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
180 /* Mailbox 4 headers */
181 #define MB4H_DDR_INIT 0x0
182 #define MB4H_MEM_ST 0x1
183 #define MB4H_HOTDOG 0x12
184 #define MB4H_HOTMON 0x13
185 #define MB4H_HOT_PERIOD 0x14
186 #define MB4H_A9WDOG_CONF 0x16
187 #define MB4H_A9WDOG_EN 0x17
188 #define MB4H_A9WDOG_DIS 0x18
189 #define MB4H_A9WDOG_LOAD 0x19
190 #define MB4H_A9WDOG_KICK 0x20
192 /* Mailbox 4 Requests */
193 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
194 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
195 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
196 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
197 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
198 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
199 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
200 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
201 #define HOTMON_CONFIG_LOW BIT(0)
202 #define HOTMON_CONFIG_HIGH BIT(1)
203 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
204 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
205 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
206 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
207 #define A9WDOG_AUTO_OFF_EN BIT(7)
208 #define A9WDOG_AUTO_OFF_DIS 0
209 #define A9WDOG_ID_MASK 0xf
211 /* Mailbox 5 Requests */
212 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
213 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
214 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
215 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
216 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
217 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
218 #define PRCMU_I2C_STOP_EN BIT(3)
221 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
222 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
223 #define I2C_WR_OK 0x1
224 #define I2C_RD_OK 0x2
228 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
234 #define WAKEUP_BIT_RTC BIT(0)
235 #define WAKEUP_BIT_RTT0 BIT(1)
236 #define WAKEUP_BIT_RTT1 BIT(2)
237 #define WAKEUP_BIT_HSI0 BIT(3)
238 #define WAKEUP_BIT_HSI1 BIT(4)
239 #define WAKEUP_BIT_CA_WAKE BIT(5)
240 #define WAKEUP_BIT_USB BIT(6)
241 #define WAKEUP_BIT_ABB BIT(7)
242 #define WAKEUP_BIT_ABB_FIFO BIT(8)
243 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
244 #define WAKEUP_BIT_CA_SLEEP BIT(10)
245 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
246 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
247 #define WAKEUP_BIT_ANC_OK BIT(13)
248 #define WAKEUP_BIT_SW_ERROR BIT(14)
249 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
250 #define WAKEUP_BIT_ARM BIT(17)
251 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
252 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
253 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
254 #define WAKEUP_BIT_GPIO0 BIT(23)
255 #define WAKEUP_BIT_GPIO1 BIT(24)
256 #define WAKEUP_BIT_GPIO2 BIT(25)
257 #define WAKEUP_BIT_GPIO3 BIT(26)
258 #define WAKEUP_BIT_GPIO4 BIT(27)
259 #define WAKEUP_BIT_GPIO5 BIT(28)
260 #define WAKEUP_BIT_GPIO6 BIT(29)
261 #define WAKEUP_BIT_GPIO7 BIT(30)
262 #define WAKEUP_BIT_GPIO8 BIT(31)
266 struct prcmu_fw_version version;
269 static struct irq_domain *db8500_irq_domain;
272 * This vector maps irq numbers to the bits in the bit field used in
273 * communication with the PRCMU firmware.
275 * The reason for having this is to keep the irq numbers contiguous even though
276 * the bits in the bit field are not. (The bits also have a tendency to move
277 * around, to further complicate matters.)
279 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
280 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
282 #define IRQ_PRCMU_RTC 0
283 #define IRQ_PRCMU_RTT0 1
284 #define IRQ_PRCMU_RTT1 2
285 #define IRQ_PRCMU_HSI0 3
286 #define IRQ_PRCMU_HSI1 4
287 #define IRQ_PRCMU_CA_WAKE 5
288 #define IRQ_PRCMU_USB 6
289 #define IRQ_PRCMU_ABB 7
290 #define IRQ_PRCMU_ABB_FIFO 8
291 #define IRQ_PRCMU_ARM 9
292 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
293 #define IRQ_PRCMU_GPIO0 11
294 #define IRQ_PRCMU_GPIO1 12
295 #define IRQ_PRCMU_GPIO2 13
296 #define IRQ_PRCMU_GPIO3 14
297 #define IRQ_PRCMU_GPIO4 15
298 #define IRQ_PRCMU_GPIO5 16
299 #define IRQ_PRCMU_GPIO6 17
300 #define IRQ_PRCMU_GPIO7 18
301 #define IRQ_PRCMU_GPIO8 19
302 #define IRQ_PRCMU_CA_SLEEP 20
303 #define IRQ_PRCMU_HOTMON_LOW 21
304 #define IRQ_PRCMU_HOTMON_HIGH 22
305 #define NUM_PRCMU_WAKEUPS 23
307 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
319 IRQ_ENTRY(HOTMON_LOW),
320 IRQ_ENTRY(HOTMON_HIGH),
321 IRQ_ENTRY(MODEM_SW_RESET_REQ),
333 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
334 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
335 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
343 WAKEUP_ENTRY(ABB_FIFO),
348 * mb0_transfer - state needed for mailbox 0 communication.
349 * @lock: The transaction lock.
350 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
352 * @mask_work: Work structure used for (un)masking wakeup interrupts.
353 * @req: Request data that need to persist between requests.
357 spinlock_t dbb_irqs_lock;
358 struct work_struct mask_work;
359 struct mutex ac_wake_lock;
360 struct completion ac_wake_work;
369 * mb1_transfer - state needed for mailbox 1 communication.
370 * @lock: The transaction lock.
371 * @work: The transaction completion structure.
372 * @ape_opp: The current APE OPP.
373 * @ack: Reply ("acknowledge") data.
377 struct completion work;
383 u8 ape_voltage_status;
388 * mb2_transfer - state needed for mailbox 2 communication.
389 * @lock: The transaction lock.
390 * @work: The transaction completion structure.
391 * @auto_pm_lock: The autonomous power management configuration lock.
392 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
393 * @req: Request data that need to persist between requests.
394 * @ack: Reply ("acknowledge") data.
398 struct completion work;
399 spinlock_t auto_pm_lock;
400 bool auto_pm_enabled;
407 * mb3_transfer - state needed for mailbox 3 communication.
408 * @lock: The request lock.
409 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
410 * @sysclk_work: Work structure used for sysclk requests.
414 struct mutex sysclk_lock;
415 struct completion sysclk_work;
419 * mb4_transfer - state needed for mailbox 4 communication.
420 * @lock: The transaction lock.
421 * @work: The transaction completion structure.
425 struct completion work;
429 * mb5_transfer - state needed for mailbox 5 communication.
430 * @lock: The transaction lock.
431 * @work: The transaction completion structure.
432 * @ack: Reply ("acknowledge") data.
436 struct completion work;
443 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
446 static DEFINE_SPINLOCK(prcmu_lock);
447 static DEFINE_SPINLOCK(clkout_lock);
449 /* Global var to runtime determine TCDM base for v2 or v1 */
450 static __iomem void *tcdm_base;
451 static __iomem void *prcmu_base;
466 static DEFINE_SPINLOCK(clk_mgt_lock);
468 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
469 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
470 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
471 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
472 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
474 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
475 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
476 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
477 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
478 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
483 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
485 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
486 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
487 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
488 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
489 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
490 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
491 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
492 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
493 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
494 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
495 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
496 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
497 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
498 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
499 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
508 static struct dsiclk dsiclk[2] = {
510 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
511 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
512 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
515 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
516 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
517 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
527 static struct dsiescclk dsiescclk[3] = {
529 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
530 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
531 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
534 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
535 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
536 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
539 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
540 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
541 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
547 * Used by MCDE to setup all necessary PRCMU registers
549 #define PRCMU_RESET_DSIPLL 0x00004000
550 #define PRCMU_UNCLAMP_DSIPLL 0x00400800
552 #define PRCMU_CLK_PLL_DIV_SHIFT 0
553 #define PRCMU_CLK_PLL_SW_SHIFT 5
554 #define PRCMU_CLK_38 (1 << 9)
555 #define PRCMU_CLK_38_SRC (1 << 10)
556 #define PRCMU_CLK_38_DIV (1 << 11)
558 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
559 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C
561 /* DPI 50000000 Hz */
562 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
563 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
564 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
566 /* D=101, N=1, R=4, SELDIV2=0 */
567 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
569 #define PRCMU_ENABLE_PLLDSI 0x00000001
570 #define PRCMU_DISABLE_PLLDSI 0x00000000
571 #define PRCMU_RELEASE_RESET_DSS 0x0000400C
572 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
573 /* ESC clk, div0=1, div1=1, div2=3 */
574 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
575 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
576 #define PRCMU_DSI_RESET_SW 0x00000007
578 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
580 int db8500_prcmu_enable_dsipll(void)
584 /* Clear DSIPLL_RESETN */
585 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
586 /* Unclamp DSIPLL in/out */
587 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
589 /* Set DSI PLL FREQ */
590 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
591 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
592 /* Enable Escape clocks */
593 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
596 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
598 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
599 for (i = 0; i < 10; i++) {
600 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
601 == PRCMU_PLLDSI_LOCKP_LOCKED)
605 /* Set DSIPLL_RESETN */
606 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
610 int db8500_prcmu_disable_dsipll(void)
612 /* Disable dsi pll */
613 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
614 /* Disable escapeclock */
615 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
619 int db8500_prcmu_set_display_clocks(void)
623 spin_lock_irqsave(&clk_mgt_lock, flags);
625 /* Grab the HW semaphore. */
626 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
629 writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
630 writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
631 writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
633 /* Release the HW semaphore. */
636 spin_unlock_irqrestore(&clk_mgt_lock, flags);
641 u32 db8500_prcmu_read(unsigned int reg)
643 return readl(prcmu_base + reg);
646 void db8500_prcmu_write(unsigned int reg, u32 value)
650 spin_lock_irqsave(&prcmu_lock, flags);
651 writel(value, (prcmu_base + reg));
652 spin_unlock_irqrestore(&prcmu_lock, flags);
655 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
660 spin_lock_irqsave(&prcmu_lock, flags);
661 val = readl(prcmu_base + reg);
662 val = ((val & ~mask) | (value & mask));
663 writel(val, (prcmu_base + reg));
664 spin_unlock_irqrestore(&prcmu_lock, flags);
667 struct prcmu_fw_version *prcmu_get_fw_version(void)
669 return fw_info.valid ? &fw_info.version : NULL;
672 static bool prcmu_is_ulppll_disabled(void)
674 struct prcmu_fw_version *ver;
676 ver = prcmu_get_fw_version();
677 return ver && ver->project == PRCMU_FW_PROJECT_U8420_SYSCLK;
680 bool prcmu_has_arm_maxopp(void)
682 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
683 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
687 * prcmu_set_rc_a2p - This function is used to run few power state sequences
688 * @val: Value to be set, i.e. transition requested
689 * Returns: 0 on success, -EINVAL on invalid argument
691 * This function is used to run the following power state sequences -
692 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
694 int prcmu_set_rc_a2p(enum romcode_write val)
696 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
698 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
703 * prcmu_get_rc_p2a - This function is used to get power state sequences
704 * Returns: the power transition that has last happened
706 * This function can return the following transitions-
707 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
709 enum romcode_read prcmu_get_rc_p2a(void)
711 return readb(tcdm_base + PRCM_ROMCODE_P2A);
715 * prcmu_get_current_mode - Return the current XP70 power mode
716 * Returns: Returns the current AP(ARM) power mode: init,
717 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
719 enum ap_pwrst prcmu_get_xp70_current_state(void)
721 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
725 * prcmu_config_clkout - Configure one of the programmable clock outputs.
726 * @clkout: The CLKOUT number (0 or 1).
727 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
728 * @div: The divider to be applied.
730 * Configures one of the programmable clock outputs (CLKOUTs).
731 * @div should be in the range [1,63] to request a configuration, or 0 to
732 * inform that the configuration is no longer requested.
734 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
736 static int requests[2];
746 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
748 if (!div && !requests[clkout])
752 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
753 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
754 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
755 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
757 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
758 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
759 PRCM_CLKOCR_CLK1TYPE);
760 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
761 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
765 spin_lock_irqsave(&clkout_lock, flags);
767 val = readl(PRCM_CLKOCR);
768 if (val & div_mask) {
770 if ((val & mask) != bits) {
772 goto unlock_and_return;
775 if ((val & mask & ~div_mask) != bits) {
777 goto unlock_and_return;
781 writel((bits | (val & ~mask)), PRCM_CLKOCR);
782 requests[clkout] += (div ? 1 : -1);
785 spin_unlock_irqrestore(&clkout_lock, flags);
790 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
794 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
796 spin_lock_irqsave(&mb0_transfer.lock, flags);
798 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
801 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
802 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
803 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
804 writeb((keep_ulp_clk ? 1 : 0),
805 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
806 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
807 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
809 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
814 u8 db8500_prcmu_get_power_state_result(void)
816 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
819 /* This function should only be called while mb0_transfer.lock is held. */
820 static void config_wakeups(void)
822 const u8 header[2] = {
823 MB0H_CONFIG_WAKEUPS_EXE,
824 MB0H_CONFIG_WAKEUPS_SLEEP
826 static u32 last_dbb_events;
827 static u32 last_abb_events;
832 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
833 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
835 abb_events = mb0_transfer.req.abb_events;
837 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
840 for (i = 0; i < 2; i++) {
841 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
843 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
844 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
845 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
846 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
848 last_dbb_events = dbb_events;
849 last_abb_events = abb_events;
852 void db8500_prcmu_enable_wakeups(u32 wakeups)
858 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
860 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
861 if (wakeups & BIT(i))
862 bits |= prcmu_wakeup_bit[i];
865 spin_lock_irqsave(&mb0_transfer.lock, flags);
867 mb0_transfer.req.dbb_wakeups = bits;
870 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
873 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
877 spin_lock_irqsave(&mb0_transfer.lock, flags);
879 mb0_transfer.req.abb_events = abb_events;
882 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
885 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
887 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
888 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
890 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
894 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
895 * @opp: The new ARM operating point to which transition is to be made
896 * Returns: 0 on success, non-zero on failure
898 * This function sets the the operating point of the ARM.
900 int db8500_prcmu_set_arm_opp(u8 opp)
904 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
909 mutex_lock(&mb1_transfer.lock);
911 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
914 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
915 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
916 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
918 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
919 wait_for_completion(&mb1_transfer.work);
921 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
922 (mb1_transfer.ack.arm_opp != opp))
925 mutex_unlock(&mb1_transfer.lock);
931 * db8500_prcmu_get_arm_opp - get the current ARM OPP
933 * Returns: the current ARM OPP
935 int db8500_prcmu_get_arm_opp(void)
937 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
941 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
943 * Returns: the current DDR OPP
945 int db8500_prcmu_get_ddr_opp(void)
947 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
950 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
951 static void request_even_slower_clocks(bool enable)
960 spin_lock_irqsave(&clk_mgt_lock, flags);
962 /* Grab the HW semaphore. */
963 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
966 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
970 val = readl(prcmu_base + clock_reg[i]);
971 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
973 if ((div <= 1) || (div > 15)) {
974 pr_err("prcmu: Bad clock divider %d in %s\n",
976 goto unlock_and_return;
981 goto unlock_and_return;
984 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
985 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
986 writel(val, prcmu_base + clock_reg[i]);
990 /* Release the HW semaphore. */
993 spin_unlock_irqrestore(&clk_mgt_lock, flags);
997 * db8500_set_ape_opp - set the appropriate APE OPP
998 * @opp: The new APE operating point to which transition is to be made
999 * Returns: 0 on success, non-zero on failure
1001 * This function sets the operating point of the APE.
1003 int db8500_prcmu_set_ape_opp(u8 opp)
1007 if (opp == mb1_transfer.ape_opp)
1010 mutex_lock(&mb1_transfer.lock);
1012 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1013 request_even_slower_clocks(false);
1015 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1018 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1021 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1022 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1023 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1024 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1026 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1027 wait_for_completion(&mb1_transfer.work);
1029 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1030 (mb1_transfer.ack.ape_opp != opp))
1034 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1035 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1036 request_even_slower_clocks(true);
1038 mb1_transfer.ape_opp = opp;
1040 mutex_unlock(&mb1_transfer.lock);
1046 * db8500_prcmu_get_ape_opp - get the current APE OPP
1048 * Returns: the current APE OPP
1050 int db8500_prcmu_get_ape_opp(void)
1052 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1056 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1057 * @enable: true to request the higher voltage, false to drop a request.
1059 * Calls to this function to enable and disable requests must be balanced.
1061 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1065 static unsigned int requests;
1067 mutex_lock(&mb1_transfer.lock);
1070 if (0 != requests++)
1071 goto unlock_and_return;
1072 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1074 if (requests == 0) {
1076 goto unlock_and_return;
1077 } else if (1 != requests--) {
1078 goto unlock_and_return;
1080 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1083 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1086 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1088 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1089 wait_for_completion(&mb1_transfer.work);
1091 if ((mb1_transfer.ack.header != header) ||
1092 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1096 mutex_unlock(&mb1_transfer.lock);
1102 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1104 * This function releases the power state requirements of a USB wakeup.
1106 int prcmu_release_usb_wakeup_state(void)
1110 mutex_lock(&mb1_transfer.lock);
1112 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1115 writeb(MB1H_RELEASE_USB_WAKEUP,
1116 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1118 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1119 wait_for_completion(&mb1_transfer.work);
1121 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1122 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1125 mutex_unlock(&mb1_transfer.lock);
1130 static int request_pll(u8 clock, bool enable)
1134 if (clock == PRCMU_PLLSOC0)
1135 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1136 else if (clock == PRCMU_PLLSOC1)
1137 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1141 mutex_lock(&mb1_transfer.lock);
1143 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1146 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1147 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1149 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1150 wait_for_completion(&mb1_transfer.work);
1152 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1155 mutex_unlock(&mb1_transfer.lock);
1161 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1162 * @epod_id: The EPOD to set
1163 * @epod_state: The new EPOD state
1165 * This function sets the state of a EPOD (power domain). It may not be called
1166 * from interrupt context.
1168 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1171 bool ram_retention = false;
1174 /* check argument */
1175 BUG_ON(epod_id >= NUM_EPOD_ID);
1177 /* set flag if retention is possible */
1179 case EPOD_ID_SVAMMDSP:
1180 case EPOD_ID_SIAMMDSP:
1181 case EPOD_ID_ESRAM12:
1182 case EPOD_ID_ESRAM34:
1183 ram_retention = true;
1187 /* check argument */
1188 BUG_ON(epod_state > EPOD_STATE_ON);
1189 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1192 mutex_lock(&mb2_transfer.lock);
1194 /* wait for mailbox */
1195 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1198 /* fill in mailbox */
1199 for (i = 0; i < NUM_EPOD_ID; i++)
1200 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1201 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1203 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1205 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1208 * The current firmware version does not handle errors correctly,
1209 * and we cannot recover if there is an error.
1210 * This is expected to change when the firmware is updated.
1212 if (!wait_for_completion_timeout(&mb2_transfer.work,
1213 msecs_to_jiffies(20000))) {
1214 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1217 goto unlock_and_return;
1220 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1224 mutex_unlock(&mb2_transfer.lock);
1229 * prcmu_configure_auto_pm - Configure autonomous power management.
1230 * @sleep: Configuration for ApSleep.
1231 * @idle: Configuration for ApIdle.
1233 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1234 struct prcmu_auto_pm_config *idle)
1238 unsigned long flags;
1240 BUG_ON((sleep == NULL) || (idle == NULL));
1242 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1243 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1244 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1245 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1246 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1247 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1249 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1250 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1251 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1252 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1253 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1254 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1256 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1259 * The autonomous power management configuration is done through
1260 * fields in mailbox 2, but these fields are only used as shared
1261 * variables - i.e. there is no need to send a message.
1263 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1264 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1266 mb2_transfer.auto_pm_enabled =
1267 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1268 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1269 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1270 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1272 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1274 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1276 bool prcmu_is_auto_pm_enabled(void)
1278 return mb2_transfer.auto_pm_enabled;
1281 static int request_sysclk(bool enable)
1284 unsigned long flags;
1288 mutex_lock(&mb3_transfer.sysclk_lock);
1290 spin_lock_irqsave(&mb3_transfer.lock, flags);
1292 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1295 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1297 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1298 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1300 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1303 * The firmware only sends an ACK if we want to enable the
1304 * SysClk, and it succeeds.
1306 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1307 msecs_to_jiffies(20000))) {
1308 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1313 mutex_unlock(&mb3_transfer.sysclk_lock);
1318 static int request_timclk(bool enable)
1323 * On the U8420_CLKSEL firmware, the ULP (Ultra Low Power)
1324 * PLL is disabled so we cannot use doze mode, this will
1325 * stop the clock on this firmware.
1327 if (prcmu_is_ulppll_disabled())
1330 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1333 val |= PRCM_TCR_STOP_TIMERS |
1334 PRCM_TCR_DOZE_MODE |
1335 PRCM_TCR_TENSEL_MASK;
1337 writel(val, PRCM_TCR);
1342 static int request_clock(u8 clock, bool enable)
1345 unsigned long flags;
1347 spin_lock_irqsave(&clk_mgt_lock, flags);
1349 /* Grab the HW semaphore. */
1350 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1353 val = readl(prcmu_base + clk_mgt[clock].offset);
1355 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1357 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1358 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1360 writel(val, prcmu_base + clk_mgt[clock].offset);
1362 /* Release the HW semaphore. */
1363 writel(0, PRCM_SEM);
1365 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1370 static int request_sga_clock(u8 clock, bool enable)
1376 val = readl(PRCM_CGATING_BYPASS);
1377 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1380 ret = request_clock(clock, enable);
1382 if (!ret && !enable) {
1383 val = readl(PRCM_CGATING_BYPASS);
1384 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1390 static inline bool plldsi_locked(void)
1392 return (readl(PRCM_PLLDSI_LOCKP) &
1393 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1394 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1395 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1396 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1399 static int request_plldsi(bool enable)
1404 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1405 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1406 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1408 val = readl(PRCM_PLLDSI_ENABLE);
1410 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1412 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1413 writel(val, PRCM_PLLDSI_ENABLE);
1417 bool locked = plldsi_locked();
1419 for (i = 10; !locked && (i > 0); --i) {
1421 locked = plldsi_locked();
1424 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1425 PRCM_APE_RESETN_SET);
1427 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1428 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1429 PRCM_MMIP_LS_CLAMP_SET);
1430 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1431 writel(val, PRCM_PLLDSI_ENABLE);
1435 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1440 static int request_dsiclk(u8 n, bool enable)
1444 val = readl(PRCM_DSI_PLLOUT_SEL);
1445 val &= ~dsiclk[n].divsel_mask;
1446 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1447 dsiclk[n].divsel_shift);
1448 writel(val, PRCM_DSI_PLLOUT_SEL);
1452 static int request_dsiescclk(u8 n, bool enable)
1456 val = readl(PRCM_DSITVCLK_DIV);
1457 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1458 writel(val, PRCM_DSITVCLK_DIV);
1463 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1464 * @clock: The clock for which the request is made.
1465 * @enable: Whether the clock should be enabled (true) or disabled (false).
1467 * This function should only be used by the clock implementation.
1468 * Do not use it from any other place!
1470 int db8500_prcmu_request_clock(u8 clock, bool enable)
1472 if (clock == PRCMU_SGACLK)
1473 return request_sga_clock(clock, enable);
1474 else if (clock < PRCMU_NUM_REG_CLOCKS)
1475 return request_clock(clock, enable);
1476 else if (clock == PRCMU_TIMCLK)
1477 return request_timclk(enable);
1478 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1479 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1480 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1481 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1482 else if (clock == PRCMU_PLLDSI)
1483 return request_plldsi(enable);
1484 else if (clock == PRCMU_SYSCLK)
1485 return request_sysclk(enable);
1486 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1487 return request_pll(clock, enable);
1492 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1503 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1505 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1509 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1513 if (val & PRCM_PLL_FREQ_SELDIV2)
1516 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1517 (val & PRCM_PLL_FREQ_DIV2EN) &&
1518 ((reg == PRCM_PLLSOC0_FREQ) ||
1519 (reg == PRCM_PLLARM_FREQ) ||
1520 (reg == PRCM_PLLDDR_FREQ))))
1523 (void)do_div(rate, div);
1525 return (unsigned long)rate;
1528 #define ROOT_CLOCK_RATE 38400000
1530 static unsigned long clock_rate(u8 clock)
1534 unsigned long rate = ROOT_CLOCK_RATE;
1536 val = readl(prcmu_base + clk_mgt[clock].offset);
1538 if (val & PRCM_CLK_MGT_CLK38) {
1539 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1544 val |= clk_mgt[clock].pllsw;
1545 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1547 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1548 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1549 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1550 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1551 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1552 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1556 if ((clock == PRCMU_SGACLK) &&
1557 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1558 u64 r = (rate * 10);
1560 (void)do_div(r, 25);
1561 return (unsigned long)r;
1563 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1570 static unsigned long armss_rate(void)
1575 r = readl(PRCM_ARM_CHGCLKREQ);
1577 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1578 /* External ARMCLKFIX clock */
1580 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1582 /* Check PRCM_ARM_CHGCLKREQ divider */
1583 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1586 /* Check PRCM_ARMCLKFIX_MGT divider */
1587 r = readl(PRCM_ARMCLKFIX_MGT);
1588 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1591 } else {/* ARM PLL */
1592 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1598 static unsigned long dsiclk_rate(u8 n)
1603 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1604 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1606 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1607 divsel = dsiclk[n].divsel;
1609 dsiclk[n].divsel = divsel;
1612 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1615 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1618 case PRCM_DSI_PLLOUT_SEL_PHI:
1619 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1626 static unsigned long dsiescclk_rate(u8 n)
1630 div = readl(PRCM_DSITVCLK_DIV);
1631 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1632 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1635 unsigned long prcmu_clock_rate(u8 clock)
1637 if (clock < PRCMU_NUM_REG_CLOCKS)
1638 return clock_rate(clock);
1639 else if (clock == PRCMU_TIMCLK)
1640 return prcmu_is_ulppll_disabled() ?
1641 32768 : ROOT_CLOCK_RATE / 16;
1642 else if (clock == PRCMU_SYSCLK)
1643 return ROOT_CLOCK_RATE;
1644 else if (clock == PRCMU_PLLSOC0)
1645 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1646 else if (clock == PRCMU_PLLSOC1)
1647 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1648 else if (clock == PRCMU_ARMSS)
1649 return armss_rate();
1650 else if (clock == PRCMU_PLLDDR)
1651 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1652 else if (clock == PRCMU_PLLDSI)
1653 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1655 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1656 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1657 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1658 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1663 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1665 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1666 return ROOT_CLOCK_RATE;
1667 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1668 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1669 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1670 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1671 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1672 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1673 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1678 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1682 div = (src_rate / rate);
1685 if (rate < (src_rate / div))
1690 static long round_clock_rate(u8 clock, unsigned long rate)
1694 unsigned long src_rate;
1697 val = readl(prcmu_base + clk_mgt[clock].offset);
1698 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1699 clk_mgt[clock].branch);
1700 div = clock_divider(src_rate, rate);
1701 if (val & PRCM_CLK_MGT_CLK38) {
1702 if (clk_mgt[clock].clk38div) {
1708 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1709 u64 r = (src_rate * 10);
1711 (void)do_div(r, 25);
1713 return (unsigned long)r;
1715 rounded_rate = (src_rate / min(div, (u32)31));
1717 return rounded_rate;
1720 static const unsigned long db8500_armss_freqs[] = {
1727 /* The DB8520 has slightly higher ARMSS max frequency */
1728 static const unsigned long db8520_armss_freqs[] = {
1737 static long round_armss_rate(unsigned long rate)
1739 unsigned long freq = 0;
1740 const unsigned long *freqs;
1744 if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1745 freqs = db8520_armss_freqs;
1746 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1748 freqs = db8500_armss_freqs;
1749 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1752 /* Find the corresponding arm opp from the cpufreq table. */
1753 for (i = 0; i < nfreqs; i++) {
1759 /* Return the last valid value, even if a match was not found. */
1763 #define MIN_PLL_VCO_RATE 600000000ULL
1764 #define MAX_PLL_VCO_RATE 1680640000ULL
1766 static long round_plldsi_rate(unsigned long rate)
1768 long rounded_rate = 0;
1769 unsigned long src_rate;
1773 src_rate = clock_rate(PRCMU_HDMICLK);
1776 for (r = 7; (rem > 0) && (r > 0); r--) {
1780 (void)do_div(d, src_rate);
1786 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1787 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1791 if (rounded_rate == 0)
1792 rounded_rate = (long)d;
1795 if ((rate - d) < rem) {
1797 rounded_rate = (long)d;
1800 return rounded_rate;
1803 static long round_dsiclk_rate(unsigned long rate)
1806 unsigned long src_rate;
1809 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1811 div = clock_divider(src_rate, rate);
1812 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1814 return rounded_rate;
1817 static long round_dsiescclk_rate(unsigned long rate)
1820 unsigned long src_rate;
1823 src_rate = clock_rate(PRCMU_TVCLK);
1824 div = clock_divider(src_rate, rate);
1825 rounded_rate = (src_rate / min(div, (u32)255));
1827 return rounded_rate;
1830 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1832 if (clock < PRCMU_NUM_REG_CLOCKS)
1833 return round_clock_rate(clock, rate);
1834 else if (clock == PRCMU_ARMSS)
1835 return round_armss_rate(rate);
1836 else if (clock == PRCMU_PLLDSI)
1837 return round_plldsi_rate(rate);
1838 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1839 return round_dsiclk_rate(rate);
1840 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1841 return round_dsiescclk_rate(rate);
1843 return (long)prcmu_clock_rate(clock);
1846 static void set_clock_rate(u8 clock, unsigned long rate)
1850 unsigned long src_rate;
1851 unsigned long flags;
1853 spin_lock_irqsave(&clk_mgt_lock, flags);
1855 /* Grab the HW semaphore. */
1856 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1859 val = readl(prcmu_base + clk_mgt[clock].offset);
1860 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1861 clk_mgt[clock].branch);
1862 div = clock_divider(src_rate, rate);
1863 if (val & PRCM_CLK_MGT_CLK38) {
1864 if (clk_mgt[clock].clk38div) {
1866 val |= PRCM_CLK_MGT_CLK38DIV;
1868 val &= ~PRCM_CLK_MGT_CLK38DIV;
1870 } else if (clock == PRCMU_SGACLK) {
1871 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1872 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1874 u64 r = (src_rate * 10);
1876 (void)do_div(r, 25);
1878 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1882 val |= min(div, (u32)31);
1884 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1885 val |= min(div, (u32)31);
1887 writel(val, prcmu_base + clk_mgt[clock].offset);
1889 /* Release the HW semaphore. */
1890 writel(0, PRCM_SEM);
1892 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1895 static int set_armss_rate(unsigned long rate)
1898 u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
1899 const unsigned long *freqs;
1903 if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1904 freqs = db8520_armss_freqs;
1905 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1907 freqs = db8500_armss_freqs;
1908 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1911 /* Find the corresponding arm opp from the cpufreq table. */
1912 for (i = 0; i < nfreqs; i++) {
1921 /* Set the new arm opp. */
1922 pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
1923 return db8500_prcmu_set_arm_opp(opps[i]);
1926 static int set_plldsi_rate(unsigned long rate)
1928 unsigned long src_rate;
1933 src_rate = clock_rate(PRCMU_HDMICLK);
1936 for (r = 7; (rem > 0) && (r > 0); r--) {
1941 (void)do_div(d, src_rate);
1946 hwrate = (d * src_rate);
1947 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1948 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1950 (void)do_div(hwrate, r);
1951 if (rate < hwrate) {
1953 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1954 (r << PRCM_PLL_FREQ_R_SHIFT));
1957 if ((rate - hwrate) < rem) {
1958 rem = (rate - hwrate);
1959 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1960 (r << PRCM_PLL_FREQ_R_SHIFT));
1966 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1967 writel(pll_freq, PRCM_PLLDSI_FREQ);
1972 static void set_dsiclk_rate(u8 n, unsigned long rate)
1977 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1978 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1980 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1981 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1982 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1984 val = readl(PRCM_DSI_PLLOUT_SEL);
1985 val &= ~dsiclk[n].divsel_mask;
1986 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1987 writel(val, PRCM_DSI_PLLOUT_SEL);
1990 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1995 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1996 val = readl(PRCM_DSITVCLK_DIV);
1997 val &= ~dsiescclk[n].div_mask;
1998 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1999 writel(val, PRCM_DSITVCLK_DIV);
2002 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
2004 if (clock < PRCMU_NUM_REG_CLOCKS)
2005 set_clock_rate(clock, rate);
2006 else if (clock == PRCMU_ARMSS)
2007 return set_armss_rate(rate);
2008 else if (clock == PRCMU_PLLDSI)
2009 return set_plldsi_rate(rate);
2010 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
2011 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
2012 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
2013 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
2017 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
2019 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2020 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2023 mutex_lock(&mb4_transfer.lock);
2025 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2028 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2029 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2030 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2031 writeb(DDR_PWR_STATE_ON,
2032 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2033 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2035 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2036 wait_for_completion(&mb4_transfer.work);
2038 mutex_unlock(&mb4_transfer.lock);
2043 int db8500_prcmu_config_hotdog(u8 threshold)
2045 mutex_lock(&mb4_transfer.lock);
2047 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2050 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2051 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2053 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2054 wait_for_completion(&mb4_transfer.work);
2056 mutex_unlock(&mb4_transfer.lock);
2061 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2063 mutex_lock(&mb4_transfer.lock);
2065 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2068 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2069 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2070 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2071 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2072 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2074 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2075 wait_for_completion(&mb4_transfer.work);
2077 mutex_unlock(&mb4_transfer.lock);
2081 EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
2083 static int config_hot_period(u16 val)
2085 mutex_lock(&mb4_transfer.lock);
2087 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2090 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2091 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2093 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2094 wait_for_completion(&mb4_transfer.work);
2096 mutex_unlock(&mb4_transfer.lock);
2101 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2103 if (cycles32k == 0xFFFF)
2106 return config_hot_period(cycles32k);
2108 EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
2110 int db8500_prcmu_stop_temp_sense(void)
2112 return config_hot_period(0xFFFF);
2114 EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
2116 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2119 mutex_lock(&mb4_transfer.lock);
2121 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2124 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2125 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2126 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2127 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2129 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2131 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2132 wait_for_completion(&mb4_transfer.work);
2134 mutex_unlock(&mb4_transfer.lock);
2140 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2142 BUG_ON(num == 0 || num > 0xf);
2143 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2144 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2145 A9WDOG_AUTO_OFF_DIS);
2147 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2149 int db8500_prcmu_enable_a9wdog(u8 id)
2151 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2153 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2155 int db8500_prcmu_disable_a9wdog(u8 id)
2157 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2159 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2161 int db8500_prcmu_kick_a9wdog(u8 id)
2163 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2165 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2168 * timeout is 28 bit, in ms.
2170 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2172 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2173 (id & A9WDOG_ID_MASK) |
2175 * Put the lowest 28 bits of timeout at
2176 * offset 4. Four first bits are used for id.
2178 (u8)((timeout << 4) & 0xf0),
2179 (u8)((timeout >> 4) & 0xff),
2180 (u8)((timeout >> 12) & 0xff),
2181 (u8)((timeout >> 20) & 0xff));
2183 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2186 * prcmu_abb_read() - Read register value(s) from the ABB.
2187 * @slave: The I2C slave address.
2188 * @reg: The (start) register address.
2189 * @value: The read out value(s).
2190 * @size: The number of registers to read.
2192 * Reads register value(s) from the ABB.
2193 * @size has to be 1 for the current firmware version.
2195 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2202 mutex_lock(&mb5_transfer.lock);
2204 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2207 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2208 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2209 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2210 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2211 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2213 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2215 if (!wait_for_completion_timeout(&mb5_transfer.work,
2216 msecs_to_jiffies(20000))) {
2217 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2221 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2225 *value = mb5_transfer.ack.value;
2227 mutex_unlock(&mb5_transfer.lock);
2233 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2234 * @slave: The I2C slave address.
2235 * @reg: The (start) register address.
2236 * @value: The value(s) to write.
2237 * @mask: The mask(s) to use.
2238 * @size: The number of registers to write.
2240 * Writes masked register value(s) to the ABB.
2241 * For each @value, only the bits set to 1 in the corresponding @mask
2242 * will be written. The other bits are not changed.
2243 * @size has to be 1 for the current firmware version.
2245 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2252 mutex_lock(&mb5_transfer.lock);
2254 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2257 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2258 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2259 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2260 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2261 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2263 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2265 if (!wait_for_completion_timeout(&mb5_transfer.work,
2266 msecs_to_jiffies(20000))) {
2267 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2271 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2274 mutex_unlock(&mb5_transfer.lock);
2280 * prcmu_abb_write() - Write register value(s) to the ABB.
2281 * @slave: The I2C slave address.
2282 * @reg: The (start) register address.
2283 * @value: The value(s) to write.
2284 * @size: The number of registers to write.
2286 * Writes register value(s) to the ABB.
2287 * @size has to be 1 for the current firmware version.
2289 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2293 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2297 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2299 int prcmu_ac_wake_req(void)
2304 mutex_lock(&mb0_transfer.ac_wake_lock);
2306 val = readl(PRCM_HOSTACCESS_REQ);
2307 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2308 goto unlock_and_return;
2310 atomic_set(&ac_wake_req_state, 1);
2313 * Force Modem Wake-up before hostaccess_req ping-pong.
2314 * It prevents Modem to enter in Sleep while acking the hostaccess
2315 * request. The 31us delay has been calculated by HWI.
2317 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2318 writel(val, PRCM_HOSTACCESS_REQ);
2322 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2323 writel(val, PRCM_HOSTACCESS_REQ);
2325 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2326 msecs_to_jiffies(5000))) {
2327 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2333 mutex_unlock(&mb0_transfer.ac_wake_lock);
2338 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2340 void prcmu_ac_sleep_req(void)
2344 mutex_lock(&mb0_transfer.ac_wake_lock);
2346 val = readl(PRCM_HOSTACCESS_REQ);
2347 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2348 goto unlock_and_return;
2350 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2351 PRCM_HOSTACCESS_REQ);
2353 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2354 msecs_to_jiffies(5000))) {
2355 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2359 atomic_set(&ac_wake_req_state, 0);
2362 mutex_unlock(&mb0_transfer.ac_wake_lock);
2365 bool db8500_prcmu_is_ac_wake_requested(void)
2367 return (atomic_read(&ac_wake_req_state) != 0);
2371 * db8500_prcmu_system_reset - System reset
2373 * Saves the reset reason code and then sets the APE_SOFTRST register which
2374 * fires interrupt to fw
2376 void db8500_prcmu_system_reset(u16 reset_code)
2378 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2379 writel(1, PRCM_APE_SOFTRST);
2383 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2385 * Retrieves the reset reason code stored by prcmu_system_reset() before
2388 u16 db8500_prcmu_get_reset_code(void)
2390 return readw(tcdm_base + PRCM_SW_RST_REASON);
2394 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2396 void db8500_prcmu_modem_reset(void)
2398 mutex_lock(&mb1_transfer.lock);
2400 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2403 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2404 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2405 wait_for_completion(&mb1_transfer.work);
2408 * No need to check return from PRCMU as modem should go in reset state
2409 * This state is already managed by upper layer
2412 mutex_unlock(&mb1_transfer.lock);
2415 static void ack_dbb_wakeup(void)
2417 unsigned long flags;
2419 spin_lock_irqsave(&mb0_transfer.lock, flags);
2421 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2424 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2425 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2427 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2430 static inline void print_unknown_header_warning(u8 n, u8 header)
2432 pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
2436 static bool read_mailbox_0(void)
2443 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2445 case MB0H_WAKEUP_EXE:
2446 case MB0H_WAKEUP_SLEEP:
2447 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2448 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2450 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2452 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2453 complete(&mb0_transfer.ac_wake_work);
2454 if (ev & WAKEUP_BIT_SYSCLK_OK)
2455 complete(&mb3_transfer.sysclk_work);
2457 ev &= mb0_transfer.req.dbb_irqs;
2459 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2460 if (ev & prcmu_irq_bit[n])
2461 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2466 print_unknown_header_warning(0, header);
2470 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2474 static bool read_mailbox_1(void)
2476 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2477 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2478 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2479 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2480 PRCM_ACK_MB1_CURRENT_APE_OPP);
2481 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2482 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2483 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2484 complete(&mb1_transfer.work);
2488 static bool read_mailbox_2(void)
2490 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2491 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2492 complete(&mb2_transfer.work);
2496 static bool read_mailbox_3(void)
2498 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2502 static bool read_mailbox_4(void)
2505 bool do_complete = true;
2507 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2512 case MB4H_HOT_PERIOD:
2513 case MB4H_A9WDOG_CONF:
2514 case MB4H_A9WDOG_EN:
2515 case MB4H_A9WDOG_DIS:
2516 case MB4H_A9WDOG_LOAD:
2517 case MB4H_A9WDOG_KICK:
2520 print_unknown_header_warning(4, header);
2521 do_complete = false;
2525 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2528 complete(&mb4_transfer.work);
2533 static bool read_mailbox_5(void)
2535 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2536 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2537 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2538 complete(&mb5_transfer.work);
2542 static bool read_mailbox_6(void)
2544 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2548 static bool read_mailbox_7(void)
2550 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2554 static bool (* const read_mailbox[NUM_MB])(void) = {
2565 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2571 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2572 if (unlikely(!bits))
2576 for (n = 0; bits; n++) {
2577 if (bits & MBOX_BIT(n)) {
2578 bits -= MBOX_BIT(n);
2579 if (read_mailbox[n]())
2580 r = IRQ_WAKE_THREAD;
2586 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2592 static void prcmu_mask_work(struct work_struct *work)
2594 unsigned long flags;
2596 spin_lock_irqsave(&mb0_transfer.lock, flags);
2600 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2603 static void prcmu_irq_mask(struct irq_data *d)
2605 unsigned long flags;
2607 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2609 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2611 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2613 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2614 schedule_work(&mb0_transfer.mask_work);
2617 static void prcmu_irq_unmask(struct irq_data *d)
2619 unsigned long flags;
2621 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2623 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2625 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2627 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2628 schedule_work(&mb0_transfer.mask_work);
2631 static void noop(struct irq_data *d)
2635 static struct irq_chip prcmu_irq_chip = {
2637 .irq_disable = prcmu_irq_mask,
2639 .irq_mask = prcmu_irq_mask,
2640 .irq_unmask = prcmu_irq_unmask,
2643 static char *fw_project_name(u32 project)
2646 case PRCMU_FW_PROJECT_U8500:
2648 case PRCMU_FW_PROJECT_U8400:
2650 case PRCMU_FW_PROJECT_U9500:
2652 case PRCMU_FW_PROJECT_U8500_MBB:
2654 case PRCMU_FW_PROJECT_U8500_C1:
2656 case PRCMU_FW_PROJECT_U8500_C2:
2658 case PRCMU_FW_PROJECT_U8500_C3:
2660 case PRCMU_FW_PROJECT_U8500_C4:
2662 case PRCMU_FW_PROJECT_U9500_MBL:
2664 case PRCMU_FW_PROJECT_U8500_MBL:
2666 case PRCMU_FW_PROJECT_U8500_MBL2:
2667 return "U8500 MBL2";
2668 case PRCMU_FW_PROJECT_U8520:
2670 case PRCMU_FW_PROJECT_U8420:
2672 case PRCMU_FW_PROJECT_U8420_SYSCLK:
2673 return "U8420-sysclk";
2674 case PRCMU_FW_PROJECT_U9540:
2676 case PRCMU_FW_PROJECT_A9420:
2678 case PRCMU_FW_PROJECT_L8540:
2680 case PRCMU_FW_PROJECT_L8580:
2687 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2688 irq_hw_number_t hwirq)
2690 irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2696 static const struct irq_domain_ops db8500_irq_ops = {
2697 .map = db8500_irq_map,
2698 .xlate = irq_domain_xlate_twocell,
2701 static int db8500_irq_init(struct device_node *np)
2705 db8500_irq_domain = irq_domain_add_simple(
2706 np, NUM_PRCMU_WAKEUPS, 0,
2707 &db8500_irq_ops, NULL);
2709 if (!db8500_irq_domain) {
2710 pr_err("Failed to create irqdomain\n");
2714 /* All wakeups will be used, so create mappings for all */
2715 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2716 irq_create_mapping(db8500_irq_domain, i);
2721 static void dbx500_fw_version_init(struct device_node *np)
2723 void __iomem *tcpm_base;
2726 tcpm_base = of_iomap(np, 1);
2728 pr_err("no prcmu tcpm mem region provided\n");
2732 version = readl(tcpm_base + DB8500_PRCMU_FW_VERSION_OFFSET);
2733 fw_info.version.project = (version & 0xFF);
2734 fw_info.version.api_version = (version >> 8) & 0xFF;
2735 fw_info.version.func_version = (version >> 16) & 0xFF;
2736 fw_info.version.errata = (version >> 24) & 0xFF;
2737 strncpy(fw_info.version.project_name,
2738 fw_project_name(fw_info.version.project),
2739 PRCMU_FW_PROJECT_NAME_LEN);
2740 fw_info.valid = true;
2741 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2742 fw_info.version.project_name,
2743 fw_info.version.project,
2744 fw_info.version.api_version,
2745 fw_info.version.func_version,
2746 fw_info.version.errata);
2750 void __init db8500_prcmu_early_init(void)
2753 * This is a temporary remap to bring up the clocks. It is
2754 * subsequently replaces with a real remap. After the merge of
2755 * the mailbox subsystem all of this early code goes away, and the
2756 * clock driver can probe independently. An early initcall will
2757 * still be needed, but it can be diverted into drivers/clk/ux500.
2759 struct device_node *np;
2761 np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
2762 prcmu_base = of_iomap(np, 0);
2765 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2768 dbx500_fw_version_init(np);
2771 spin_lock_init(&mb0_transfer.lock);
2772 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2773 mutex_init(&mb0_transfer.ac_wake_lock);
2774 init_completion(&mb0_transfer.ac_wake_work);
2775 mutex_init(&mb1_transfer.lock);
2776 init_completion(&mb1_transfer.work);
2777 mb1_transfer.ape_opp = APE_NO_CHANGE;
2778 mutex_init(&mb2_transfer.lock);
2779 init_completion(&mb2_transfer.work);
2780 spin_lock_init(&mb2_transfer.auto_pm_lock);
2781 spin_lock_init(&mb3_transfer.lock);
2782 mutex_init(&mb3_transfer.sysclk_lock);
2783 init_completion(&mb3_transfer.sysclk_work);
2784 mutex_init(&mb4_transfer.lock);
2785 init_completion(&mb4_transfer.work);
2786 mutex_init(&mb5_transfer.lock);
2787 init_completion(&mb5_transfer.work);
2789 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2792 static void init_prcm_registers(void)
2796 val = readl(PRCM_A9PL_FORCE_CLKEN);
2797 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2798 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2799 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2803 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2805 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2806 REGULATOR_SUPPLY("v-ape", NULL),
2807 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2808 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2809 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2810 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2811 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2812 /* "v-mmc" changed to "vcore" in the mainline kernel */
2813 REGULATOR_SUPPLY("vcore", "sdi0"),
2814 REGULATOR_SUPPLY("vcore", "sdi1"),
2815 REGULATOR_SUPPLY("vcore", "sdi2"),
2816 REGULATOR_SUPPLY("vcore", "sdi3"),
2817 REGULATOR_SUPPLY("vcore", "sdi4"),
2818 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2819 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2820 /* "v-uart" changed to "vcore" in the mainline kernel */
2821 REGULATOR_SUPPLY("vcore", "uart0"),
2822 REGULATOR_SUPPLY("vcore", "uart1"),
2823 REGULATOR_SUPPLY("vcore", "uart2"),
2824 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2825 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2826 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2829 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2830 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2831 /* AV8100 regulator */
2832 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2835 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2836 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2837 REGULATOR_SUPPLY("vsupply", "mcde"),
2840 /* SVA MMDSP regulator switch */
2841 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2842 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2845 /* SVA pipe regulator switch */
2846 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2847 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2850 /* SIA MMDSP regulator switch */
2851 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2852 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2855 /* SIA pipe regulator switch */
2856 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2857 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2860 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2861 REGULATOR_SUPPLY("v-mali", NULL),
2864 /* ESRAM1 and 2 regulator switch */
2865 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2866 REGULATOR_SUPPLY("esram12", "cm_control"),
2869 /* ESRAM3 and 4 regulator switch */
2870 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2871 REGULATOR_SUPPLY("v-esram34", "mcde"),
2872 REGULATOR_SUPPLY("esram34", "cm_control"),
2873 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2876 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2877 [DB8500_REGULATOR_VAPE] = {
2879 .name = "db8500-vape",
2880 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2883 .consumer_supplies = db8500_vape_consumers,
2884 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2886 [DB8500_REGULATOR_VARM] = {
2888 .name = "db8500-varm",
2889 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2892 [DB8500_REGULATOR_VMODEM] = {
2894 .name = "db8500-vmodem",
2895 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2898 [DB8500_REGULATOR_VPLL] = {
2900 .name = "db8500-vpll",
2901 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2904 [DB8500_REGULATOR_VSMPS1] = {
2906 .name = "db8500-vsmps1",
2907 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2910 [DB8500_REGULATOR_VSMPS2] = {
2912 .name = "db8500-vsmps2",
2913 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2915 .consumer_supplies = db8500_vsmps2_consumers,
2916 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2918 [DB8500_REGULATOR_VSMPS3] = {
2920 .name = "db8500-vsmps3",
2921 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2924 [DB8500_REGULATOR_VRF1] = {
2926 .name = "db8500-vrf1",
2927 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2930 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2931 /* dependency to u8500-vape is handled outside regulator framework */
2933 .name = "db8500-sva-mmdsp",
2934 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2936 .consumer_supplies = db8500_svammdsp_consumers,
2937 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2939 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2941 /* "ret" means "retention" */
2942 .name = "db8500-sva-mmdsp-ret",
2943 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2946 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2947 /* dependency to u8500-vape is handled outside regulator framework */
2949 .name = "db8500-sva-pipe",
2950 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2952 .consumer_supplies = db8500_svapipe_consumers,
2953 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2955 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2956 /* dependency to u8500-vape is handled outside regulator framework */
2958 .name = "db8500-sia-mmdsp",
2959 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2961 .consumer_supplies = db8500_siammdsp_consumers,
2962 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2964 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2966 .name = "db8500-sia-mmdsp-ret",
2967 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2970 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2971 /* dependency to u8500-vape is handled outside regulator framework */
2973 .name = "db8500-sia-pipe",
2974 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2976 .consumer_supplies = db8500_siapipe_consumers,
2977 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2979 [DB8500_REGULATOR_SWITCH_SGA] = {
2980 .supply_regulator = "db8500-vape",
2982 .name = "db8500-sga",
2983 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2985 .consumer_supplies = db8500_sga_consumers,
2986 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2989 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2990 .supply_regulator = "db8500-vape",
2992 .name = "db8500-b2r2-mcde",
2993 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2995 .consumer_supplies = db8500_b2r2_mcde_consumers,
2996 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2998 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
3000 * esram12 is set in retention and supplied by Vsafe when Vape is off,
3001 * no need to hold Vape
3004 .name = "db8500-esram12",
3005 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3007 .consumer_supplies = db8500_esram12_consumers,
3008 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
3010 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
3012 .name = "db8500-esram12-ret",
3013 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3016 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
3018 * esram34 is set in retention and supplied by Vsafe when Vape is off,
3019 * no need to hold Vape
3022 .name = "db8500-esram34",
3023 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3025 .consumer_supplies = db8500_esram34_consumers,
3026 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3028 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3030 .name = "db8500-esram34-ret",
3031 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3036 static struct ux500_wdt_data db8500_wdt_pdata = {
3037 .timeout = 600, /* 10 minutes */
3038 .has_28_bits_resolution = true,
3041 static const struct mfd_cell common_prcmu_devs[] = {
3043 .name = "ux500_wdt",
3044 .platform_data = &db8500_wdt_pdata,
3045 .pdata_size = sizeof(db8500_wdt_pdata),
3050 static const struct mfd_cell db8500_prcmu_devs[] = {
3051 OF_MFD_CELL("db8500-prcmu-regulators", NULL,
3052 &db8500_regulators, sizeof(db8500_regulators), 0,
3053 "stericsson,db8500-prcmu-regulator"),
3054 OF_MFD_CELL("cpuidle-dbx500",
3055 NULL, NULL, 0, 0, "stericsson,cpuidle-dbx500"),
3056 OF_MFD_CELL("db8500-thermal",
3057 NULL, NULL, 0, 0, "stericsson,db8500-thermal"),
3060 static int db8500_prcmu_register_ab8500(struct device *parent)
3062 struct device_node *np;
3063 struct resource ab8500_resource;
3064 const struct mfd_cell ab8500_cell = {
3065 .name = "ab8500-core",
3066 .of_compatible = "stericsson,ab8500",
3067 .id = AB8500_VERSION_AB8500,
3068 .resources = &ab8500_resource,
3072 if (!parent->of_node)
3075 /* Look up the device node, sneak the IRQ out of it */
3076 for_each_child_of_node(parent->of_node, np) {
3077 if (of_device_is_compatible(np, ab8500_cell.of_compatible))
3081 dev_info(parent, "could not find AB8500 node in the device tree\n");
3084 of_irq_to_resource_table(np, &ab8500_resource, 1);
3086 return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3090 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3093 static int db8500_prcmu_probe(struct platform_device *pdev)
3095 struct device_node *np = pdev->dev.of_node;
3096 int irq = 0, err = 0;
3097 struct resource *res;
3099 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3101 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3104 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3107 "failed to ioremap prcmu register memory\n");
3110 init_prcm_registers();
3111 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3113 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3116 tcdm_base = devm_ioremap(&pdev->dev, res->start,
3117 resource_size(res));
3120 "failed to ioremap prcmu-tcdm register memory\n");
3124 /* Clean up the mailbox interrupts after pre-kernel code. */
3125 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3127 irq = platform_get_irq(pdev, 0);
3131 err = request_threaded_irq(irq, prcmu_irq_handler,
3132 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3134 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3138 db8500_irq_init(np);
3140 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3142 err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3143 ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3145 pr_err("prcmu: Failed to add subdevices\n");
3149 /* TODO: Remove restriction when clk definitions are available. */
3150 if (!of_machine_is_compatible("st-ericsson,u8540")) {
3151 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3152 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3155 mfd_remove_devices(&pdev->dev);
3156 pr_err("prcmu: Failed to add subdevices\n");
3161 err = db8500_prcmu_register_ab8500(&pdev->dev);
3163 mfd_remove_devices(&pdev->dev);
3164 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3168 pr_info("DB8500 PRCMU initialized\n");
3171 static const struct of_device_id db8500_prcmu_match[] = {
3172 { .compatible = "stericsson,db8500-prcmu"},
3176 static struct platform_driver db8500_prcmu_driver = {
3178 .name = "db8500-prcmu",
3179 .of_match_table = db8500_prcmu_match,
3181 .probe = db8500_prcmu_probe,
3184 static int __init db8500_prcmu_init(void)
3186 return platform_driver_register(&db8500_prcmu_driver);
3188 core_initcall(db8500_prcmu_init);