drivers/mfd/intel_soc_pmic_bxtwc.c

   1 /*
   2  * MFD core driver for Intel Broxton Whiskey Cove PMIC
   3  *
   4  * Copyright (C) 2015 Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/acpi.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/kernel.h>
  21 #include <linux/mfd/core.h>
  22 #include <linux/mfd/intel_soc_pmic.h>
  23 #include <linux/mfd/intel_soc_pmic_bxtwc.h>
  24 #include <linux/module.h>
  25
  26 #include <asm/intel_pmc_ipc.h>
  27
  28 /* PMIC device registers */
  29 #define REG_ADDR_MASK           0xFF00
  30 #define REG_ADDR_SHIFT          8
  31 #define REG_OFFSET_MASK         0xFF
  32
  33 /* Interrupt Status Registers */
  34 #define BXTWC_IRQLVL1           0x4E02
  35
  36 #define BXTWC_PWRBTNIRQ         0x4E03
  37 #define BXTWC_THRM0IRQ          0x4E04
  38 #define BXTWC_THRM1IRQ          0x4E05
  39 #define BXTWC_THRM2IRQ          0x4E06
  40 #define BXTWC_BCUIRQ            0x4E07
  41 #define BXTWC_ADCIRQ            0x4E08
  42 #define BXTWC_CHGR0IRQ          0x4E09
  43 #define BXTWC_CHGR1IRQ          0x4E0A
  44 #define BXTWC_GPIOIRQ0          0x4E0B
  45 #define BXTWC_GPIOIRQ1          0x4E0C
  46 #define BXTWC_CRITIRQ           0x4E0D
  47 #define BXTWC_TMUIRQ            0x4FB6
  48
  49 /* Interrupt MASK Registers */
  50 #define BXTWC_MIRQLVL1          0x4E0E
  51 #define BXTWC_MIRQLVL1_MCHGR    BIT(5)
  52
  53 #define BXTWC_MPWRBTNIRQ        0x4E0F
  54 #define BXTWC_MTHRM0IRQ         0x4E12
  55 #define BXTWC_MTHRM1IRQ         0x4E13
  56 #define BXTWC_MTHRM2IRQ         0x4E14
  57 #define BXTWC_MBCUIRQ           0x4E15
  58 #define BXTWC_MADCIRQ           0x4E16
  59 #define BXTWC_MCHGR0IRQ         0x4E17
  60 #define BXTWC_MCHGR1IRQ         0x4E18
  61 #define BXTWC_MGPIO0IRQ         0x4E19
  62 #define BXTWC_MGPIO1IRQ         0x4E1A
  63 #define BXTWC_MCRITIRQ          0x4E1B
  64 #define BXTWC_MTMUIRQ           0x4FB7
  65
  66 /* Whiskey Cove PMIC share same ACPI ID between different platforms */
  67 #define BROXTON_PMIC_WC_HRV     4
  68
  69 enum bxtwc_irqs {
  70         BXTWC_PWRBTN_LVL1_IRQ = 0,
  71         BXTWC_TMU_LVL1_IRQ,
  72         BXTWC_THRM_LVL1_IRQ,
  73         BXTWC_BCU_LVL1_IRQ,
  74         BXTWC_ADC_LVL1_IRQ,
  75         BXTWC_CHGR_LVL1_IRQ,
  76         BXTWC_GPIO_LVL1_IRQ,
  77         BXTWC_CRIT_LVL1_IRQ,
  78 };
  79
  80 enum bxtwc_irqs_pwrbtn {
  81         BXTWC_PWRBTN_IRQ = 0,
  82         BXTWC_UIBTN_IRQ,
  83 };
  84
  85 enum bxtwc_irqs_bcu {
  86         BXTWC_BCU_IRQ = 0,
  87 };
  88
  89 enum bxtwc_irqs_adc {
  90         BXTWC_ADC_IRQ = 0,
  91 };
  92
  93 enum bxtwc_irqs_chgr {
  94         BXTWC_USBC_IRQ = 0,
  95         BXTWC_CHGR0_IRQ,
  96         BXTWC_CHGR1_IRQ,
  97 };
  98
  99 enum bxtwc_irqs_tmu {
 100         BXTWC_TMU_IRQ = 0,
 101 };
 102
 103 enum bxtwc_irqs_crit {
 104         BXTWC_CRIT_IRQ = 0,
 105 };
 106
 107 static const struct regmap_irq bxtwc_regmap_irqs[] = {
 108         REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
 109         REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
 110         REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
 111         REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
 112         REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
 113         REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
 114         REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
 115         REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
 116 };
 117
 118 static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
 119         REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, 0x01),
 120 };
 121
 122 static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
 123         REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
 124 };
 125
 126 static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
 127         REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
 128 };
 129
 130 static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
 131         REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, 0x20),
 132         REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
 133         REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
 134 };
 135
 136 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
 137         REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
 138 };
 139
 140 static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
 141         REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
 142 };
 143
 144 static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 145         .name = "bxtwc_irq_chip",
 146         .status_base = BXTWC_IRQLVL1,
 147         .mask_base = BXTWC_MIRQLVL1,
 148         .irqs = bxtwc_regmap_irqs,
 149         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
 150         .num_regs = 1,
 151 };
 152
 153 static struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {
 154         .name = "bxtwc_irq_chip_pwrbtn",
 155         .status_base = BXTWC_PWRBTNIRQ,
 156         .mask_base = BXTWC_MPWRBTNIRQ,
 157         .irqs = bxtwc_regmap_irqs_pwrbtn,
 158         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),
 159         .num_regs = 1,
 160 };
 161
 162 static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 163         .name = "bxtwc_irq_chip_tmu",
 164         .status_base = BXTWC_TMUIRQ,
 165         .mask_base = BXTWC_MTMUIRQ,
 166         .irqs = bxtwc_regmap_irqs_tmu,
 167         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),
 168         .num_regs = 1,
 169 };
 170
 171 static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
 172         .name = "bxtwc_irq_chip_bcu",
 173         .status_base = BXTWC_BCUIRQ,
 174         .mask_base = BXTWC_MBCUIRQ,
 175         .irqs = bxtwc_regmap_irqs_bcu,
 176         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
 177         .num_regs = 1,
 178 };
 179
 180 static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
 181         .name = "bxtwc_irq_chip_adc",
 182         .status_base = BXTWC_ADCIRQ,
 183         .mask_base = BXTWC_MADCIRQ,
 184         .irqs = bxtwc_regmap_irqs_adc,
 185         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
 186         .num_regs = 1,
 187 };
 188
 189 static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
 190         .name = "bxtwc_irq_chip_chgr",
 191         .status_base = BXTWC_CHGR0IRQ,
 192         .mask_base = BXTWC_MCHGR0IRQ,
 193         .irqs = bxtwc_regmap_irqs_chgr,
 194         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
 195         .num_regs = 2,
 196 };
 197
 198 static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
 199         .name = "bxtwc_irq_chip_crit",
 200         .status_base = BXTWC_CRITIRQ,
 201         .mask_base = BXTWC_MCRITIRQ,
 202         .irqs = bxtwc_regmap_irqs_crit,
 203         .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
 204         .num_regs = 1,
 205 };
 206
 207 static struct resource gpio_resources[] = {
 208         DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
 209 };
 210
 211 static struct resource adc_resources[] = {
 212         DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
 213 };
 214
 215 static struct resource usbc_resources[] = {
 216         DEFINE_RES_IRQ(BXTWC_USBC_IRQ),
 217 };
 218
 219 static struct resource charger_resources[] = {
 220         DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
 221         DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
 222 };
 223
 224 static struct resource thermal_resources[] = {
 225         DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
 226 };
 227
 228 static struct resource bcu_resources[] = {
 229         DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
 230 };
 231
 232 static struct resource tmu_resources[] = {
 233         DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),
 234 };
 235
 236 static struct mfd_cell bxt_wc_dev[] = {
 237         {
 238                 .name = "bxt_wcove_gpadc",
 239                 .num_resources = ARRAY_SIZE(adc_resources),
 240                 .resources = adc_resources,
 241         },
 242         {
 243                 .name = "bxt_wcove_thermal",
 244                 .num_resources = ARRAY_SIZE(thermal_resources),
 245                 .resources = thermal_resources,
 246         },
 247         {
 248                 .name = "bxt_wcove_usbc",
 249                 .num_resources = ARRAY_SIZE(usbc_resources),
 250                 .resources = usbc_resources,
 251         },
 252         {
 253                 .name = "bxt_wcove_ext_charger",
 254                 .num_resources = ARRAY_SIZE(charger_resources),
 255                 .resources = charger_resources,
 256         },
 257         {
 258                 .name = "bxt_wcove_bcu",
 259                 .num_resources = ARRAY_SIZE(bcu_resources),
 260                 .resources = bcu_resources,
 261         },
 262         {
 263                 .name = "bxt_wcove_tmu",
 264                 .num_resources = ARRAY_SIZE(tmu_resources),
 265                 .resources = tmu_resources,
 266         },
 267
 268         {
 269                 .name = "bxt_wcove_gpio",
 270                 .num_resources = ARRAY_SIZE(gpio_resources),
 271                 .resources = gpio_resources,
 272         },
 273         {
 274                 .name = "bxt_wcove_region",
 275         },
 276 };
 277
 278 static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
 279                                     unsigned int *val)
 280 {
 281         int ret;
 282         int i2c_addr;
 283         u8 ipc_in[2];
 284         u8 ipc_out[4];
 285         struct intel_soc_pmic *pmic = context;
 286
 287         if (!pmic)
 288                 return -EINVAL;
 289
 290         if (reg & REG_ADDR_MASK)
 291                 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
 292         else
 293                 i2c_addr = BXTWC_DEVICE1_ADDR;
 294
 295         reg &= REG_OFFSET_MASK;
 296
 297         ipc_in[0] = reg;
 298         ipc_in[1] = i2c_addr;
 299         ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
 300                         PMC_IPC_PMIC_ACCESS_READ,
 301                         ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
 302         if (ret) {
 303                 dev_err(pmic->dev, "Failed to read from PMIC\n");
 304                 return ret;
 305         }
 306         *val = ipc_out[0];
 307
 308         return 0;
 309 }
 310
 311 static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
 312                                        unsigned int val)
 313 {
 314         int ret;
 315         int i2c_addr;
 316         u8 ipc_in[3];
 317         struct intel_soc_pmic *pmic = context;
 318
 319         if (!pmic)
 320                 return -EINVAL;
 321
 322         if (reg & REG_ADDR_MASK)
 323                 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
 324         else
 325                 i2c_addr = BXTWC_DEVICE1_ADDR;
 326
 327         reg &= REG_OFFSET_MASK;
 328
 329         ipc_in[0] = reg;
 330         ipc_in[1] = i2c_addr;
 331         ipc_in[2] = val;
 332         ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
 333                         PMC_IPC_PMIC_ACCESS_WRITE,
 334                         ipc_in, sizeof(ipc_in), NULL, 0);
 335         if (ret) {
 336                 dev_err(pmic->dev, "Failed to write to PMIC\n");
 337                 return ret;
 338         }
 339
 340         return 0;
 341 }
 342
 343 /* sysfs interfaces to r/w PMIC registers, required by initial script */
 344 static unsigned long bxtwc_reg_addr;
 345 static ssize_t bxtwc_reg_show(struct device *dev,
 346                 struct device_attribute *attr, char *buf)
 347 {
 348         return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
 349 }
 350
 351 static ssize_t bxtwc_reg_store(struct device *dev,
 352         struct device_attribute *attr, const char *buf, size_t count)
 353 {
 354         if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
 355                 dev_err(dev, "Invalid register address\n");
 356                 return -EINVAL;
 357         }
 358         return (ssize_t)count;
 359 }
 360
 361 static ssize_t bxtwc_val_show(struct device *dev,
 362                 struct device_attribute *attr, char *buf)
 363 {
 364         int ret;
 365         unsigned int val;
 366         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 367
 368         ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
 369         if (ret < 0) {
 370                 dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
 371                 return -EIO;
 372         }
 373
 374         return sprintf(buf, "0x%02x\n", val);
 375 }
 376
 377 static ssize_t bxtwc_val_store(struct device *dev,
 378         struct device_attribute *attr, const char *buf, size_t count)
 379 {
 380         int ret;
 381         unsigned int val;
 382         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 383
 384         ret = kstrtouint(buf, 0, &val);
 385         if (ret)
 386                 return ret;
 387
 388         ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
 389         if (ret) {
 390                 dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
 391                         val, bxtwc_reg_addr);
 392                 return -EIO;
 393         }
 394         return count;
 395 }
 396
 397 static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
 398 static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store);
 399 static struct attribute *bxtwc_attrs[] = {
 400         &dev_attr_addr.attr,
 401         &dev_attr_val.attr,
 402         NULL
 403 };
 404
 405 static const struct attribute_group bxtwc_group = {
 406         .attrs = bxtwc_attrs,
 407 };
 408
 409 static const struct regmap_config bxtwc_regmap_config = {
 410         .reg_bits = 16,
 411         .val_bits = 8,
 412         .reg_write = regmap_ipc_byte_reg_write,
 413         .reg_read = regmap_ipc_byte_reg_read,
 414 };
 415
 416 static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
 417                                 struct regmap_irq_chip_data *pdata,
 418                                 int pirq, int irq_flags,
 419                                 const struct regmap_irq_chip *chip,
 420                                 struct regmap_irq_chip_data **data)
 421 {
 422         int irq;
 423
 424         irq = regmap_irq_get_virq(pdata, pirq);
 425         if (irq < 0) {
 426                 dev_err(pmic->dev,
 427                         "Failed to get parent vIRQ(%d) for chip %s, ret:%d\n",
 428                         pirq, chip->name, irq);
 429                 return irq;
 430         }
 431
 432         return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
 433                                         0, chip, data);
 434 }
 435
 436 static int bxtwc_probe(struct platform_device *pdev)
 437 {
 438         int ret;
 439         acpi_handle handle;
 440         acpi_status status;
 441         unsigned long long hrv;
 442         struct intel_soc_pmic *pmic;
 443
 444         handle = ACPI_HANDLE(&pdev->dev);
 445         status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
 446         if (ACPI_FAILURE(status)) {
 447                 dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
 448                 return -ENODEV;
 449         }
 450         if (hrv != BROXTON_PMIC_WC_HRV) {
 451                 dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
 452                         hrv);
 453                 return -ENODEV;
 454         }
 455
 456         pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
 457         if (!pmic)
 458                 return -ENOMEM;
 459
 460         ret = platform_get_irq(pdev, 0);
 461         if (ret < 0) {
 462                 dev_err(&pdev->dev, "Invalid IRQ\n");
 463                 return ret;
 464         }
 465         pmic->irq = ret;
 466
 467         dev_set_drvdata(&pdev->dev, pmic);
 468         pmic->dev = &pdev->dev;
 469
 470         pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
 471                                         &bxtwc_regmap_config);
 472         if (IS_ERR(pmic->regmap)) {
 473                 ret = PTR_ERR(pmic->regmap);
 474                 dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
 475                 return ret;
 476         }
 477
 478         ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
 479                                        IRQF_ONESHOT | IRQF_SHARED,
 480                                        0, &bxtwc_regmap_irq_chip,
 481                                        &pmic->irq_chip_data);
 482         if (ret) {
 483                 dev_err(&pdev->dev, "Failed to add IRQ chip\n");
 484                 return ret;
 485         }
 486
 487         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 488                                          BXTWC_PWRBTN_LVL1_IRQ,
 489                                          IRQF_ONESHOT,
 490                                          &bxtwc_regmap_irq_chip_pwrbtn,
 491                                          &pmic->irq_chip_data_pwrbtn);
 492         if (ret) {
 493                 dev_err(&pdev->dev, "Failed to add PWRBTN IRQ chip\n");
 494                 return ret;
 495         }
 496
 497         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 498                                          BXTWC_TMU_LVL1_IRQ,
 499                                          IRQF_ONESHOT,
 500                                          &bxtwc_regmap_irq_chip_tmu,
 501                                          &pmic->irq_chip_data_tmu);
 502         if (ret) {
 503                 dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
 504                 return ret;
 505         }
 506
 507         /* Add chained IRQ handler for BCU IRQs */
 508         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 509                                          BXTWC_BCU_LVL1_IRQ,
 510                                          IRQF_ONESHOT,
 511                                          &bxtwc_regmap_irq_chip_bcu,
 512                                          &pmic->irq_chip_data_bcu);
 513
 514
 515         if (ret) {
 516                 dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
 517                 return ret;
 518         }
 519
 520         /* Add chained IRQ handler for ADC IRQs */
 521         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 522                                          BXTWC_ADC_LVL1_IRQ,
 523                                          IRQF_ONESHOT,
 524                                          &bxtwc_regmap_irq_chip_adc,
 525                                          &pmic->irq_chip_data_adc);
 526
 527
 528         if (ret) {
 529                 dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
 530                 return ret;
 531         }
 532
 533         /* Add chained IRQ handler for CHGR IRQs */
 534         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 535                                          BXTWC_CHGR_LVL1_IRQ,
 536                                          IRQF_ONESHOT,
 537                                          &bxtwc_regmap_irq_chip_chgr,
 538                                          &pmic->irq_chip_data_chgr);
 539
 540
 541         if (ret) {
 542                 dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
 543                 return ret;
 544         }
 545
 546         /* Add chained IRQ handler for CRIT IRQs */
 547         ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
 548                                          BXTWC_CRIT_LVL1_IRQ,
 549                                          IRQF_ONESHOT,
 550                                          &bxtwc_regmap_irq_chip_crit,
 551                                          &pmic->irq_chip_data_crit);
 552
 553
 554         if (ret) {
 555                 dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n");
 556                 return ret;
 557         }
 558
 559         ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
 560                                    ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
 561         if (ret) {
 562                 dev_err(&pdev->dev, "Failed to add devices\n");
 563                 return ret;
 564         }
 565
 566         ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
 567         if (ret) {
 568                 dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
 569                 return ret;
 570         }
 571
 572         /*
 573          * There is known hw bug. Upon reset BIT 5 of register
 574          * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
 575          * later it's set to 1(masked) automatically by hardware. So we
 576          * have the software workaround here to unmaksed it in order to let
 577          * charger interrutp work.
 578          */
 579         regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1,
 580                                 BXTWC_MIRQLVL1_MCHGR, 0);
 581
 582         return 0;
 583 }
 584
 585 static int bxtwc_remove(struct platform_device *pdev)
 586 {
 587         sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
 588
 589         return 0;
 590 }
 591
 592 static void bxtwc_shutdown(struct platform_device *pdev)
 593 {
 594         struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
 595
 596         disable_irq(pmic->irq);
 597 }
 598
 599 #ifdef CONFIG_PM_SLEEP
 600 static int bxtwc_suspend(struct device *dev)
 601 {
 602         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 603
 604         disable_irq(pmic->irq);
 605
 606         return 0;
 607 }
 608
 609 static int bxtwc_resume(struct device *dev)
 610 {
 611         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 612
 613         enable_irq(pmic->irq);
 614         return 0;
 615 }
 616 #endif
 617 static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
 618
 619 static const struct acpi_device_id bxtwc_acpi_ids[] = {
 620         { "INT34D3", },
 621         { }
 622 };
 623 MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
 624
 625 static struct platform_driver bxtwc_driver = {
 626         .probe = bxtwc_probe,
 627         .remove = bxtwc_remove,
 628         .shutdown = bxtwc_shutdown,
 629         .driver = {
 630                 .name   = "BXTWC PMIC",
 631                 .pm     = &bxtwc_pm_ops,
 632                 .acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
 633         },
 634 };
 635
 636 module_platform_driver(bxtwc_driver);
 637
 638 MODULE_LICENSE("GPL v2");
 639 MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");