drivers/misc/habanalabs/goya/goya.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Copyright 2016-2019 HabanaLabs, Ltd.
   5  * All Rights Reserved.
   6  */
   7
   8 #include "goyaP.h"
   9 #include "include/hw_ip/mmu/mmu_general.h"
  10 #include "include/hw_ip/mmu/mmu_v1_0.h"
  11 #include "include/goya/asic_reg/goya_masks.h"
  12
  13 #include <linux/pci.h>
  14 #include <linux/genalloc.h>
  15 #include <linux/hwmon.h>
  16 #include <linux/io-64-nonatomic-lo-hi.h>
  17
  18 /*
  19  * GOYA security scheme:
  20  *
  21  * 1. Host is protected by:
  22  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
  23  *        - MMU
  24  *
  25  * 2. DRAM is protected by:
  26  *        - Range registers (protect the first 512MB)
  27  *        - MMU (isolation between users)
  28  *
  29  * 3. Configuration is protected by:
  30  *        - Range registers
  31  *        - Protection bits
  32  *
  33  * When MMU is disabled:
  34  *
  35  * QMAN DMA: PQ, CQ, CP, DMA are secured.
  36  * PQ, CB and the data are on the host.
  37  *
  38  * QMAN TPC/MME:
  39  * PQ, CQ and CP are not secured.
  40  * PQ, CB and the data are on the SRAM/DRAM.
  41  *
  42  * Since QMAN DMA is secured, KMD is parsing the DMA CB:
  43  *     - KMD checks DMA pointer
  44  *     - WREG, MSG_PROT are not allowed.
  45  *     - MSG_LONG/SHORT are allowed.
  46  *
  47  * A read/write transaction by the QMAN to a protected area will succeed if
  48  * and only if the QMAN's CP is secured and MSG_PROT is used
  49  *
  50  *
  51  * When MMU is enabled:
  52  *
  53  * QMAN DMA: PQ, CQ and CP are secured.
  54  * MMU is set to bypass on the Secure props register of the QMAN.
  55  * The reasons we don't enable MMU for PQ, CQ and CP are:
  56  *     - PQ entry is in kernel address space and KMD doesn't map it.
  57  *     - CP writes to MSIX register and to kernel address space (completion
  58  *       queue).
  59  *
  60  * DMA is not secured but because CP is secured, KMD still needs to parse the
  61  * CB, but doesn't need to check the DMA addresses.
  62  *
  63  * For QMAN DMA 0, DMA is also secured because only KMD uses this DMA and KMD
  64  * doesn't map memory in MMU.
  65  *
  66  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
  67  *
  68  * DMA RR does NOT protect host because DMA is not secured
  69  *
  70  */
  71
  72 #define GOYA_MMU_REGS_NUM               63
  73
  74 #define GOYA_DMA_POOL_BLK_SIZE          0x100           /* 256 bytes */
  75
  76 #define GOYA_RESET_TIMEOUT_MSEC         500             /* 500ms */
  77 #define GOYA_PLDM_RESET_TIMEOUT_MSEC    20000           /* 20s */
  78 #define GOYA_RESET_WAIT_MSEC            1               /* 1ms */
  79 #define GOYA_CPU_RESET_WAIT_MSEC        100             /* 100ms */
  80 #define GOYA_PLDM_RESET_WAIT_MSEC       1000            /* 1s */
  81 #define GOYA_TEST_QUEUE_WAIT_USEC       100000          /* 100ms */
  82 #define GOYA_PLDM_MMU_TIMEOUT_USEC      (MMU_CONFIG_TIMEOUT_USEC * 100)
  83 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC    (HL_DEVICE_TIMEOUT_USEC * 30)
  84
  85 #define GOYA_QMAN0_FENCE_VAL            0xD169B243
  86
  87 #define GOYA_MAX_STRING_LEN             20
  88
  89 #define GOYA_CB_POOL_CB_CNT             512
  90 #define GOYA_CB_POOL_CB_SIZE            0x20000         /* 128KB */
  91
  92 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
  93                 "goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
  94                 "goya cq 4", "goya cpu eq"
  95 };
  96
  97 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
  98         [PACKET_WREG_32]        = sizeof(struct packet_wreg32),
  99         [PACKET_WREG_BULK]      = sizeof(struct packet_wreg_bulk),
 100         [PACKET_MSG_LONG]       = sizeof(struct packet_msg_long),
 101         [PACKET_MSG_SHORT]      = sizeof(struct packet_msg_short),
 102         [PACKET_CP_DMA]         = sizeof(struct packet_cp_dma),
 103         [PACKET_MSG_PROT]       = sizeof(struct packet_msg_prot),
 104         [PACKET_FENCE]          = sizeof(struct packet_fence),
 105         [PACKET_LIN_DMA]        = sizeof(struct packet_lin_dma),
 106         [PACKET_NOP]            = sizeof(struct packet_nop),
 107         [PACKET_STOP]           = sizeof(struct packet_stop)
 108 };
 109
 110 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
 111         mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
 112         mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
 113         mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
 114         mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
 115         mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
 116         mmTPC0_QM_GLBL_SECURE_PROPS,
 117         mmTPC0_QM_GLBL_NON_SECURE_PROPS,
 118         mmTPC0_CMDQ_GLBL_SECURE_PROPS,
 119         mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
 120         mmTPC0_CFG_ARUSER,
 121         mmTPC0_CFG_AWUSER,
 122         mmTPC1_QM_GLBL_SECURE_PROPS,
 123         mmTPC1_QM_GLBL_NON_SECURE_PROPS,
 124         mmTPC1_CMDQ_GLBL_SECURE_PROPS,
 125         mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
 126         mmTPC1_CFG_ARUSER,
 127         mmTPC1_CFG_AWUSER,
 128         mmTPC2_QM_GLBL_SECURE_PROPS,
 129         mmTPC2_QM_GLBL_NON_SECURE_PROPS,
 130         mmTPC2_CMDQ_GLBL_SECURE_PROPS,
 131         mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
 132         mmTPC2_CFG_ARUSER,
 133         mmTPC2_CFG_AWUSER,
 134         mmTPC3_QM_GLBL_SECURE_PROPS,
 135         mmTPC3_QM_GLBL_NON_SECURE_PROPS,
 136         mmTPC3_CMDQ_GLBL_SECURE_PROPS,
 137         mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
 138         mmTPC3_CFG_ARUSER,
 139         mmTPC3_CFG_AWUSER,
 140         mmTPC4_QM_GLBL_SECURE_PROPS,
 141         mmTPC4_QM_GLBL_NON_SECURE_PROPS,
 142         mmTPC4_CMDQ_GLBL_SECURE_PROPS,
 143         mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
 144         mmTPC4_CFG_ARUSER,
 145         mmTPC4_CFG_AWUSER,
 146         mmTPC5_QM_GLBL_SECURE_PROPS,
 147         mmTPC5_QM_GLBL_NON_SECURE_PROPS,
 148         mmTPC5_CMDQ_GLBL_SECURE_PROPS,
 149         mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
 150         mmTPC5_CFG_ARUSER,
 151         mmTPC5_CFG_AWUSER,
 152         mmTPC6_QM_GLBL_SECURE_PROPS,
 153         mmTPC6_QM_GLBL_NON_SECURE_PROPS,
 154         mmTPC6_CMDQ_GLBL_SECURE_PROPS,
 155         mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
 156         mmTPC6_CFG_ARUSER,
 157         mmTPC6_CFG_AWUSER,
 158         mmTPC7_QM_GLBL_SECURE_PROPS,
 159         mmTPC7_QM_GLBL_NON_SECURE_PROPS,
 160         mmTPC7_CMDQ_GLBL_SECURE_PROPS,
 161         mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
 162         mmTPC7_CFG_ARUSER,
 163         mmTPC7_CFG_AWUSER,
 164         mmMME_QM_GLBL_SECURE_PROPS,
 165         mmMME_QM_GLBL_NON_SECURE_PROPS,
 166         mmMME_CMDQ_GLBL_SECURE_PROPS,
 167         mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
 168         mmMME_SBA_CONTROL_DATA,
 169         mmMME_SBB_CONTROL_DATA,
 170         mmMME_SBC_CONTROL_DATA,
 171         mmMME_WBC_CONTROL_DATA,
 172         mmPCIE_WRAP_PSOC_ARUSER,
 173         mmPCIE_WRAP_PSOC_AWUSER
 174 };
 175
 176 static u32 goya_all_events[] = {
 177         GOYA_ASYNC_EVENT_ID_PCIE_IF,
 178         GOYA_ASYNC_EVENT_ID_TPC0_ECC,
 179         GOYA_ASYNC_EVENT_ID_TPC1_ECC,
 180         GOYA_ASYNC_EVENT_ID_TPC2_ECC,
 181         GOYA_ASYNC_EVENT_ID_TPC3_ECC,
 182         GOYA_ASYNC_EVENT_ID_TPC4_ECC,
 183         GOYA_ASYNC_EVENT_ID_TPC5_ECC,
 184         GOYA_ASYNC_EVENT_ID_TPC6_ECC,
 185         GOYA_ASYNC_EVENT_ID_TPC7_ECC,
 186         GOYA_ASYNC_EVENT_ID_MME_ECC,
 187         GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
 188         GOYA_ASYNC_EVENT_ID_MMU_ECC,
 189         GOYA_ASYNC_EVENT_ID_DMA_MACRO,
 190         GOYA_ASYNC_EVENT_ID_DMA_ECC,
 191         GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
 192         GOYA_ASYNC_EVENT_ID_PSOC_MEM,
 193         GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
 194         GOYA_ASYNC_EVENT_ID_SRAM0,
 195         GOYA_ASYNC_EVENT_ID_SRAM1,
 196         GOYA_ASYNC_EVENT_ID_SRAM2,
 197         GOYA_ASYNC_EVENT_ID_SRAM3,
 198         GOYA_ASYNC_EVENT_ID_SRAM4,
 199         GOYA_ASYNC_EVENT_ID_SRAM5,
 200         GOYA_ASYNC_EVENT_ID_SRAM6,
 201         GOYA_ASYNC_EVENT_ID_SRAM7,
 202         GOYA_ASYNC_EVENT_ID_SRAM8,
 203         GOYA_ASYNC_EVENT_ID_SRAM9,
 204         GOYA_ASYNC_EVENT_ID_SRAM10,
 205         GOYA_ASYNC_EVENT_ID_SRAM11,
 206         GOYA_ASYNC_EVENT_ID_SRAM12,
 207         GOYA_ASYNC_EVENT_ID_SRAM13,
 208         GOYA_ASYNC_EVENT_ID_SRAM14,
 209         GOYA_ASYNC_EVENT_ID_SRAM15,
 210         GOYA_ASYNC_EVENT_ID_SRAM16,
 211         GOYA_ASYNC_EVENT_ID_SRAM17,
 212         GOYA_ASYNC_EVENT_ID_SRAM18,
 213         GOYA_ASYNC_EVENT_ID_SRAM19,
 214         GOYA_ASYNC_EVENT_ID_SRAM20,
 215         GOYA_ASYNC_EVENT_ID_SRAM21,
 216         GOYA_ASYNC_EVENT_ID_SRAM22,
 217         GOYA_ASYNC_EVENT_ID_SRAM23,
 218         GOYA_ASYNC_EVENT_ID_SRAM24,
 219         GOYA_ASYNC_EVENT_ID_SRAM25,
 220         GOYA_ASYNC_EVENT_ID_SRAM26,
 221         GOYA_ASYNC_EVENT_ID_SRAM27,
 222         GOYA_ASYNC_EVENT_ID_SRAM28,
 223         GOYA_ASYNC_EVENT_ID_SRAM29,
 224         GOYA_ASYNC_EVENT_ID_GIC500,
 225         GOYA_ASYNC_EVENT_ID_PLL0,
 226         GOYA_ASYNC_EVENT_ID_PLL1,
 227         GOYA_ASYNC_EVENT_ID_PLL3,
 228         GOYA_ASYNC_EVENT_ID_PLL4,
 229         GOYA_ASYNC_EVENT_ID_PLL5,
 230         GOYA_ASYNC_EVENT_ID_PLL6,
 231         GOYA_ASYNC_EVENT_ID_AXI_ECC,
 232         GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
 233         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
 234         GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
 235         GOYA_ASYNC_EVENT_ID_PCIE_DEC,
 236         GOYA_ASYNC_EVENT_ID_TPC0_DEC,
 237         GOYA_ASYNC_EVENT_ID_TPC1_DEC,
 238         GOYA_ASYNC_EVENT_ID_TPC2_DEC,
 239         GOYA_ASYNC_EVENT_ID_TPC3_DEC,
 240         GOYA_ASYNC_EVENT_ID_TPC4_DEC,
 241         GOYA_ASYNC_EVENT_ID_TPC5_DEC,
 242         GOYA_ASYNC_EVENT_ID_TPC6_DEC,
 243         GOYA_ASYNC_EVENT_ID_TPC7_DEC,
 244         GOYA_ASYNC_EVENT_ID_MME_WACS,
 245         GOYA_ASYNC_EVENT_ID_MME_WACSD,
 246         GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
 247         GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
 248         GOYA_ASYNC_EVENT_ID_PSOC,
 249         GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
 250         GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
 251         GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
 252         GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
 253         GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
 254         GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
 255         GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
 256         GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
 257         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
 258         GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
 259         GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
 260         GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
 261         GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
 262         GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
 263         GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
 264         GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
 265         GOYA_ASYNC_EVENT_ID_TPC0_QM,
 266         GOYA_ASYNC_EVENT_ID_TPC1_QM,
 267         GOYA_ASYNC_EVENT_ID_TPC2_QM,
 268         GOYA_ASYNC_EVENT_ID_TPC3_QM,
 269         GOYA_ASYNC_EVENT_ID_TPC4_QM,
 270         GOYA_ASYNC_EVENT_ID_TPC5_QM,
 271         GOYA_ASYNC_EVENT_ID_TPC6_QM,
 272         GOYA_ASYNC_EVENT_ID_TPC7_QM,
 273         GOYA_ASYNC_EVENT_ID_MME_QM,
 274         GOYA_ASYNC_EVENT_ID_MME_CMDQ,
 275         GOYA_ASYNC_EVENT_ID_DMA0_QM,
 276         GOYA_ASYNC_EVENT_ID_DMA1_QM,
 277         GOYA_ASYNC_EVENT_ID_DMA2_QM,
 278         GOYA_ASYNC_EVENT_ID_DMA3_QM,
 279         GOYA_ASYNC_EVENT_ID_DMA4_QM,
 280         GOYA_ASYNC_EVENT_ID_DMA0_CH,
 281         GOYA_ASYNC_EVENT_ID_DMA1_CH,
 282         GOYA_ASYNC_EVENT_ID_DMA2_CH,
 283         GOYA_ASYNC_EVENT_ID_DMA3_CH,
 284         GOYA_ASYNC_EVENT_ID_DMA4_CH,
 285         GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
 286         GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
 287         GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
 288         GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
 289         GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
 290         GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
 291         GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
 292         GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
 293         GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
 294         GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
 295         GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
 296         GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
 297         GOYA_ASYNC_EVENT_ID_DMA_BM_CH4
 298 };
 299
 300 void goya_get_fixed_properties(struct hl_device *hdev)
 301 {
 302         struct asic_fixed_properties *prop = &hdev->asic_prop;
 303         int i;
 304
 305         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
 306                 prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
 307                 prop->hw_queues_props[i].kmd_only = 0;
 308         }
 309
 310         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
 311                 prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
 312                 prop->hw_queues_props[i].kmd_only = 1;
 313         }
 314
 315         for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
 316                         NUMBER_OF_INT_HW_QUEUES; i++) {
 317                 prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
 318                 prop->hw_queues_props[i].kmd_only = 0;
 319         }
 320
 321         for (; i < HL_MAX_QUEUES; i++)
 322                 prop->hw_queues_props[i].type = QUEUE_TYPE_NA;
 323
 324         prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
 325
 326         prop->dram_base_address = DRAM_PHYS_BASE;
 327         prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
 328         prop->dram_end_address = prop->dram_base_address + prop->dram_size;
 329         prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
 330
 331         prop->sram_base_address = SRAM_BASE_ADDR;
 332         prop->sram_size = SRAM_SIZE;
 333         prop->sram_end_address = prop->sram_base_address + prop->sram_size;
 334         prop->sram_user_base_address = prop->sram_base_address +
 335                                                 SRAM_USER_BASE_OFFSET;
 336
 337         prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
 338         prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
 339         if (hdev->pldm)
 340                 prop->mmu_pgt_size = 0x800000; /* 8MB */
 341         else
 342                 prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
 343         prop->mmu_pte_size = HL_PTE_SIZE;
 344         prop->mmu_hop_table_size = HOP_TABLE_SIZE;
 345         prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE;
 346         prop->dram_page_size = PAGE_SIZE_2MB;
 347
 348         prop->host_phys_base_address = HOST_PHYS_BASE;
 349         prop->va_space_host_start_address = VA_HOST_SPACE_START;
 350         prop->va_space_host_end_address = VA_HOST_SPACE_END;
 351         prop->va_space_dram_start_address = VA_DDR_SPACE_START;
 352         prop->va_space_dram_end_address = VA_DDR_SPACE_END;
 353         prop->dram_size_for_default_page_mapping =
 354                         prop->va_space_dram_end_address;
 355         prop->cfg_size = CFG_SIZE;
 356         prop->max_asid = MAX_ASID;
 357         prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
 358         prop->high_pll = PLL_HIGH_DEFAULT;
 359         prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
 360         prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
 361         prop->max_power_default = MAX_POWER_DEFAULT;
 362         prop->tpc_enabled_mask = TPC_ENABLED_MASK;
 363         prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
 364         prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
 365 }
 366
 367 /*
 368  * goya_pci_bars_map - Map PCI BARS of Goya device
 369  *
 370  * @hdev: pointer to hl_device structure
 371  *
 372  * Request PCI regions and map them to kernel virtual addresses.
 373  * Returns 0 on success
 374  *
 375  */
 376 static int goya_pci_bars_map(struct hl_device *hdev)
 377 {
 378         static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
 379         bool is_wc[3] = {false, false, true};
 380         int rc;
 381
 382         rc = hl_pci_bars_map(hdev, name, is_wc);
 383         if (rc)
 384                 return rc;
 385
 386         hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
 387                         (CFG_BASE - SRAM_BASE_ADDR);
 388
 389         return 0;
 390 }
 391
 392 /*
 393  * goya_set_ddr_bar_base - set DDR bar to map specific device address
 394  *
 395  * @hdev: pointer to hl_device structure
 396  * @addr: address in DDR. Must be aligned to DDR bar size
 397  *
 398  * This function configures the iATU so that the DDR bar will start at the
 399  * specified addr.
 400  *
 401  */
 402 static int goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
 403 {
 404         struct goya_device *goya = hdev->asic_specific;
 405         int rc;
 406
 407         if ((goya) && (goya->ddr_bar_cur_addr == addr))
 408                 return 0;
 409
 410         /* Inbound Region 1 - Bar 4 - Point to DDR */
 411         rc = hl_pci_set_dram_bar_base(hdev, 1, 4, addr);
 412         if (rc)
 413                 return rc;
 414
 415         if (goya)
 416                 goya->ddr_bar_cur_addr = addr;
 417
 418         return 0;
 419 }
 420
 421 /*
 422  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
 423  *
 424  * @hdev: pointer to hl_device structure
 425  *
 426  * This is needed in case the firmware doesn't initialize the iATU
 427  *
 428  */
 429 static int goya_init_iatu(struct hl_device *hdev)
 430 {
 431         return hl_pci_init_iatu(hdev, SRAM_BASE_ADDR, DRAM_PHYS_BASE,
 432                                 HOST_PHYS_SIZE);
 433 }
 434
 435 /*
 436  * goya_early_init - GOYA early initialization code
 437  *
 438  * @hdev: pointer to hl_device structure
 439  *
 440  * Verify PCI bars
 441  * Set DMA masks
 442  * PCI controller initialization
 443  * Map PCI bars
 444  *
 445  */
 446 static int goya_early_init(struct hl_device *hdev)
 447 {
 448         struct asic_fixed_properties *prop = &hdev->asic_prop;
 449         struct pci_dev *pdev = hdev->pdev;
 450         u32 val;
 451         int rc;
 452
 453         goya_get_fixed_properties(hdev);
 454
 455         /* Check BAR sizes */
 456         if (pci_resource_len(pdev, SRAM_CFG_BAR_ID) != CFG_BAR_SIZE) {
 457                 dev_err(hdev->dev,
 458                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 459                         SRAM_CFG_BAR_ID,
 460                         (unsigned long long) pci_resource_len(pdev,
 461                                                         SRAM_CFG_BAR_ID),
 462                         CFG_BAR_SIZE);
 463                 return -ENODEV;
 464         }
 465
 466         if (pci_resource_len(pdev, MSIX_BAR_ID) != MSIX_BAR_SIZE) {
 467                 dev_err(hdev->dev,
 468                         "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n",
 469                         MSIX_BAR_ID,
 470                         (unsigned long long) pci_resource_len(pdev,
 471                                                                 MSIX_BAR_ID),
 472                         MSIX_BAR_SIZE);
 473                 return -ENODEV;
 474         }
 475
 476         prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
 477
 478         rc = hl_pci_init(hdev, 39);
 479         if (rc)
 480                 return rc;
 481
 482         if (!hdev->pldm) {
 483                 val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
 484                 if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
 485                         dev_warn(hdev->dev,
 486                                 "PCI strap is not configured correctly, PCI bus errors may occur\n");
 487         }
 488
 489         return 0;
 490 }
 491
 492 /*
 493  * goya_early_fini - GOYA early finalization code
 494  *
 495  * @hdev: pointer to hl_device structure
 496  *
 497  * Unmap PCI bars
 498  *
 499  */
 500 static int goya_early_fini(struct hl_device *hdev)
 501 {
 502         hl_pci_fini(hdev);
 503
 504         return 0;
 505 }
 506
 507 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
 508 {
 509         /* mask to zero the MMBP and ASID bits */
 510         WREG32_AND(reg, ~0x7FF);
 511         WREG32_OR(reg, asid);
 512 }
 513
 514 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
 515 {
 516         struct goya_device *goya = hdev->asic_specific;
 517
 518         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
 519                 return;
 520
 521         if (secure)
 522                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
 523         else
 524                 WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
 525
 526         RREG32(mmDMA_QM_0_GLBL_PROT);
 527 }
 528
 529 /*
 530  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
 531  *
 532  * @hdev: pointer to hl_device structure
 533  *
 534  */
 535 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
 536 {
 537         struct asic_fixed_properties *prop = &hdev->asic_prop;
 538
 539         prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR);
 540         prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF);
 541         prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD);
 542         prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
 543 }
 544
 545 int goya_late_init(struct hl_device *hdev)
 546 {
 547         struct asic_fixed_properties *prop = &hdev->asic_prop;
 548         int rc;
 549
 550         rc = goya_armcp_info_get(hdev);
 551         if (rc) {
 552                 dev_err(hdev->dev, "Failed to get armcp info\n");
 553                 return rc;
 554         }
 555
 556         /* Now that we have the DRAM size in ASIC prop, we need to check
 557          * its size and configure the DMA_IF DDR wrap protection (which is in
 558          * the MMU block) accordingly. The value is the log2 of the DRAM size
 559          */
 560         WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
 561
 562         rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS);
 563         if (rc) {
 564                 dev_err(hdev->dev, "Failed to enable PCI access from CPU\n");
 565                 return rc;
 566         }
 567
 568         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
 569                         GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
 570
 571         goya_fetch_psoc_frequency(hdev);
 572
 573         rc = goya_mmu_clear_pgt_range(hdev);
 574         if (rc) {
 575                 dev_err(hdev->dev, "Failed to clear MMU page tables range\n");
 576                 goto disable_pci_access;
 577         }
 578
 579         rc = goya_mmu_set_dram_default_page(hdev);
 580         if (rc) {
 581                 dev_err(hdev->dev, "Failed to set DRAM default page\n");
 582                 goto disable_pci_access;
 583         }
 584
 585         return 0;
 586
 587 disable_pci_access:
 588         hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
 589
 590         return rc;
 591 }
 592
 593 /*
 594  * goya_late_fini - GOYA late tear-down code
 595  *
 596  * @hdev: pointer to hl_device structure
 597  *
 598  * Free sensors allocated structures
 599  */
 600 void goya_late_fini(struct hl_device *hdev)
 601 {
 602         const struct hwmon_channel_info **channel_info_arr;
 603         int i = 0;
 604
 605         if (!hdev->hl_chip_info->info)
 606                 return;
 607
 608         channel_info_arr = hdev->hl_chip_info->info;
 609
 610         while (channel_info_arr[i]) {
 611                 kfree(channel_info_arr[i]->config);
 612                 kfree(channel_info_arr[i]);
 613                 i++;
 614         }
 615
 616         kfree(channel_info_arr);
 617
 618         hdev->hl_chip_info->info = NULL;
 619 }
 620
 621 /*
 622  * goya_sw_init - Goya software initialization code
 623  *
 624  * @hdev: pointer to hl_device structure
 625  *
 626  */
 627 static int goya_sw_init(struct hl_device *hdev)
 628 {
 629         struct goya_device *goya;
 630         int rc;
 631
 632         /* Allocate device structure */
 633         goya = kzalloc(sizeof(*goya), GFP_KERNEL);
 634         if (!goya)
 635                 return -ENOMEM;
 636
 637         /* according to goya_init_iatu */
 638         goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
 639
 640         goya->mme_clk = GOYA_PLL_FREQ_LOW;
 641         goya->tpc_clk = GOYA_PLL_FREQ_LOW;
 642         goya->ic_clk = GOYA_PLL_FREQ_LOW;
 643
 644         hdev->asic_specific = goya;
 645
 646         /* Create DMA pool for small allocations */
 647         hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
 648                         &hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
 649         if (!hdev->dma_pool) {
 650                 dev_err(hdev->dev, "failed to create DMA pool\n");
 651                 rc = -ENOMEM;
 652                 goto free_goya_device;
 653         }
 654
 655         hdev->cpu_accessible_dma_mem =
 656                         hdev->asic_funcs->dma_alloc_coherent(hdev,
 657                                         HL_CPU_ACCESSIBLE_MEM_SIZE,
 658                                         &hdev->cpu_accessible_dma_address,
 659                                         GFP_KERNEL | __GFP_ZERO);
 660
 661         if (!hdev->cpu_accessible_dma_mem) {
 662                 rc = -ENOMEM;
 663                 goto free_dma_pool;
 664         }
 665
 666         hdev->cpu_accessible_dma_pool = gen_pool_create(HL_CPU_PKT_SHIFT, -1);
 667         if (!hdev->cpu_accessible_dma_pool) {
 668                 dev_err(hdev->dev,
 669                         "Failed to create CPU accessible DMA pool\n");
 670                 rc = -ENOMEM;
 671                 goto free_cpu_pq_dma_mem;
 672         }
 673
 674         rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
 675                                 (uintptr_t) hdev->cpu_accessible_dma_mem,
 676                                 HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
 677         if (rc) {
 678                 dev_err(hdev->dev,
 679                         "Failed to add memory to CPU accessible DMA pool\n");
 680                 rc = -EFAULT;
 681                 goto free_cpu_pq_pool;
 682         }
 683
 684         spin_lock_init(&goya->hw_queues_lock);
 685
 686         return 0;
 687
 688 free_cpu_pq_pool:
 689         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 690 free_cpu_pq_dma_mem:
 691         hdev->asic_funcs->dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE,
 692                         hdev->cpu_accessible_dma_mem,
 693                         hdev->cpu_accessible_dma_address);
 694 free_dma_pool:
 695         dma_pool_destroy(hdev->dma_pool);
 696 free_goya_device:
 697         kfree(goya);
 698
 699         return rc;
 700 }
 701
 702 /*
 703  * goya_sw_fini - Goya software tear-down code
 704  *
 705  * @hdev: pointer to hl_device structure
 706  *
 707  */
 708 static int goya_sw_fini(struct hl_device *hdev)
 709 {
 710         struct goya_device *goya = hdev->asic_specific;
 711
 712         gen_pool_destroy(hdev->cpu_accessible_dma_pool);
 713
 714         hdev->asic_funcs->dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE,
 715                         hdev->cpu_accessible_dma_mem,
 716                         hdev->cpu_accessible_dma_address);
 717
 718         dma_pool_destroy(hdev->dma_pool);
 719
 720         kfree(goya);
 721
 722         return 0;
 723 }
 724
 725 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
 726                 dma_addr_t bus_address)
 727 {
 728         struct goya_device *goya = hdev->asic_specific;
 729         u32 mtr_base_lo, mtr_base_hi;
 730         u32 so_base_lo, so_base_hi;
 731         u32 gic_base_lo, gic_base_hi;
 732         u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
 733
 734         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 735         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
 736         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 737         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
 738
 739         gic_base_lo =
 740                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 741         gic_base_hi =
 742                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 743
 744         WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
 745         WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
 746
 747         WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
 748         WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
 749         WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
 750
 751         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
 752         WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
 753         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
 754         WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
 755         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
 756         WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
 757         WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
 758                         GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
 759
 760         /* PQ has buffer of 2 cache lines, while CQ has 8 lines */
 761         WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
 762         WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
 763
 764         if (goya->hw_cap_initialized & HW_CAP_MMU)
 765                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
 766         else
 767                 WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
 768
 769         WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN);
 770         WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
 771 }
 772
 773 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
 774 {
 775         u32 gic_base_lo, gic_base_hi;
 776         u64 sob_addr;
 777         u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
 778
 779         gic_base_lo =
 780                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 781         gic_base_hi =
 782                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
 783
 784         WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
 785         WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
 786         WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
 787                         GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
 788
 789         if (dma_id)
 790                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
 791                                 (dma_id - 1) * 4;
 792         else
 793                 sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
 794
 795         WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + reg_off, lower_32_bits(sob_addr));
 796         WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
 797         WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
 798 }
 799
 800 /*
 801  * goya_init_dma_qmans - Initialize QMAN DMA registers
 802  *
 803  * @hdev: pointer to hl_device structure
 804  *
 805  * Initialize the H/W registers of the QMAN DMA channels
 806  *
 807  */
 808 void goya_init_dma_qmans(struct hl_device *hdev)
 809 {
 810         struct goya_device *goya = hdev->asic_specific;
 811         struct hl_hw_queue *q;
 812         dma_addr_t bus_address;
 813         int i;
 814
 815         if (goya->hw_cap_initialized & HW_CAP_DMA)
 816                 return;
 817
 818         q = &hdev->kernel_queues[0];
 819
 820         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
 821                 bus_address = q->bus_address +
 822                                 hdev->asic_prop.host_phys_base_address;
 823
 824                 goya_init_dma_qman(hdev, i, bus_address);
 825                 goya_init_dma_ch(hdev, i);
 826         }
 827
 828         goya->hw_cap_initialized |= HW_CAP_DMA;
 829 }
 830
 831 /*
 832  * goya_disable_external_queues - Disable external queues
 833  *
 834  * @hdev: pointer to hl_device structure
 835  *
 836  */
 837 static void goya_disable_external_queues(struct hl_device *hdev)
 838 {
 839         WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
 840         WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
 841         WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
 842         WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
 843         WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
 844 }
 845
 846 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
 847                                 u32 cp_sts_reg, u32 glbl_sts0_reg)
 848 {
 849         int rc;
 850         u32 status;
 851
 852         /* use the values of TPC0 as they are all the same*/
 853
 854         WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
 855
 856         status = RREG32(cp_sts_reg);
 857         if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
 858                 rc = hl_poll_timeout(
 859                         hdev,
 860                         cp_sts_reg,
 861                         status,
 862                         !(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
 863                         1000,
 864                         QMAN_FENCE_TIMEOUT_USEC);
 865
 866                 /* if QMAN is stuck in fence no need to check for stop */
 867                 if (rc)
 868                         return 0;
 869         }
 870
 871         rc = hl_poll_timeout(
 872                 hdev,
 873                 glbl_sts0_reg,
 874                 status,
 875                 (status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
 876                 1000,
 877                 QMAN_STOP_TIMEOUT_USEC);
 878
 879         if (rc) {
 880                 dev_err(hdev->dev,
 881                         "Timeout while waiting for QMAN to stop\n");
 882                 return -EINVAL;
 883         }
 884
 885         return 0;
 886 }
 887
 888 /*
 889  * goya_stop_external_queues - Stop external queues
 890  *
 891  * @hdev: pointer to hl_device structure
 892  *
 893  * Returns 0 on success
 894  *
 895  */
 896 static int goya_stop_external_queues(struct hl_device *hdev)
 897 {
 898         int rc, retval = 0;
 899
 900         rc = goya_stop_queue(hdev,
 901                         mmDMA_QM_0_GLBL_CFG1,
 902                         mmDMA_QM_0_CP_STS,
 903                         mmDMA_QM_0_GLBL_STS0);
 904
 905         if (rc) {
 906                 dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
 907                 retval = -EIO;
 908         }
 909
 910         rc = goya_stop_queue(hdev,
 911                         mmDMA_QM_1_GLBL_CFG1,
 912                         mmDMA_QM_1_CP_STS,
 913                         mmDMA_QM_1_GLBL_STS0);
 914
 915         if (rc) {
 916                 dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
 917                 retval = -EIO;
 918         }
 919
 920         rc = goya_stop_queue(hdev,
 921                         mmDMA_QM_2_GLBL_CFG1,
 922                         mmDMA_QM_2_CP_STS,
 923                         mmDMA_QM_2_GLBL_STS0);
 924
 925         if (rc) {
 926                 dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
 927                 retval = -EIO;
 928         }
 929
 930         rc = goya_stop_queue(hdev,
 931                         mmDMA_QM_3_GLBL_CFG1,
 932                         mmDMA_QM_3_CP_STS,
 933                         mmDMA_QM_3_GLBL_STS0);
 934
 935         if (rc) {
 936                 dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
 937                 retval = -EIO;
 938         }
 939
 940         rc = goya_stop_queue(hdev,
 941                         mmDMA_QM_4_GLBL_CFG1,
 942                         mmDMA_QM_4_CP_STS,
 943                         mmDMA_QM_4_GLBL_STS0);
 944
 945         if (rc) {
 946                 dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
 947                 retval = -EIO;
 948         }
 949
 950         return retval;
 951 }
 952
 953 /*
 954  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
 955  *
 956  * @hdev: pointer to hl_device structure
 957  *
 958  * Returns 0 on success
 959  *
 960  */
 961 int goya_init_cpu_queues(struct hl_device *hdev)
 962 {
 963         struct goya_device *goya = hdev->asic_specific;
 964         struct hl_eq *eq;
 965         dma_addr_t bus_address;
 966         u32 status;
 967         struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
 968         int err;
 969
 970         if (!hdev->cpu_queues_enable)
 971                 return 0;
 972
 973         if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
 974                 return 0;
 975
 976         eq = &hdev->event_queue;
 977
 978         bus_address = cpu_pq->bus_address +
 979                         hdev->asic_prop.host_phys_base_address;
 980         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_0, lower_32_bits(bus_address));
 981         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_1, upper_32_bits(bus_address));
 982
 983         bus_address = eq->bus_address + hdev->asic_prop.host_phys_base_address;
 984         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_2, lower_32_bits(bus_address));
 985         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_3, upper_32_bits(bus_address));
 986
 987         bus_address = hdev->cpu_accessible_dma_address +
 988                         hdev->asic_prop.host_phys_base_address;
 989         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_8, lower_32_bits(bus_address));
 990         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_9, upper_32_bits(bus_address));
 991
 992         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_5, HL_QUEUE_SIZE_IN_BYTES);
 993         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_4, HL_EQ_SIZE_IN_BYTES);
 994         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_10, HL_CPU_ACCESSIBLE_MEM_SIZE);
 995
 996         /* Used for EQ CI */
 997         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_6, 0);
 998
 999         WREG32(mmCPU_IF_PF_PQ_PI, 0);
1000
1001         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_7, PQ_INIT_STATUS_READY_FOR_CP);
1002
1003         WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1004                         GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1005
1006         err = hl_poll_timeout(
1007                 hdev,
1008                 mmPSOC_GLOBAL_CONF_SCRATCHPAD_7,
1009                 status,
1010                 (status == PQ_INIT_STATUS_READY_FOR_HOST),
1011                 1000,
1012                 GOYA_CPU_TIMEOUT_USEC);
1013
1014         if (err) {
1015                 dev_err(hdev->dev,
1016                         "Failed to communicate with ARM CPU (ArmCP timeout)\n");
1017                 return -EIO;
1018         }
1019
1020         goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1021         return 0;
1022 }
1023
1024 static void goya_set_pll_refclk(struct hl_device *hdev)
1025 {
1026         WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1027         WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1028         WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1029         WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1030
1031         WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1032         WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1033         WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1034         WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1035
1036         WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1037         WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1038         WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1039         WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1040
1041         WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1042         WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1043         WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1044         WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1045
1046         WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1047         WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1048         WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1049         WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1050
1051         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1052         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1053         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1054         WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1055
1056         WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1057         WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1058         WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1059         WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1060 }
1061
1062 static void goya_disable_clk_rlx(struct hl_device *hdev)
1063 {
1064         WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1065         WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1066 }
1067
1068 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1069 {
1070         u64 tpc_eml_address;
1071         u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1072         int err, slm_index;
1073
1074         tpc_offset = tpc_id * 0x40000;
1075         tpc_eml_offset = tpc_id * 0x200000;
1076         tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1077         tpc_slm_offset = tpc_eml_address + 0x100000;
1078
1079         /*
1080          * Workaround for Bug H2 #2443 :
1081          * "TPC SB is not initialized on chip reset"
1082          */
1083
1084         val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1085         if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1086                 dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1087                         tpc_id);
1088
1089         WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1090
1091         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1092         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1093         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1094         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1095         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1096         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1097         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1098         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1099         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1100         WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1101
1102         WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1103                 1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1104
1105         err = hl_poll_timeout(
1106                 hdev,
1107                 mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1108                 val,
1109                 (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1110                 1000,
1111                 HL_DEVICE_TIMEOUT_USEC);
1112
1113         if (err)
1114                 dev_err(hdev->dev,
1115                         "Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1116
1117         WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1118                 1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1119
1120         msleep(GOYA_RESET_WAIT_MSEC);
1121
1122         WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1123                 ~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1124
1125         msleep(GOYA_RESET_WAIT_MSEC);
1126
1127         for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1128                 WREG32(tpc_slm_offset + (slm_index << 2), 0);
1129
1130         val = RREG32(tpc_slm_offset);
1131 }
1132
1133 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1134 {
1135         struct goya_device *goya = hdev->asic_specific;
1136         int i;
1137
1138         if (hdev->pldm)
1139                 return;
1140
1141         if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1142                 return;
1143
1144         /* Workaround for H2 #2443 */
1145
1146         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1147                 _goya_tpc_mbist_workaround(hdev, i);
1148
1149         goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1150 }
1151
1152 /*
1153  * goya_init_golden_registers - Initialize golden registers
1154  *
1155  * @hdev: pointer to hl_device structure
1156  *
1157  * Initialize the H/W registers of the device
1158  *
1159  */
1160 static void goya_init_golden_registers(struct hl_device *hdev)
1161 {
1162         struct goya_device *goya = hdev->asic_specific;
1163         u32 polynom[10], tpc_intr_mask, offset;
1164         int i;
1165
1166         if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1167                 return;
1168
1169         polynom[0] = 0x00020080;
1170         polynom[1] = 0x00401000;
1171         polynom[2] = 0x00200800;
1172         polynom[3] = 0x00002000;
1173         polynom[4] = 0x00080200;
1174         polynom[5] = 0x00040100;
1175         polynom[6] = 0x00100400;
1176         polynom[7] = 0x00004000;
1177         polynom[8] = 0x00010000;
1178         polynom[9] = 0x00008000;
1179
1180         /* Mask all arithmetic interrupts from TPC */
1181         tpc_intr_mask = 0x7FFF;
1182
1183         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1184                 WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1185                 WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1186                 WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1187                 WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1188                 WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1189
1190                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1191                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1192                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1193                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1194                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1195
1196
1197                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1198                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1199                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1200                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1201                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1202
1203                 WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1204                 WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1205                 WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1206                 WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1207                 WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1208
1209                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1210                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1211                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1212                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1213                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1214
1215                 WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1216                 WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1217                 WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1218                 WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1219                 WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1220         }
1221
1222         WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1223         WREG32(mmMME_AGU, 0x0f0f0f10);
1224         WREG32(mmMME_SEI_MASK, ~0x0);
1225
1226         WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1227         WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1228         WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1229         WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1230         WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1231         WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1232         WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1233         WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1234         WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1235         WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1236         WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1237         WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1238         WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1239         WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1240         WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1241         WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1242         WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1243         WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1244         WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1245         WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1246         WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1247         WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1248         WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1249         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1250         WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1251         WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1252         WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1253         WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1254         WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1255         WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1256         WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1257         WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1258         WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1259         WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1260         WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1261         WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1262         WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1263         WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1264         WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1265         WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1266         WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1267         WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1268         WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1269         WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1270         WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1271         WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1272         WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1273         WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1274         WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1275         WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1276         WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1277         WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1278         WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1279         WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1280         WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1281         WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1282         WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1283         WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1284         WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1285         WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1286         WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1287         WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1288         WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1289         WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1290         WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1291         WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1292         WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1293         WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1294         WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1295         WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1296         WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1297         WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1298         WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1299         WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1300         WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1301         WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1302         WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1303         WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1304         WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1305         WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1306         WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1307         WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1308         WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1309         WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1310
1311         WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1312         WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1313         WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1314         WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1315         WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1316         WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1317         WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1318         WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1319         WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1320         WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1321         WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1322         WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1323
1324         WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1325         WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1326         WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1327         WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1328         WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1329         WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1330         WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1331         WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1332         WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1333         WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1334         WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1335         WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1336
1337         WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1338         WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1339         WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1340         WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1341         WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1342         WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1343         WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1344         WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1345         WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1346         WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1347         WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1348         WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1349
1350         WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1351         WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1352         WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1353         WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1354         WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1355         WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1356         WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1357         WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1358         WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1359         WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1360         WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1361         WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1362
1363         WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1364         WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1365         WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1366         WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1367         WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1368         WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1369         WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1370         WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1371         WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1372         WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1373         WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1374         WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1375
1376         WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1377         WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1378         WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1379         WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1380         WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1381         WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1382         WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1383         WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1384         WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1385         WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1386         WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1387         WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1388
1389         for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1390                 WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1391                 WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1392                 WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1393                 WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1394                 WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1395                 WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1396
1397                 WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1398                 WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1399                 WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1400                 WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1401                 WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1402                 WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1403                 WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1404                 WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1405
1406                 WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1407                 WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1408         }
1409
1410         for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1411                 WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1412                                 1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1413                 WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1414                                 1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1415         }
1416
1417         for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1418                 /*
1419                  * Workaround for Bug H2 #2441 :
1420                  * "ST.NOP set trace event illegal opcode"
1421                  */
1422                 WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1423
1424                 WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1425                                 1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1426                 WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1427                                 1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1428         }
1429
1430         WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1431         WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1432                         1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1433
1434         WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1435         WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1436                         1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1437
1438         /*
1439          * Workaround for H2 #HW-23 bug
1440          * Set DMA max outstanding read requests to 240 on DMA CH 1.
1441          * This limitation is still large enough to not affect Gen4 bandwidth.
1442          * We need to only limit that DMA channel because the user can only read
1443          * from Host using DMA CH 1
1444          */
1445         WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1446
1447         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1448
1449         goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1450 }
1451
1452 static void goya_init_mme_qman(struct hl_device *hdev)
1453 {
1454         u32 mtr_base_lo, mtr_base_hi;
1455         u32 so_base_lo, so_base_hi;
1456         u32 gic_base_lo, gic_base_hi;
1457         u64 qman_base_addr;
1458
1459         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1460         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1461         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1462         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1463
1464         gic_base_lo =
1465                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1466         gic_base_hi =
1467                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1468
1469         qman_base_addr = hdev->asic_prop.sram_base_address +
1470                                 MME_QMAN_BASE_OFFSET;
1471
1472         WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1473         WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1474         WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1475         WREG32(mmMME_QM_PQ_PI, 0);
1476         WREG32(mmMME_QM_PQ_CI, 0);
1477         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1478         WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1479         WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1480         WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1481
1482         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1483         WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1484         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1485         WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1486
1487         /* QMAN CQ has 8 cache lines */
1488         WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1489
1490         WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1491         WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1492
1493         WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1494
1495         WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1496
1497         WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1498
1499         WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1500 }
1501
1502 static void goya_init_mme_cmdq(struct hl_device *hdev)
1503 {
1504         u32 mtr_base_lo, mtr_base_hi;
1505         u32 so_base_lo, so_base_hi;
1506         u32 gic_base_lo, gic_base_hi;
1507         u64 qman_base_addr;
1508
1509         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1510         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1511         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1512         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1513
1514         gic_base_lo =
1515                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1516         gic_base_hi =
1517                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1518
1519         qman_base_addr = hdev->asic_prop.sram_base_address +
1520                                 MME_QMAN_BASE_OFFSET;
1521
1522         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1523         WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1524         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1525         WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1526
1527         /* CMDQ CQ has 20 cache lines */
1528         WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1529
1530         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1531         WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1532
1533         WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1534
1535         WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1536
1537         WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1538
1539         WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1540 }
1541
1542 void goya_init_mme_qmans(struct hl_device *hdev)
1543 {
1544         struct goya_device *goya = hdev->asic_specific;
1545         u32 so_base_lo, so_base_hi;
1546
1547         if (goya->hw_cap_initialized & HW_CAP_MME)
1548                 return;
1549
1550         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1551         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1552
1553         WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1554         WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1555
1556         goya_init_mme_qman(hdev);
1557         goya_init_mme_cmdq(hdev);
1558
1559         goya->hw_cap_initialized |= HW_CAP_MME;
1560 }
1561
1562 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1563 {
1564         u32 mtr_base_lo, mtr_base_hi;
1565         u32 so_base_lo, so_base_hi;
1566         u32 gic_base_lo, gic_base_hi;
1567         u64 qman_base_addr;
1568         u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1569
1570         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1571         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1572         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1573         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1574
1575         gic_base_lo =
1576                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1577         gic_base_hi =
1578                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1579
1580         qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1581
1582         WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1583         WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1584         WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1585         WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1586         WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1587         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1588         WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1589         WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1590         WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1591
1592         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1593         WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1594         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1595         WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1596
1597         WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1598
1599         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1600         WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1601
1602         WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1603                         GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1604
1605         WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1606
1607         WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1608
1609         WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1610 }
1611
1612 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1613 {
1614         u32 mtr_base_lo, mtr_base_hi;
1615         u32 so_base_lo, so_base_hi;
1616         u32 gic_base_lo, gic_base_hi;
1617         u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1618
1619         mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1620         mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1621         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1622         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1623
1624         gic_base_lo =
1625                 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1626         gic_base_hi =
1627                 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1628
1629         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1630         WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1631         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1632         WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1633
1634         WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
1635
1636         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1637         WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1638
1639         WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
1640                         GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
1641
1642         WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
1643
1644         WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
1645
1646         WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
1647 }
1648
1649 void goya_init_tpc_qmans(struct hl_device *hdev)
1650 {
1651         struct goya_device *goya = hdev->asic_specific;
1652         u32 so_base_lo, so_base_hi;
1653         u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
1654                         mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
1655         int i;
1656
1657         if (goya->hw_cap_initialized & HW_CAP_TPC)
1658                 return;
1659
1660         so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1661         so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1662
1663         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
1664                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
1665                                 so_base_lo);
1666                 WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
1667                                 so_base_hi);
1668         }
1669
1670         goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
1671         goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
1672         goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
1673         goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
1674         goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
1675         goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
1676         goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
1677         goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
1678
1679         for (i = 0 ; i < TPC_MAX_NUM ; i++)
1680                 goya_init_tpc_cmdq(hdev, i);
1681
1682         goya->hw_cap_initialized |= HW_CAP_TPC;
1683 }
1684
1685 /*
1686  * goya_disable_internal_queues - Disable internal queues
1687  *
1688  * @hdev: pointer to hl_device structure
1689  *
1690  */
1691 static void goya_disable_internal_queues(struct hl_device *hdev)
1692 {
1693         WREG32(mmMME_QM_GLBL_CFG0, 0);
1694         WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
1695
1696         WREG32(mmTPC0_QM_GLBL_CFG0, 0);
1697         WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
1698
1699         WREG32(mmTPC1_QM_GLBL_CFG0, 0);
1700         WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
1701
1702         WREG32(mmTPC2_QM_GLBL_CFG0, 0);
1703         WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
1704
1705         WREG32(mmTPC3_QM_GLBL_CFG0, 0);
1706         WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
1707
1708         WREG32(mmTPC4_QM_GLBL_CFG0, 0);
1709         WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
1710
1711         WREG32(mmTPC5_QM_GLBL_CFG0, 0);
1712         WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
1713
1714         WREG32(mmTPC6_QM_GLBL_CFG0, 0);
1715         WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
1716
1717         WREG32(mmTPC7_QM_GLBL_CFG0, 0);
1718         WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
1719 }
1720
1721 /*
1722  * goya_stop_internal_queues - Stop internal queues
1723  *
1724  * @hdev: pointer to hl_device structure
1725  *
1726  * Returns 0 on success
1727  *
1728  */
1729 static int goya_stop_internal_queues(struct hl_device *hdev)
1730 {
1731         int rc, retval = 0;
1732
1733         /*
1734          * Each queue (QMAN) is a separate H/W logic. That means that each
1735          * QMAN can be stopped independently and failure to stop one does NOT
1736          * mandate we should not try to stop other QMANs
1737          */
1738
1739         rc = goya_stop_queue(hdev,
1740                         mmMME_QM_GLBL_CFG1,
1741                         mmMME_QM_CP_STS,
1742                         mmMME_QM_GLBL_STS0);
1743
1744         if (rc) {
1745                 dev_err(hdev->dev, "failed to stop MME QMAN\n");
1746                 retval = -EIO;
1747         }
1748
1749         rc = goya_stop_queue(hdev,
1750                         mmMME_CMDQ_GLBL_CFG1,
1751                         mmMME_CMDQ_CP_STS,
1752                         mmMME_CMDQ_GLBL_STS0);
1753
1754         if (rc) {
1755                 dev_err(hdev->dev, "failed to stop MME CMDQ\n");
1756                 retval = -EIO;
1757         }
1758
1759         rc = goya_stop_queue(hdev,
1760                         mmTPC0_QM_GLBL_CFG1,
1761                         mmTPC0_QM_CP_STS,
1762                         mmTPC0_QM_GLBL_STS0);
1763
1764         if (rc) {
1765                 dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
1766                 retval = -EIO;
1767         }
1768
1769         rc = goya_stop_queue(hdev,
1770                         mmTPC0_CMDQ_GLBL_CFG1,
1771                         mmTPC0_CMDQ_CP_STS,
1772                         mmTPC0_CMDQ_GLBL_STS0);
1773
1774         if (rc) {
1775                 dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
1776                 retval = -EIO;
1777         }
1778
1779         rc = goya_stop_queue(hdev,
1780                         mmTPC1_QM_GLBL_CFG1,
1781                         mmTPC1_QM_CP_STS,
1782                         mmTPC1_QM_GLBL_STS0);
1783
1784         if (rc) {
1785                 dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
1786                 retval = -EIO;
1787         }
1788
1789         rc = goya_stop_queue(hdev,
1790                         mmTPC1_CMDQ_GLBL_CFG1,
1791                         mmTPC1_CMDQ_CP_STS,
1792                         mmTPC1_CMDQ_GLBL_STS0);
1793
1794         if (rc) {
1795                 dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
1796                 retval = -EIO;
1797         }
1798
1799         rc = goya_stop_queue(hdev,
1800                         mmTPC2_QM_GLBL_CFG1,
1801                         mmTPC2_QM_CP_STS,
1802                         mmTPC2_QM_GLBL_STS0);
1803
1804         if (rc) {
1805                 dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
1806                 retval = -EIO;
1807         }
1808
1809         rc = goya_stop_queue(hdev,
1810                         mmTPC2_CMDQ_GLBL_CFG1,
1811                         mmTPC2_CMDQ_CP_STS,
1812                         mmTPC2_CMDQ_GLBL_STS0);
1813
1814         if (rc) {
1815                 dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
1816                 retval = -EIO;
1817         }
1818
1819         rc = goya_stop_queue(hdev,
1820                         mmTPC3_QM_GLBL_CFG1,
1821                         mmTPC3_QM_CP_STS,
1822                         mmTPC3_QM_GLBL_STS0);
1823
1824         if (rc) {
1825                 dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
1826                 retval = -EIO;
1827         }
1828
1829         rc = goya_stop_queue(hdev,
1830                         mmTPC3_CMDQ_GLBL_CFG1,
1831                         mmTPC3_CMDQ_CP_STS,
1832                         mmTPC3_CMDQ_GLBL_STS0);
1833
1834         if (rc) {
1835                 dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
1836                 retval = -EIO;
1837         }
1838
1839         rc = goya_stop_queue(hdev,
1840                         mmTPC4_QM_GLBL_CFG1,
1841                         mmTPC4_QM_CP_STS,
1842                         mmTPC4_QM_GLBL_STS0);
1843
1844         if (rc) {
1845                 dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
1846                 retval = -EIO;
1847         }
1848
1849         rc = goya_stop_queue(hdev,
1850                         mmTPC4_CMDQ_GLBL_CFG1,
1851                         mmTPC4_CMDQ_CP_STS,
1852                         mmTPC4_CMDQ_GLBL_STS0);
1853
1854         if (rc) {
1855                 dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
1856                 retval = -EIO;
1857         }
1858
1859         rc = goya_stop_queue(hdev,
1860                         mmTPC5_QM_GLBL_CFG1,
1861                         mmTPC5_QM_CP_STS,
1862                         mmTPC5_QM_GLBL_STS0);
1863
1864         if (rc) {
1865                 dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
1866                 retval = -EIO;
1867         }
1868
1869         rc = goya_stop_queue(hdev,
1870                         mmTPC5_CMDQ_GLBL_CFG1,
1871                         mmTPC5_CMDQ_CP_STS,
1872                         mmTPC5_CMDQ_GLBL_STS0);
1873
1874         if (rc) {
1875                 dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
1876                 retval = -EIO;
1877         }
1878
1879         rc = goya_stop_queue(hdev,
1880                         mmTPC6_QM_GLBL_CFG1,
1881                         mmTPC6_QM_CP_STS,
1882                         mmTPC6_QM_GLBL_STS0);
1883
1884         if (rc) {
1885                 dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
1886                 retval = -EIO;
1887         }
1888
1889         rc = goya_stop_queue(hdev,
1890                         mmTPC6_CMDQ_GLBL_CFG1,
1891                         mmTPC6_CMDQ_CP_STS,
1892                         mmTPC6_CMDQ_GLBL_STS0);
1893
1894         if (rc) {
1895                 dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
1896                 retval = -EIO;
1897         }
1898
1899         rc = goya_stop_queue(hdev,
1900                         mmTPC7_QM_GLBL_CFG1,
1901                         mmTPC7_QM_CP_STS,
1902                         mmTPC7_QM_GLBL_STS0);
1903
1904         if (rc) {
1905                 dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
1906                 retval = -EIO;
1907         }
1908
1909         rc = goya_stop_queue(hdev,
1910                         mmTPC7_CMDQ_GLBL_CFG1,
1911                         mmTPC7_CMDQ_CP_STS,
1912                         mmTPC7_CMDQ_GLBL_STS0);
1913
1914         if (rc) {
1915                 dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
1916                 retval = -EIO;
1917         }
1918
1919         return retval;
1920 }
1921
1922 static void goya_dma_stall(struct hl_device *hdev)
1923 {
1924         WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
1925         WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
1926         WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
1927         WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
1928         WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
1929 }
1930
1931 static void goya_tpc_stall(struct hl_device *hdev)
1932 {
1933         WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
1934         WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
1935         WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
1936         WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
1937         WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
1938         WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
1939         WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
1940         WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
1941 }
1942
1943 static void goya_mme_stall(struct hl_device *hdev)
1944 {
1945         WREG32(mmMME_STALL, 0xFFFFFFFF);
1946 }
1947
1948 static int goya_enable_msix(struct hl_device *hdev)
1949 {
1950         struct goya_device *goya = hdev->asic_specific;
1951         int cq_cnt = hdev->asic_prop.completion_queues_count;
1952         int rc, i, irq_cnt_init, irq;
1953
1954         if (goya->hw_cap_initialized & HW_CAP_MSIX)
1955                 return 0;
1956
1957         rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
1958                                 GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
1959         if (rc < 0) {
1960                 dev_err(hdev->dev,
1961                         "MSI-X: Failed to enable support -- %d/%d\n",
1962                         GOYA_MSIX_ENTRIES, rc);
1963                 return rc;
1964         }
1965
1966         for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
1967                 irq = pci_irq_vector(hdev->pdev, i);
1968                 rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
1969                                 &hdev->completion_queue[i]);
1970                 if (rc) {
1971                         dev_err(hdev->dev, "Failed to request IRQ %d", irq);
1972                         goto free_irqs;
1973                 }
1974         }
1975
1976         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
1977
1978         rc = request_irq(irq, hl_irq_handler_eq, 0,
1979                         goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
1980                         &hdev->event_queue);
1981         if (rc) {
1982                 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
1983                 goto free_irqs;
1984         }
1985
1986         goya->hw_cap_initialized |= HW_CAP_MSIX;
1987         return 0;
1988
1989 free_irqs:
1990         for (i = 0 ; i < irq_cnt_init ; i++)
1991                 free_irq(pci_irq_vector(hdev->pdev, i),
1992                         &hdev->completion_queue[i]);
1993
1994         pci_free_irq_vectors(hdev->pdev);
1995         return rc;
1996 }
1997
1998 static void goya_sync_irqs(struct hl_device *hdev)
1999 {
2000         struct goya_device *goya = hdev->asic_specific;
2001         int i;
2002
2003         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2004                 return;
2005
2006         /* Wait for all pending IRQs to be finished */
2007         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2008                 synchronize_irq(pci_irq_vector(hdev->pdev, i));
2009
2010         synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2011 }
2012
2013 static void goya_disable_msix(struct hl_device *hdev)
2014 {
2015         struct goya_device *goya = hdev->asic_specific;
2016         int i, irq;
2017
2018         if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2019                 return;
2020
2021         goya_sync_irqs(hdev);
2022
2023         irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2024         free_irq(irq, &hdev->event_queue);
2025
2026         for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2027                 irq = pci_irq_vector(hdev->pdev, i);
2028                 free_irq(irq, &hdev->completion_queue[i]);
2029         }
2030
2031         pci_free_irq_vectors(hdev->pdev);
2032
2033         goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2034 }
2035
2036 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset)
2037 {
2038         u32 wait_timeout_ms, cpu_timeout_ms;
2039
2040         dev_info(hdev->dev,
2041                 "Halting compute engines and disabling interrupts\n");
2042
2043         if (hdev->pldm) {
2044                 wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2045                 cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2046         } else {
2047                 wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2048                 cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2049         }
2050
2051         if (hard_reset) {
2052                 /*
2053                  * I don't know what is the state of the CPU so make sure it is
2054                  * stopped in any means necessary
2055                  */
2056                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2057                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2058                         GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2059                 msleep(cpu_timeout_ms);
2060         }
2061
2062         goya_stop_external_queues(hdev);
2063         goya_stop_internal_queues(hdev);
2064
2065         msleep(wait_timeout_ms);
2066
2067         goya_dma_stall(hdev);
2068         goya_tpc_stall(hdev);
2069         goya_mme_stall(hdev);
2070
2071         msleep(wait_timeout_ms);
2072
2073         goya_disable_external_queues(hdev);
2074         goya_disable_internal_queues(hdev);
2075
2076         if (hard_reset)
2077                 goya_disable_msix(hdev);
2078         else
2079                 goya_sync_irqs(hdev);
2080 }
2081
2082 /*
2083  * goya_push_uboot_to_device() - Push u-boot FW code to device.
2084  * @hdev: Pointer to hl_device structure.
2085  *
2086  * Copy u-boot fw code from firmware file to SRAM BAR.
2087  *
2088  * Return: 0 on success, non-zero for failure.
2089  */
2090 static int goya_push_uboot_to_device(struct hl_device *hdev)
2091 {
2092         char fw_name[200];
2093         void __iomem *dst;
2094
2095         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-u-boot.bin");
2096         dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + UBOOT_FW_OFFSET;
2097
2098         return hl_fw_push_fw_to_device(hdev, fw_name, dst);
2099 }
2100
2101 /*
2102  * goya_push_linux_to_device() - Push LINUX FW code to device.
2103  * @hdev: Pointer to hl_device structure.
2104  *
2105  * Copy LINUX fw code from firmware file to HBM BAR.
2106  *
2107  * Return: 0 on success, non-zero for failure.
2108  */
2109 static int goya_push_linux_to_device(struct hl_device *hdev)
2110 {
2111         char fw_name[200];
2112         void __iomem *dst;
2113
2114         snprintf(fw_name, sizeof(fw_name), "habanalabs/goya/goya-fit.itb");
2115         dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2116
2117         return hl_fw_push_fw_to_device(hdev, fw_name, dst);
2118 }
2119
2120 static int goya_pldm_init_cpu(struct hl_device *hdev)
2121 {
2122         u32 val, unit_rst_val;
2123         int rc;
2124
2125         /* Must initialize SRAM scrambler before pushing u-boot to SRAM */
2126         goya_init_golden_registers(hdev);
2127
2128         /* Put ARM cores into reset */
2129         WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT);
2130         val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
2131
2132         /* Reset the CA53 MACRO */
2133         unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2134         WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET);
2135         val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2136         WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val);
2137         val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N);
2138
2139         rc = goya_push_uboot_to_device(hdev);
2140         if (rc)
2141                 return rc;
2142
2143         rc = goya_push_linux_to_device(hdev);
2144         if (rc)
2145                 return rc;
2146
2147         WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
2148         WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA);
2149
2150         WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0,
2151                 lower_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
2152         WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0,
2153                 upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET));
2154
2155         /* Release ARM core 0 from reset */
2156         WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL,
2157                                         CPU_RESET_CORE0_DEASSERT);
2158         val = RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL);
2159
2160         return 0;
2161 }
2162
2163 /*
2164  * FW component passes an offset from SRAM_BASE_ADDR in SCRATCHPAD_xx.
2165  * The version string should be located by that offset.
2166  */
2167 static void goya_read_device_fw_version(struct hl_device *hdev,
2168                                         enum goya_fw_component fwc)
2169 {
2170         const char *name;
2171         u32 ver_off;
2172         char *dest;
2173
2174         switch (fwc) {
2175         case FW_COMP_UBOOT:
2176                 ver_off = RREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_29);
2177                 dest = hdev->asic_prop.uboot_ver;
2178                 name = "U-Boot";
2179                 break;
2180         case FW_COMP_PREBOOT:
2181                 ver_off = RREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_28);
2182                 dest = hdev->asic_prop.preboot_ver;
2183                 name = "Preboot";
2184                 break;
2185         default:
2186                 dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc);
2187                 return;
2188         }
2189
2190         ver_off &= ~((u32)SRAM_BASE_ADDR);
2191
2192         if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) {
2193                 memcpy_fromio(dest, hdev->pcie_bar[SRAM_CFG_BAR_ID] + ver_off,
2194                                                         VERSION_MAX_LEN);
2195         } else {
2196                 dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n",
2197                                                                 name, ver_off);
2198                 strcpy(dest, "unavailable");
2199         }
2200 }
2201
2202 static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout)
2203 {
2204         struct goya_device *goya = hdev->asic_specific;
2205         u32 status;
2206         int rc;
2207
2208         if (!hdev->cpu_enable)
2209                 return 0;
2210
2211         if (goya->hw_cap_initialized & HW_CAP_CPU)
2212                 return 0;
2213
2214         /*
2215          * Before pushing u-boot/linux to device, need to set the ddr bar to
2216          * base address of dram
2217          */
2218         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2219         if (rc) {
2220                 dev_err(hdev->dev,
2221                         "failed to map DDR bar to DRAM base address\n");
2222                 return rc;
2223         }
2224
2225         if (hdev->pldm) {
2226                 rc = goya_pldm_init_cpu(hdev);
2227                 if (rc)
2228                         return rc;
2229
2230                 goto out;
2231         }
2232
2233         /* Make sure CPU boot-loader is running */
2234         rc = hl_poll_timeout(
2235                 hdev,
2236                 mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2237                 status,
2238                 (status == CPU_BOOT_STATUS_DRAM_RDY) ||
2239                 (status == CPU_BOOT_STATUS_SRAM_AVAIL),
2240                 10000,
2241                 cpu_timeout);
2242
2243         if (rc) {
2244                 dev_err(hdev->dev, "Error in ARM u-boot!");
2245                 switch (status) {
2246                 case CPU_BOOT_STATUS_NA:
2247                         dev_err(hdev->dev,
2248                                 "ARM status %d - BTL did NOT run\n", status);
2249                         break;
2250                 case CPU_BOOT_STATUS_IN_WFE:
2251                         dev_err(hdev->dev,
2252                                 "ARM status %d - Inside WFE loop\n", status);
2253                         break;
2254                 case CPU_BOOT_STATUS_IN_BTL:
2255                         dev_err(hdev->dev,
2256                                 "ARM status %d - Stuck in BTL\n", status);
2257                         break;
2258                 case CPU_BOOT_STATUS_IN_PREBOOT:
2259                         dev_err(hdev->dev,
2260                                 "ARM status %d - Stuck in Preboot\n", status);
2261                         break;
2262                 case CPU_BOOT_STATUS_IN_SPL:
2263                         dev_err(hdev->dev,
2264                                 "ARM status %d - Stuck in SPL\n", status);
2265                         break;
2266                 case CPU_BOOT_STATUS_IN_UBOOT:
2267                         dev_err(hdev->dev,
2268                                 "ARM status %d - Stuck in u-boot\n", status);
2269                         break;
2270                 case CPU_BOOT_STATUS_DRAM_INIT_FAIL:
2271                         dev_err(hdev->dev,
2272                                 "ARM status %d - DDR initialization failed\n",
2273                                 status);
2274                         break;
2275                 case CPU_BOOT_STATUS_UBOOT_NOT_READY:
2276                         dev_err(hdev->dev,
2277                                 "ARM status %d - u-boot stopped by user\n",
2278                                 status);
2279                         break;
2280                 default:
2281                         dev_err(hdev->dev,
2282                                 "ARM status %d - Invalid status code\n",
2283                                 status);
2284                         break;
2285                 }
2286                 return -EIO;
2287         }
2288
2289         /* Read U-Boot version now in case we will later fail */
2290         goya_read_device_fw_version(hdev, FW_COMP_UBOOT);
2291         goya_read_device_fw_version(hdev, FW_COMP_PREBOOT);
2292
2293         if (status == CPU_BOOT_STATUS_SRAM_AVAIL)
2294                 goto out;
2295
2296         if (!hdev->fw_loading) {
2297                 dev_info(hdev->dev, "Skip loading FW\n");
2298                 goto out;
2299         }
2300
2301         rc = goya_push_linux_to_device(hdev);
2302         if (rc)
2303                 return rc;
2304
2305         WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY);
2306
2307         rc = hl_poll_timeout(
2308                 hdev,
2309                 mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2310                 status,
2311                 (status == CPU_BOOT_STATUS_SRAM_AVAIL),
2312                 10000,
2313                 cpu_timeout);
2314
2315         if (rc) {
2316                 if (status == CPU_BOOT_STATUS_FIT_CORRUPTED)
2317                         dev_err(hdev->dev,
2318                                 "ARM u-boot reports FIT image is corrupted\n");
2319                 else
2320                         dev_err(hdev->dev,
2321                                 "ARM Linux failed to load, %d\n", status);
2322                 WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA);
2323                 return -EIO;
2324         }
2325
2326         dev_info(hdev->dev, "Successfully loaded firmware to device\n");
2327
2328 out:
2329         goya->hw_cap_initialized |= HW_CAP_CPU;
2330
2331         return 0;
2332 }
2333
2334 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2335                                                 u64 phys_addr)
2336 {
2337         u32 status, timeout_usec;
2338         int rc;
2339
2340         if (hdev->pldm)
2341                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2342         else
2343                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2344
2345         WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2346         WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2347         WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2348
2349         rc = hl_poll_timeout(
2350                 hdev,
2351                 MMU_ASID_BUSY,
2352                 status,
2353                 !(status & 0x80000000),
2354                 1000,
2355                 timeout_usec);
2356
2357         if (rc) {
2358                 dev_err(hdev->dev,
2359                         "Timeout during MMU hop0 config of asid %d\n", asid);
2360                 return rc;
2361         }
2362
2363         return 0;
2364 }
2365
2366 int goya_mmu_init(struct hl_device *hdev)
2367 {
2368         struct asic_fixed_properties *prop = &hdev->asic_prop;
2369         struct goya_device *goya = hdev->asic_specific;
2370         u64 hop0_addr;
2371         int rc, i;
2372
2373         if (!hdev->mmu_enable)
2374                 return 0;
2375
2376         if (goya->hw_cap_initialized & HW_CAP_MMU)
2377                 return 0;
2378
2379         hdev->dram_supports_virtual_memory = true;
2380         hdev->dram_default_page_mapping = true;
2381
2382         for (i = 0 ; i < prop->max_asid ; i++) {
2383                 hop0_addr = prop->mmu_pgt_addr +
2384                                 (i * prop->mmu_hop_table_size);
2385
2386                 rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2387                 if (rc) {
2388                         dev_err(hdev->dev,
2389                                 "failed to set hop0 addr for asid %d\n", i);
2390                         goto err;
2391                 }
2392         }
2393
2394         goya->hw_cap_initialized |= HW_CAP_MMU;
2395
2396         /* init MMU cache manage page */
2397         WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2398                                 lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2399         WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2400
2401         /* Remove follower feature due to performance bug */
2402         WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2403                         (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2404
2405         hdev->asic_funcs->mmu_invalidate_cache(hdev, true);
2406
2407         WREG32(mmMMU_MMU_ENABLE, 1);
2408         WREG32(mmMMU_SPI_MASK, 0xF);
2409
2410         return 0;
2411
2412 err:
2413         return rc;
2414 }
2415
2416 /*
2417  * goya_hw_init - Goya hardware initialization code
2418  *
2419  * @hdev: pointer to hl_device structure
2420  *
2421  * Returns 0 on success
2422  *
2423  */
2424 static int goya_hw_init(struct hl_device *hdev)
2425 {
2426         struct asic_fixed_properties *prop = &hdev->asic_prop;
2427         u32 val;
2428         int rc;
2429
2430         dev_info(hdev->dev, "Starting initialization of H/W\n");
2431
2432         /* Perform read from the device to make sure device is up */
2433         val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2434
2435         /*
2436          * Let's mark in the H/W that we have reached this point. We check
2437          * this value in the reset_before_init function to understand whether
2438          * we need to reset the chip before doing H/W init. This register is
2439          * cleared by the H/W upon H/W reset
2440          */
2441         WREG32(mmPSOC_GLOBAL_CONF_APP_STATUS, HL_DEVICE_HW_STATE_DIRTY);
2442
2443         rc = goya_init_cpu(hdev, GOYA_CPU_TIMEOUT_USEC);
2444         if (rc) {
2445                 dev_err(hdev->dev, "failed to initialize CPU\n");
2446                 return rc;
2447         }
2448
2449         goya_tpc_mbist_workaround(hdev);
2450
2451         goya_init_golden_registers(hdev);
2452
2453         /*
2454          * After CPU initialization is finished, change DDR bar mapping inside
2455          * iATU to point to the start address of the MMU page tables
2456          */
2457         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
2458                 (MMU_PAGE_TABLES_ADDR & ~(prop->dram_pci_bar_size - 0x1ull)));
2459         if (rc) {
2460                 dev_err(hdev->dev,
2461                         "failed to map DDR bar to MMU page tables\n");
2462                 return rc;
2463         }
2464
2465         rc = goya_mmu_init(hdev);
2466         if (rc)
2467                 return rc;
2468
2469         goya_init_security(hdev);
2470
2471         goya_init_dma_qmans(hdev);
2472
2473         goya_init_mme_qmans(hdev);
2474
2475         goya_init_tpc_qmans(hdev);
2476
2477         /* MSI-X must be enabled before CPU queues are initialized */
2478         rc = goya_enable_msix(hdev);
2479         if (rc)
2480                 goto disable_queues;
2481
2482         rc = goya_init_cpu_queues(hdev);
2483         if (rc) {
2484                 dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n",
2485                         rc);
2486                 goto disable_msix;
2487         }
2488
2489         /*
2490          * Check if we managed to set the DMA mask to more then 32 bits. If so,
2491          * let's try to increase it again because in Goya we set the initial
2492          * dma mask to less then 39 bits so that the allocation of the memory
2493          * area for the device's cpu will be under 39 bits
2494          */
2495         if (hdev->dma_mask > 32) {
2496                 rc = hl_pci_set_dma_mask(hdev, 48);
2497                 if (rc)
2498                         goto disable_pci_access;
2499         }
2500
2501         /* Perform read from the device to flush all MSI-X configuration */
2502         val = RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2503
2504         return 0;
2505
2506 disable_pci_access:
2507         hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
2508 disable_msix:
2509         goya_disable_msix(hdev);
2510 disable_queues:
2511         goya_disable_internal_queues(hdev);
2512         goya_disable_external_queues(hdev);
2513
2514         return rc;
2515 }
2516
2517 /*
2518  * goya_hw_fini - Goya hardware tear-down code
2519  *
2520  * @hdev: pointer to hl_device structure
2521  * @hard_reset: should we do hard reset to all engines or just reset the
2522  *              compute/dma engines
2523  */
2524 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset)
2525 {
2526         struct goya_device *goya = hdev->asic_specific;
2527         u32 reset_timeout_ms, status;
2528
2529         if (hdev->pldm)
2530                 reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2531         else
2532                 reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2533
2534         if (hard_reset) {
2535                 goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2536                 goya_disable_clk_rlx(hdev);
2537                 goya_set_pll_refclk(hdev);
2538
2539                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2540                 dev_info(hdev->dev,
2541                         "Issued HARD reset command, going to wait %dms\n",
2542                         reset_timeout_ms);
2543         } else {
2544                 WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2545                 dev_info(hdev->dev,
2546                         "Issued SOFT reset command, going to wait %dms\n",
2547                         reset_timeout_ms);
2548         }
2549
2550         /*
2551          * After hard reset, we can't poll the BTM_FSM register because the PSOC
2552          * itself is in reset. In either reset we need to wait until the reset
2553          * is deasserted
2554          */
2555         msleep(reset_timeout_ms);
2556
2557         status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2558         if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2559                 dev_err(hdev->dev,
2560                         "Timeout while waiting for device to reset 0x%x\n",
2561                         status);
2562
2563         if (!hard_reset) {
2564                 goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2565                                                 HW_CAP_GOLDEN | HW_CAP_TPC);
2566                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2567                                 GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2568                 return;
2569         }
2570
2571         /* Chicken bit to re-initiate boot sequencer flow */
2572         WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2573                 1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2574         /* Move boot manager FSM to pre boot sequencer init state */
2575         WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2576                         0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2577
2578         goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2579                                         HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2580                                         HW_CAP_DMA | HW_CAP_MME |
2581                                         HW_CAP_MMU | HW_CAP_TPC_MBIST |
2582                                         HW_CAP_GOLDEN | HW_CAP_TPC);
2583         memset(goya->events_stat, 0, sizeof(goya->events_stat));
2584
2585         if (!hdev->pldm) {
2586                 int rc;
2587                 /* In case we are running inside VM and the VM is
2588                  * shutting down, we need to make sure CPU boot-loader
2589                  * is running before we can continue the VM shutdown.
2590                  * That is because the VM will send an FLR signal that
2591                  * we must answer
2592                  */
2593                 dev_info(hdev->dev,
2594                         "Going to wait up to %ds for CPU boot loader\n",
2595                         GOYA_CPU_TIMEOUT_USEC / 1000 / 1000);
2596
2597                 rc = hl_poll_timeout(
2598                         hdev,
2599                         mmPSOC_GLOBAL_CONF_WARM_REBOOT,
2600                         status,
2601                         (status == CPU_BOOT_STATUS_DRAM_RDY),
2602                         10000,
2603                         GOYA_CPU_TIMEOUT_USEC);
2604                 if (rc)
2605                         dev_err(hdev->dev,
2606                                 "failed to wait for CPU boot loader\n");
2607         }
2608 }
2609
2610 int goya_suspend(struct hl_device *hdev)
2611 {
2612         int rc;
2613
2614         rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS);
2615         if (rc)
2616                 dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2617
2618         return rc;
2619 }
2620
2621 int goya_resume(struct hl_device *hdev)
2622 {
2623         return goya_init_iatu(hdev);
2624 }
2625
2626 static int goya_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2627                 u64 kaddress, phys_addr_t paddress, u32 size)
2628 {
2629         int rc;
2630
2631         vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2632                         VM_DONTCOPY | VM_NORESERVE;
2633
2634         rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT,
2635                                 size, vma->vm_page_prot);
2636         if (rc)
2637                 dev_err(hdev->dev, "remap_pfn_range error %d", rc);
2638
2639         return rc;
2640 }
2641
2642 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2643 {
2644         u32 db_reg_offset, db_value;
2645         bool invalid_queue = false;
2646
2647         switch (hw_queue_id) {
2648         case GOYA_QUEUE_ID_DMA_0:
2649                 db_reg_offset = mmDMA_QM_0_PQ_PI;
2650                 break;
2651
2652         case GOYA_QUEUE_ID_DMA_1:
2653                 db_reg_offset = mmDMA_QM_1_PQ_PI;
2654                 break;
2655
2656         case GOYA_QUEUE_ID_DMA_2:
2657                 db_reg_offset = mmDMA_QM_2_PQ_PI;
2658                 break;
2659
2660         case GOYA_QUEUE_ID_DMA_3:
2661                 db_reg_offset = mmDMA_QM_3_PQ_PI;
2662                 break;
2663
2664         case GOYA_QUEUE_ID_DMA_4:
2665                 db_reg_offset = mmDMA_QM_4_PQ_PI;
2666                 break;
2667
2668         case GOYA_QUEUE_ID_CPU_PQ:
2669                 if (hdev->cpu_queues_enable)
2670                         db_reg_offset = mmCPU_IF_PF_PQ_PI;
2671                 else
2672                         invalid_queue = true;
2673                 break;
2674
2675         case GOYA_QUEUE_ID_MME:
2676                 db_reg_offset = mmMME_QM_PQ_PI;
2677                 break;
2678
2679         case GOYA_QUEUE_ID_TPC0:
2680                 db_reg_offset = mmTPC0_QM_PQ_PI;
2681                 break;
2682
2683         case GOYA_QUEUE_ID_TPC1:
2684                 db_reg_offset = mmTPC1_QM_PQ_PI;
2685                 break;
2686
2687         case GOYA_QUEUE_ID_TPC2:
2688                 db_reg_offset = mmTPC2_QM_PQ_PI;
2689                 break;
2690
2691         case GOYA_QUEUE_ID_TPC3:
2692                 db_reg_offset = mmTPC3_QM_PQ_PI;
2693                 break;
2694
2695         case GOYA_QUEUE_ID_TPC4:
2696                 db_reg_offset = mmTPC4_QM_PQ_PI;
2697                 break;
2698
2699         case GOYA_QUEUE_ID_TPC5:
2700                 db_reg_offset = mmTPC5_QM_PQ_PI;
2701                 break;
2702
2703         case GOYA_QUEUE_ID_TPC6:
2704                 db_reg_offset = mmTPC6_QM_PQ_PI;
2705                 break;
2706
2707         case GOYA_QUEUE_ID_TPC7:
2708                 db_reg_offset = mmTPC7_QM_PQ_PI;
2709                 break;
2710
2711         default:
2712                 invalid_queue = true;
2713         }
2714
2715         if (invalid_queue) {
2716                 /* Should never get here */
2717                 dev_err(hdev->dev, "h/w queue %d is invalid. Can't set pi\n",
2718                         hw_queue_id);
2719                 return;
2720         }
2721
2722         db_value = pi;
2723
2724         /* ring the doorbell */
2725         WREG32(db_reg_offset, db_value);
2726
2727         if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ)
2728                 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2729                                 GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2730 }
2731
2732 void goya_flush_pq_write(struct hl_device *hdev, u64 *pq, u64 exp_val)
2733 {
2734         /* Not needed in Goya */
2735 }
2736
2737 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2738                                         dma_addr_t *dma_handle, gfp_t flags)
2739 {
2740         return dma_alloc_coherent(&hdev->pdev->dev, size, dma_handle, flags);
2741 }
2742
2743 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2744                                         void *cpu_addr, dma_addr_t dma_handle)
2745 {
2746         dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, dma_handle);
2747 }
2748
2749 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
2750                                 dma_addr_t *dma_handle, u16 *queue_len)
2751 {
2752         void *base;
2753         u32 offset;
2754
2755         *dma_handle = hdev->asic_prop.sram_base_address;
2756
2757         base = (void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
2758
2759         switch (queue_id) {
2760         case GOYA_QUEUE_ID_MME:
2761                 offset = MME_QMAN_BASE_OFFSET;
2762                 *queue_len = MME_QMAN_LENGTH;
2763                 break;
2764         case GOYA_QUEUE_ID_TPC0:
2765                 offset = TPC0_QMAN_BASE_OFFSET;
2766                 *queue_len = TPC_QMAN_LENGTH;
2767                 break;
2768         case GOYA_QUEUE_ID_TPC1:
2769                 offset = TPC1_QMAN_BASE_OFFSET;
2770                 *queue_len = TPC_QMAN_LENGTH;
2771                 break;
2772         case GOYA_QUEUE_ID_TPC2:
2773                 offset = TPC2_QMAN_BASE_OFFSET;
2774                 *queue_len = TPC_QMAN_LENGTH;
2775                 break;
2776         case GOYA_QUEUE_ID_TPC3:
2777                 offset = TPC3_QMAN_BASE_OFFSET;
2778                 *queue_len = TPC_QMAN_LENGTH;
2779                 break;
2780         case GOYA_QUEUE_ID_TPC4:
2781                 offset = TPC4_QMAN_BASE_OFFSET;
2782                 *queue_len = TPC_QMAN_LENGTH;
2783                 break;
2784         case GOYA_QUEUE_ID_TPC5:
2785                 offset = TPC5_QMAN_BASE_OFFSET;
2786                 *queue_len = TPC_QMAN_LENGTH;
2787                 break;
2788         case GOYA_QUEUE_ID_TPC6:
2789                 offset = TPC6_QMAN_BASE_OFFSET;
2790                 *queue_len = TPC_QMAN_LENGTH;
2791                 break;
2792         case GOYA_QUEUE_ID_TPC7:
2793                 offset = TPC7_QMAN_BASE_OFFSET;
2794                 *queue_len = TPC_QMAN_LENGTH;
2795                 break;
2796         default:
2797                 dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
2798                 return NULL;
2799         }
2800
2801         base += offset;
2802         *dma_handle += offset;
2803
2804         return base;
2805 }
2806
2807 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
2808 {
2809         struct packet_msg_prot *fence_pkt;
2810         u32 *fence_ptr;
2811         dma_addr_t fence_dma_addr;
2812         struct hl_cb *cb;
2813         u32 tmp, timeout;
2814         char buf[16] = {};
2815         int rc;
2816
2817         if (hdev->pldm)
2818                 timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
2819         else
2820                 timeout = HL_DEVICE_TIMEOUT_USEC;
2821
2822         if (!hdev->asic_funcs->is_device_idle(hdev, buf, sizeof(buf))) {
2823                 dev_err_ratelimited(hdev->dev,
2824                         "Can't send KMD job on QMAN0 because %s is busy\n",
2825                         buf);
2826                 return -EBUSY;
2827         }
2828
2829         fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL,
2830                                                         &fence_dma_addr);
2831         if (!fence_ptr) {
2832                 dev_err(hdev->dev,
2833                         "Failed to allocate fence memory for QMAN0\n");
2834                 return -ENOMEM;
2835         }
2836
2837         *fence_ptr = 0;
2838
2839         goya_qman0_set_security(hdev, true);
2840
2841         /*
2842          * goya cs parser saves space for 2xpacket_msg_prot at end of CB. For
2843          * synchronized kernel jobs we only need space for 1 packet_msg_prot
2844          */
2845         job->job_cb_size -= sizeof(struct packet_msg_prot);
2846
2847         cb = job->patched_cb;
2848
2849         fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address +
2850                         job->job_cb_size - sizeof(struct packet_msg_prot));
2851
2852         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
2853                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
2854                         (1 << GOYA_PKT_CTL_MB_SHIFT);
2855         fence_pkt->ctl = cpu_to_le32(tmp);
2856         fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
2857         fence_pkt->addr = cpu_to_le64(fence_dma_addr +
2858                                         hdev->asic_prop.host_phys_base_address);
2859
2860         rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
2861                                         job->job_cb_size, cb->bus_address);
2862         if (rc) {
2863                 dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
2864                 goto free_fence_ptr;
2865         }
2866
2867         rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) fence_ptr, timeout,
2868                                         &tmp);
2869
2870         hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
2871
2872         if ((rc) || (tmp != GOYA_QMAN0_FENCE_VAL)) {
2873                 dev_err(hdev->dev, "QMAN0 Job hasn't finished in time\n");
2874                 rc = -ETIMEDOUT;
2875         }
2876
2877 free_fence_ptr:
2878         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr,
2879                                         fence_dma_addr);
2880
2881         goya_qman0_set_security(hdev, false);
2882
2883         return rc;
2884 }
2885
2886 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
2887                                 u32 timeout, long *result)
2888 {
2889         struct goya_device *goya = hdev->asic_specific;
2890
2891         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
2892                 if (result)
2893                         *result = 0;
2894                 return 0;
2895         }
2896
2897         return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
2898                                         timeout, result);
2899 }
2900
2901 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
2902 {
2903         struct packet_msg_prot *fence_pkt;
2904         dma_addr_t pkt_dma_addr;
2905         u32 fence_val, tmp;
2906         dma_addr_t fence_dma_addr;
2907         u32 *fence_ptr;
2908         int rc;
2909
2910         fence_val = GOYA_QMAN0_FENCE_VAL;
2911
2912         fence_ptr = hdev->asic_funcs->dma_pool_zalloc(hdev, 4, GFP_KERNEL,
2913                                                         &fence_dma_addr);
2914         if (!fence_ptr) {
2915                 dev_err(hdev->dev,
2916                         "Failed to allocate memory for queue testing\n");
2917                 return -ENOMEM;
2918         }
2919
2920         *fence_ptr = 0;
2921
2922         fence_pkt = hdev->asic_funcs->dma_pool_zalloc(hdev,
2923                                         sizeof(struct packet_msg_prot),
2924                                         GFP_KERNEL, &pkt_dma_addr);
2925         if (!fence_pkt) {
2926                 dev_err(hdev->dev,
2927                         "Failed to allocate packet for queue testing\n");
2928                 rc = -ENOMEM;
2929                 goto free_fence_ptr;
2930         }
2931
2932         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
2933                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
2934                         (1 << GOYA_PKT_CTL_MB_SHIFT);
2935         fence_pkt->ctl = cpu_to_le32(tmp);
2936         fence_pkt->value = cpu_to_le32(fence_val);
2937         fence_pkt->addr = cpu_to_le64(fence_dma_addr +
2938                                         hdev->asic_prop.host_phys_base_address);
2939
2940         rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
2941                                         sizeof(struct packet_msg_prot),
2942                                         pkt_dma_addr);
2943         if (rc) {
2944                 dev_err(hdev->dev,
2945                         "Failed to send fence packet\n");
2946                 goto free_pkt;
2947         }
2948
2949         rc = hl_poll_timeout_memory(hdev, (u64) (uintptr_t) fence_ptr,
2950                                         GOYA_TEST_QUEUE_WAIT_USEC, &tmp);
2951
2952         hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
2953
2954         if ((!rc) && (tmp == fence_val)) {
2955                 dev_info(hdev->dev,
2956                         "queue test on H/W queue %d succeeded\n",
2957                         hw_queue_id);
2958         } else {
2959                 dev_err(hdev->dev,
2960                         "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
2961                         hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
2962                 rc = -EINVAL;
2963         }
2964
2965 free_pkt:
2966         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_pkt,
2967                                         pkt_dma_addr);
2968 free_fence_ptr:
2969         hdev->asic_funcs->dma_pool_free(hdev, (void *) fence_ptr,
2970                                         fence_dma_addr);
2971         return rc;
2972 }
2973
2974 int goya_test_cpu_queue(struct hl_device *hdev)
2975 {
2976         struct goya_device *goya = hdev->asic_specific;
2977
2978         /*
2979          * check capability here as send_cpu_message() won't update the result
2980          * value if no capability
2981          */
2982         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
2983                 return 0;
2984
2985         return hl_fw_test_cpu_queue(hdev);
2986 }
2987
2988 int goya_test_queues(struct hl_device *hdev)
2989 {
2990         int i, rc, ret_val = 0;
2991
2992         for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
2993                 rc = goya_test_queue(hdev, i);
2994                 if (rc)
2995                         ret_val = -EINVAL;
2996         }
2997
2998         if (hdev->cpu_queues_enable) {
2999                 rc = goya_test_cpu_queue(hdev);
3000                 if (rc)
3001                         ret_val = -EINVAL;
3002         }
3003
3004         return ret_val;
3005 }
3006
3007 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3008                                         gfp_t mem_flags, dma_addr_t *dma_handle)
3009 {
3010         if (size > GOYA_DMA_POOL_BLK_SIZE)
3011                 return NULL;
3012
3013         return dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3014 }
3015
3016 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3017                                 dma_addr_t dma_addr)
3018 {
3019         dma_pool_free(hdev->dma_pool, vaddr, dma_addr);
3020 }
3021
3022 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3023                                         dma_addr_t *dma_handle)
3024 {
3025         return hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3026 }
3027
3028 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3029                                         void *vaddr)
3030 {
3031         hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3032 }
3033
3034 static int goya_dma_map_sg(struct hl_device *hdev, struct scatterlist *sg,
3035                                 int nents, enum dma_data_direction dir)
3036 {
3037         if (!dma_map_sg(&hdev->pdev->dev, sg, nents, dir))
3038                 return -ENOMEM;
3039
3040         return 0;
3041 }
3042
3043 static void goya_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sg,
3044                                 int nents, enum dma_data_direction dir)
3045 {
3046         dma_unmap_sg(&hdev->pdev->dev, sg, nents, dir);
3047 }
3048
3049 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3050 {
3051         struct scatterlist *sg, *sg_next_iter;
3052         u32 count, dma_desc_cnt;
3053         u64 len, len_next;
3054         dma_addr_t addr, addr_next;
3055
3056         dma_desc_cnt = 0;
3057
3058         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3059
3060                 len = sg_dma_len(sg);
3061                 addr = sg_dma_address(sg);
3062
3063                 if (len == 0)
3064                         break;
3065
3066                 while ((count + 1) < sgt->nents) {
3067                         sg_next_iter = sg_next(sg);
3068                         len_next = sg_dma_len(sg_next_iter);
3069                         addr_next = sg_dma_address(sg_next_iter);
3070
3071                         if (len_next == 0)
3072                                 break;
3073
3074                         if ((addr + len == addr_next) &&
3075                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3076                                 len += len_next;
3077                                 count++;
3078                                 sg = sg_next_iter;
3079                         } else {
3080                                 break;
3081                         }
3082                 }
3083
3084                 dma_desc_cnt++;
3085         }
3086
3087         return dma_desc_cnt * sizeof(struct packet_lin_dma);
3088 }
3089
3090 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3091                                 struct hl_cs_parser *parser,
3092                                 struct packet_lin_dma *user_dma_pkt,
3093                                 u64 addr, enum dma_data_direction dir)
3094 {
3095         struct hl_userptr *userptr;
3096         int rc;
3097
3098         if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3099                         parser->job_userptr_list, &userptr))
3100                 goto already_pinned;
3101
3102         userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC);
3103         if (!userptr)
3104                 return -ENOMEM;
3105
3106         rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3107                                 userptr);
3108         if (rc)
3109                 goto free_userptr;
3110
3111         list_add_tail(&userptr->job_node, parser->job_userptr_list);
3112
3113         rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl,
3114                                         userptr->sgt->nents, dir);
3115         if (rc) {
3116                 dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3117                 goto unpin_memory;
3118         }
3119
3120         userptr->dma_mapped = true;
3121         userptr->dir = dir;
3122
3123 already_pinned:
3124         parser->patched_cb_size +=
3125                         goya_get_dma_desc_list_size(hdev, userptr->sgt);
3126
3127         return 0;
3128
3129 unpin_memory:
3130         hl_unpin_host_memory(hdev, userptr);
3131 free_userptr:
3132         kfree(userptr);
3133         return rc;
3134 }
3135
3136 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3137                                 struct hl_cs_parser *parser,
3138                                 struct packet_lin_dma *user_dma_pkt)
3139 {
3140         u64 device_memory_addr, addr;
3141         enum dma_data_direction dir;
3142         enum goya_dma_direction user_dir;
3143         bool sram_addr = true;
3144         bool skip_host_mem_pin = false;
3145         bool user_memset;
3146         u32 ctl;
3147         int rc = 0;
3148
3149         ctl = le32_to_cpu(user_dma_pkt->ctl);
3150
3151         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3152                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3153
3154         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3155                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3156
3157         switch (user_dir) {
3158         case DMA_HOST_TO_DRAM:
3159                 dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3160                 dir = DMA_TO_DEVICE;
3161                 sram_addr = false;
3162                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3163                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3164                 if (user_memset)
3165                         skip_host_mem_pin = true;
3166                 break;
3167
3168         case DMA_DRAM_TO_HOST:
3169                 dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3170                 dir = DMA_FROM_DEVICE;
3171                 sram_addr = false;
3172                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3173                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3174                 break;
3175
3176         case DMA_HOST_TO_SRAM:
3177                 dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3178                 dir = DMA_TO_DEVICE;
3179                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3180                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3181                 if (user_memset)
3182                         skip_host_mem_pin = true;
3183                 break;
3184
3185         case DMA_SRAM_TO_HOST:
3186                 dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3187                 dir = DMA_FROM_DEVICE;
3188                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3189                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3190                 break;
3191         default:
3192                 dev_err(hdev->dev, "DMA direction is undefined\n");
3193                 return -EFAULT;
3194         }
3195
3196         if (parser->ctx_id != HL_KERNEL_ASID_ID) {
3197                 if (sram_addr) {
3198                         if (!hl_mem_area_inside_range(device_memory_addr,
3199                                         le32_to_cpu(user_dma_pkt->tsize),
3200                                         hdev->asic_prop.sram_user_base_address,
3201                                         hdev->asic_prop.sram_end_address)) {
3202
3203                                 dev_err(hdev->dev,
3204                                         "SRAM address 0x%llx + 0x%x is invalid\n",
3205                                         device_memory_addr,
3206                                         user_dma_pkt->tsize);
3207                                 return -EFAULT;
3208                         }
3209                 } else {
3210                         if (!hl_mem_area_inside_range(device_memory_addr,
3211                                         le32_to_cpu(user_dma_pkt->tsize),
3212                                         hdev->asic_prop.dram_user_base_address,
3213                                         hdev->asic_prop.dram_end_address)) {
3214
3215                                 dev_err(hdev->dev,
3216                                         "DRAM address 0x%llx + 0x%x is invalid\n",
3217                                         device_memory_addr,
3218                                         user_dma_pkt->tsize);
3219                                 return -EFAULT;
3220                         }
3221                 }
3222         }
3223
3224         if (skip_host_mem_pin)
3225                 parser->patched_cb_size += sizeof(*user_dma_pkt);
3226         else {
3227                 if ((dir == DMA_TO_DEVICE) &&
3228                                 (parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3229                         dev_err(hdev->dev,
3230                                 "Can't DMA from host on queue other then 1\n");
3231                         return -EFAULT;
3232                 }
3233
3234                 rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3235                                                 addr, dir);
3236         }
3237
3238         return rc;
3239 }
3240
3241 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3242                                 struct hl_cs_parser *parser,
3243                                 struct packet_lin_dma *user_dma_pkt)
3244 {
3245         u64 sram_memory_addr, dram_memory_addr;
3246         enum goya_dma_direction user_dir;
3247         u32 ctl;
3248
3249         ctl = le32_to_cpu(user_dma_pkt->ctl);
3250         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3251                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3252
3253         if (user_dir == DMA_DRAM_TO_SRAM) {
3254                 dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3255                 dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3256                 sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3257         } else {
3258                 dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3259                 sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3260                 dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3261         }
3262
3263         if (!hl_mem_area_inside_range(sram_memory_addr,
3264                                 le32_to_cpu(user_dma_pkt->tsize),
3265                                 hdev->asic_prop.sram_user_base_address,
3266                                 hdev->asic_prop.sram_end_address)) {
3267                 dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3268                         sram_memory_addr, user_dma_pkt->tsize);
3269                 return -EFAULT;
3270         }
3271
3272         if (!hl_mem_area_inside_range(dram_memory_addr,
3273                                 le32_to_cpu(user_dma_pkt->tsize),
3274                                 hdev->asic_prop.dram_user_base_address,
3275                                 hdev->asic_prop.dram_end_address)) {
3276                 dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3277                         dram_memory_addr, user_dma_pkt->tsize);
3278                 return -EFAULT;
3279         }
3280
3281         parser->patched_cb_size += sizeof(*user_dma_pkt);
3282
3283         return 0;
3284 }
3285
3286 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3287                                 struct hl_cs_parser *parser,
3288                                 struct packet_lin_dma *user_dma_pkt)
3289 {
3290         enum goya_dma_direction user_dir;
3291         u32 ctl;
3292         int rc;
3293
3294         dev_dbg(hdev->dev, "DMA packet details:\n");
3295         dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr);
3296         dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr);
3297         dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize);
3298
3299         ctl = le32_to_cpu(user_dma_pkt->ctl);
3300         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3301                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3302
3303         /*
3304          * Special handling for DMA with size 0. The H/W has a bug where
3305          * this can cause the QMAN DMA to get stuck, so block it here.
3306          */
3307         if (user_dma_pkt->tsize == 0) {
3308                 dev_err(hdev->dev,
3309                         "Got DMA with size 0, might reset the device\n");
3310                 return -EINVAL;
3311         }
3312
3313         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM))
3314                 rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3315         else
3316                 rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3317
3318         return rc;
3319 }
3320
3321 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3322                                 struct hl_cs_parser *parser,
3323                                 struct packet_lin_dma *user_dma_pkt)
3324 {
3325         dev_dbg(hdev->dev, "DMA packet details:\n");
3326         dev_dbg(hdev->dev, "source == 0x%llx\n", user_dma_pkt->src_addr);
3327         dev_dbg(hdev->dev, "destination == 0x%llx\n", user_dma_pkt->dst_addr);
3328         dev_dbg(hdev->dev, "size == %u\n", user_dma_pkt->tsize);
3329
3330         /*
3331          * WA for HW-23.
3332          * We can't allow user to read from Host using QMANs other than 1.
3333          */
3334         if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3335                 hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3336                                 le32_to_cpu(user_dma_pkt->tsize),
3337                                 hdev->asic_prop.va_space_host_start_address,
3338                                 hdev->asic_prop.va_space_host_end_address)) {
3339                 dev_err(hdev->dev,
3340                         "Can't DMA from host on queue other then 1\n");
3341                 return -EFAULT;
3342         }
3343
3344         if (user_dma_pkt->tsize == 0) {
3345                 dev_err(hdev->dev,
3346                         "Got DMA with size 0, might reset the device\n");
3347                 return -EINVAL;
3348         }
3349
3350         parser->patched_cb_size += sizeof(*user_dma_pkt);
3351
3352         return 0;
3353 }
3354
3355 static int goya_validate_wreg32(struct hl_device *hdev,
3356                                 struct hl_cs_parser *parser,
3357                                 struct packet_wreg32 *wreg_pkt)
3358 {
3359         struct goya_device *goya = hdev->asic_specific;
3360         u32 sob_start_addr, sob_end_addr;
3361         u16 reg_offset;
3362
3363         reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3364                         GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3365
3366         dev_dbg(hdev->dev, "WREG32 packet details:\n");
3367         dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3368         dev_dbg(hdev->dev, "value      == 0x%x\n", wreg_pkt->value);
3369
3370         if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3371                 dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3372                         reg_offset);
3373                 return -EPERM;
3374         }
3375
3376         /*
3377          * With MMU, DMA channels are not secured, so it doesn't matter where
3378          * the WR COMP will be written to because it will go out with
3379          * non-secured property
3380          */
3381         if (goya->hw_cap_initialized & HW_CAP_MMU)
3382                 return 0;
3383
3384         sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3385         sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3386
3387         if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3388                         (le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3389
3390                 dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3391                         wreg_pkt->value);
3392                 return -EPERM;
3393         }
3394
3395         return 0;
3396 }
3397
3398 static int goya_validate_cb(struct hl_device *hdev,
3399                         struct hl_cs_parser *parser, bool is_mmu)
3400 {
3401         u32 cb_parsed_length = 0;
3402         int rc = 0;
3403
3404         parser->patched_cb_size = 0;
3405
3406         /* cb_user_size is more than 0 so loop will always be executed */
3407         while (cb_parsed_length < parser->user_cb_size) {
3408                 enum packet_id pkt_id;
3409                 u16 pkt_size;
3410                 void *user_pkt;
3411
3412                 user_pkt = (void *) (uintptr_t)
3413                         (parser->user_cb->kernel_address + cb_parsed_length);
3414
3415                 pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
3416                                 PACKET_HEADER_PACKET_ID_MASK) >>
3417                                         PACKET_HEADER_PACKET_ID_SHIFT);
3418
3419                 pkt_size = goya_packet_sizes[pkt_id];
3420                 cb_parsed_length += pkt_size;
3421                 if (cb_parsed_length > parser->user_cb_size) {
3422                         dev_err(hdev->dev,
3423                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3424                         rc = -EINVAL;
3425                         break;
3426                 }
3427
3428                 switch (pkt_id) {
3429                 case PACKET_WREG_32:
3430                         /*
3431                          * Although it is validated after copy in patch_cb(),
3432                          * need to validate here as well because patch_cb() is
3433                          * not called in MMU path while this function is called
3434                          */
3435                         rc = goya_validate_wreg32(hdev, parser, user_pkt);
3436                         break;
3437
3438                 case PACKET_WREG_BULK:
3439                         dev_err(hdev->dev,
3440                                 "User not allowed to use WREG_BULK\n");
3441                         rc = -EPERM;
3442                         break;
3443
3444                 case PACKET_MSG_PROT:
3445                         dev_err(hdev->dev,
3446                                 "User not allowed to use MSG_PROT\n");
3447                         rc = -EPERM;
3448                         break;
3449
3450                 case PACKET_CP_DMA:
3451                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3452                         rc = -EPERM;
3453                         break;
3454
3455                 case PACKET_STOP:
3456                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3457                         rc = -EPERM;
3458                         break;
3459
3460                 case PACKET_LIN_DMA:
3461                         if (is_mmu)
3462                                 rc = goya_validate_dma_pkt_mmu(hdev, parser,
3463                                                 user_pkt);
3464                         else
3465                                 rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3466                                                 user_pkt);
3467                         break;
3468
3469                 case PACKET_MSG_LONG:
3470                 case PACKET_MSG_SHORT:
3471                 case PACKET_FENCE:
3472                 case PACKET_NOP:
3473                         parser->patched_cb_size += pkt_size;
3474                         break;
3475
3476                 default:
3477                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3478                                 pkt_id);
3479                         rc = -EINVAL;
3480                         break;
3481                 }
3482
3483                 if (rc)
3484                         break;
3485         }
3486
3487         /*
3488          * The new CB should have space at the end for two MSG_PROT packets:
3489          * 1. A packet that will act as a completion packet
3490          * 2. A packet that will generate MSI-X interrupt
3491          */
3492         parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3493
3494         return rc;
3495 }
3496
3497 static int goya_patch_dma_packet(struct hl_device *hdev,
3498                                 struct hl_cs_parser *parser,
3499                                 struct packet_lin_dma *user_dma_pkt,
3500                                 struct packet_lin_dma *new_dma_pkt,
3501                                 u32 *new_dma_pkt_size)
3502 {
3503         struct hl_userptr *userptr;
3504         struct scatterlist *sg, *sg_next_iter;
3505         u32 count, dma_desc_cnt;
3506         u64 len, len_next;
3507         dma_addr_t dma_addr, dma_addr_next;
3508         enum goya_dma_direction user_dir;
3509         u64 device_memory_addr, addr;
3510         enum dma_data_direction dir;
3511         struct sg_table *sgt;
3512         bool skip_host_mem_pin = false;
3513         bool user_memset;
3514         u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3515
3516         ctl = le32_to_cpu(user_dma_pkt->ctl);
3517
3518         user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3519                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3520
3521         user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3522                         GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3523
3524         if ((user_dir == DMA_DRAM_TO_SRAM) || (user_dir == DMA_SRAM_TO_DRAM) ||
3525                         (user_dma_pkt->tsize == 0)) {
3526                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3527                 *new_dma_pkt_size = sizeof(*new_dma_pkt);
3528                 return 0;
3529         }
3530
3531         if ((user_dir == DMA_HOST_TO_DRAM) || (user_dir == DMA_HOST_TO_SRAM)) {
3532                 addr = le64_to_cpu(user_dma_pkt->src_addr);
3533                 device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3534                 dir = DMA_TO_DEVICE;
3535                 if (user_memset)
3536                         skip_host_mem_pin = true;
3537         } else {
3538                 addr = le64_to_cpu(user_dma_pkt->dst_addr);
3539                 device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3540                 dir = DMA_FROM_DEVICE;
3541         }
3542
3543         if ((!skip_host_mem_pin) &&
3544                 (hl_userptr_is_pinned(hdev, addr,
3545                         le32_to_cpu(user_dma_pkt->tsize),
3546                         parser->job_userptr_list, &userptr) == false)) {
3547                 dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3548                                 addr, user_dma_pkt->tsize);
3549                 return -EFAULT;
3550         }
3551
3552         if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3553                 memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3554                 *new_dma_pkt_size = sizeof(*user_dma_pkt);
3555                 return 0;
3556         }
3557
3558         user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3559
3560         user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3561
3562         sgt = userptr->sgt;
3563         dma_desc_cnt = 0;
3564
3565         for_each_sg(sgt->sgl, sg, sgt->nents, count) {
3566                 len = sg_dma_len(sg);
3567                 dma_addr = sg_dma_address(sg);
3568
3569                 if (len == 0)
3570                         break;
3571
3572                 while ((count + 1) < sgt->nents) {
3573                         sg_next_iter = sg_next(sg);
3574                         len_next = sg_dma_len(sg_next_iter);
3575                         dma_addr_next = sg_dma_address(sg_next_iter);
3576
3577                         if (len_next == 0)
3578                                 break;
3579
3580                         if ((dma_addr + len == dma_addr_next) &&
3581                                 (len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3582                                 len += len_next;
3583                                 count++;
3584                                 sg = sg_next_iter;
3585                         } else {
3586                                 break;
3587                         }
3588                 }
3589
3590                 ctl = le32_to_cpu(user_dma_pkt->ctl);
3591                 if (likely(dma_desc_cnt))
3592                         ctl &= ~GOYA_PKT_CTL_EB_MASK;
3593                 ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3594                                 GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3595                 new_dma_pkt->ctl = cpu_to_le32(ctl);
3596                 new_dma_pkt->tsize = cpu_to_le32((u32) len);
3597
3598                 dma_addr += hdev->asic_prop.host_phys_base_address;
3599
3600                 if (dir == DMA_TO_DEVICE) {
3601                         new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3602                         new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3603                 } else {
3604                         new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3605                         new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3606                 }
3607
3608                 if (!user_memset)
3609                         device_memory_addr += len;
3610                 dma_desc_cnt++;
3611                 new_dma_pkt++;
3612         }
3613
3614         if (!dma_desc_cnt) {
3615                 dev_err(hdev->dev,
3616                         "Error of 0 SG entries when patching DMA packet\n");
3617                 return -EFAULT;
3618         }
3619
3620         /* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3621         new_dma_pkt--;
3622         new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3623
3624         *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3625
3626         return 0;
3627 }
3628
3629 static int goya_patch_cb(struct hl_device *hdev,
3630                                 struct hl_cs_parser *parser)
3631 {
3632         u32 cb_parsed_length = 0;
3633         u32 cb_patched_cur_length = 0;
3634         int rc = 0;
3635
3636         /* cb_user_size is more than 0 so loop will always be executed */
3637         while (cb_parsed_length < parser->user_cb_size) {
3638                 enum packet_id pkt_id;
3639                 u16 pkt_size;
3640                 u32 new_pkt_size = 0;
3641                 void *user_pkt, *kernel_pkt;
3642
3643                 user_pkt = (void *) (uintptr_t)
3644                         (parser->user_cb->kernel_address + cb_parsed_length);
3645                 kernel_pkt = (void *) (uintptr_t)
3646                         (parser->patched_cb->kernel_address +
3647                                         cb_patched_cur_length);
3648
3649                 pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
3650                                 PACKET_HEADER_PACKET_ID_MASK) >>
3651                                         PACKET_HEADER_PACKET_ID_SHIFT);
3652
3653                 pkt_size = goya_packet_sizes[pkt_id];
3654                 cb_parsed_length += pkt_size;
3655                 if (cb_parsed_length > parser->user_cb_size) {
3656                         dev_err(hdev->dev,
3657                                 "packet 0x%x is out of CB boundary\n", pkt_id);
3658                         rc = -EINVAL;
3659                         break;
3660                 }
3661
3662                 switch (pkt_id) {
3663                 case PACKET_LIN_DMA:
3664                         rc = goya_patch_dma_packet(hdev, parser, user_pkt,
3665                                                 kernel_pkt, &new_pkt_size);
3666                         cb_patched_cur_length += new_pkt_size;
3667                         break;
3668
3669                 case PACKET_WREG_32:
3670                         memcpy(kernel_pkt, user_pkt, pkt_size);
3671                         cb_patched_cur_length += pkt_size;
3672                         rc = goya_validate_wreg32(hdev, parser, kernel_pkt);
3673                         break;
3674
3675                 case PACKET_WREG_BULK:
3676                         dev_err(hdev->dev,
3677                                 "User not allowed to use WREG_BULK\n");
3678                         rc = -EPERM;
3679                         break;
3680
3681                 case PACKET_MSG_PROT:
3682                         dev_err(hdev->dev,
3683                                 "User not allowed to use MSG_PROT\n");
3684                         rc = -EPERM;
3685                         break;
3686
3687                 case PACKET_CP_DMA:
3688                         dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3689                         rc = -EPERM;
3690                         break;
3691
3692                 case PACKET_STOP:
3693                         dev_err(hdev->dev, "User not allowed to use STOP\n");
3694                         rc = -EPERM;
3695                         break;
3696
3697                 case PACKET_MSG_LONG:
3698                 case PACKET_MSG_SHORT:
3699                 case PACKET_FENCE:
3700                 case PACKET_NOP:
3701                         memcpy(kernel_pkt, user_pkt, pkt_size);
3702                         cb_patched_cur_length += pkt_size;
3703                         break;
3704
3705                 default:
3706                         dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3707                                 pkt_id);
3708                         rc = -EINVAL;
3709                         break;
3710                 }
3711
3712                 if (rc)
3713                         break;
3714         }
3715
3716         return rc;
3717 }
3718
3719 static int goya_parse_cb_mmu(struct hl_device *hdev,
3720                 struct hl_cs_parser *parser)
3721 {
3722         u64 patched_cb_handle;
3723         u32 patched_cb_size;
3724         struct hl_cb *user_cb;
3725         int rc;
3726
3727         /*
3728          * The new CB should have space at the end for two MSG_PROT pkt:
3729          * 1. A packet that will act as a completion packet
3730          * 2. A packet that will generate MSI-X interrupt
3731          */
3732         parser->patched_cb_size = parser->user_cb_size +
3733                         sizeof(struct packet_msg_prot) * 2;
3734
3735         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
3736                                 parser->patched_cb_size,
3737                                 &patched_cb_handle, HL_KERNEL_ASID_ID);
3738
3739         if (rc) {
3740                 dev_err(hdev->dev,
3741                         "Failed to allocate patched CB for DMA CS %d\n",
3742                         rc);
3743                 return rc;
3744         }
3745
3746         patched_cb_handle >>= PAGE_SHIFT;
3747         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3748                                 (u32) patched_cb_handle);
3749         /* hl_cb_get should never fail here so use kernel WARN */
3750         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
3751                         (u32) patched_cb_handle);
3752         if (!parser->patched_cb) {
3753                 rc = -EFAULT;
3754                 goto out;
3755         }
3756
3757         /*
3758          * The check that parser->user_cb_size <= parser->user_cb->size was done
3759          * in validate_queue_index().
3760          */
3761         memcpy((void *) (uintptr_t) parser->patched_cb->kernel_address,
3762                 (void *) (uintptr_t) parser->user_cb->kernel_address,
3763                 parser->user_cb_size);
3764
3765         patched_cb_size = parser->patched_cb_size;
3766
3767         /* validate patched CB instead of user CB */
3768         user_cb = parser->user_cb;
3769         parser->user_cb = parser->patched_cb;
3770         rc = goya_validate_cb(hdev, parser, true);
3771         parser->user_cb = user_cb;
3772
3773         if (rc) {
3774                 hl_cb_put(parser->patched_cb);
3775                 goto out;
3776         }
3777
3778         if (patched_cb_size != parser->patched_cb_size) {
3779                 dev_err(hdev->dev, "user CB size mismatch\n");
3780                 hl_cb_put(parser->patched_cb);
3781                 rc = -EINVAL;
3782                 goto out;
3783         }
3784
3785 out:
3786         /*
3787          * Always call cb destroy here because we still have 1 reference
3788          * to it by calling cb_get earlier. After the job will be completed,
3789          * cb_put will release it, but here we want to remove it from the
3790          * idr
3791          */
3792         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
3793                                         patched_cb_handle << PAGE_SHIFT);
3794
3795         return rc;
3796 }
3797
3798 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
3799                                 struct hl_cs_parser *parser)
3800 {
3801         u64 patched_cb_handle;
3802         int rc;
3803
3804         rc = goya_validate_cb(hdev, parser, false);
3805
3806         if (rc)
3807                 goto free_userptr;
3808
3809         rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr,
3810                                 parser->patched_cb_size,
3811                                 &patched_cb_handle, HL_KERNEL_ASID_ID);
3812         if (rc) {
3813                 dev_err(hdev->dev,
3814                         "Failed to allocate patched CB for DMA CS %d\n", rc);
3815                 goto free_userptr;
3816         }
3817
3818         patched_cb_handle >>= PAGE_SHIFT;
3819         parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr,
3820                                 (u32) patched_cb_handle);
3821         /* hl_cb_get should never fail here so use kernel WARN */
3822         WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n",
3823                         (u32) patched_cb_handle);
3824         if (!parser->patched_cb) {
3825                 rc = -EFAULT;
3826                 goto out;
3827         }
3828
3829         rc = goya_patch_cb(hdev, parser);
3830
3831         if (rc)
3832                 hl_cb_put(parser->patched_cb);
3833
3834 out:
3835         /*
3836          * Always call cb destroy here because we still have 1 reference
3837          * to it by calling cb_get earlier. After the job will be completed,
3838          * cb_put will release it, but here we want to remove it from the
3839          * idr
3840          */
3841         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr,
3842                                 patched_cb_handle << PAGE_SHIFT);
3843
3844 free_userptr:
3845         if (rc)
3846                 hl_userptr_delete_list(hdev, parser->job_userptr_list);
3847         return rc;
3848 }
3849
3850 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
3851                                         struct hl_cs_parser *parser)
3852 {
3853         struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
3854         struct goya_device *goya = hdev->asic_specific;
3855
3856         if (goya->hw_cap_initialized & HW_CAP_MMU)
3857                 return 0;
3858
3859         /* For internal queue jobs, just check if CB address is valid */
3860         if (hl_mem_area_inside_range(
3861                         (u64) (uintptr_t) parser->user_cb,
3862                         parser->user_cb_size,
3863                         asic_prop->sram_user_base_address,
3864                         asic_prop->sram_end_address))
3865                 return 0;
3866
3867         if (hl_mem_area_inside_range(
3868                         (u64) (uintptr_t) parser->user_cb,
3869                         parser->user_cb_size,
3870                         asic_prop->dram_user_base_address,
3871                         asic_prop->dram_end_address))
3872                 return 0;
3873
3874         dev_err(hdev->dev,
3875                 "Internal CB address %px + 0x%x is not in SRAM nor in DRAM\n",
3876                 parser->user_cb, parser->user_cb_size);
3877
3878         return -EFAULT;
3879 }
3880
3881 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
3882 {
3883         struct goya_device *goya = hdev->asic_specific;
3884
3885         if (!parser->ext_queue)
3886                 return goya_parse_cb_no_ext_queue(hdev, parser);
3887
3888         if ((goya->hw_cap_initialized & HW_CAP_MMU) && parser->use_virt_addr)
3889                 return goya_parse_cb_mmu(hdev, parser);
3890         else
3891                 return goya_parse_cb_no_mmu(hdev, parser);
3892 }
3893
3894 void goya_add_end_of_cb_packets(u64 kernel_address, u32 len, u64 cq_addr,
3895                                 u32 cq_val, u32 msix_vec)
3896 {
3897         struct packet_msg_prot *cq_pkt;
3898         u32 tmp;
3899
3900         cq_pkt = (struct packet_msg_prot *) (uintptr_t)
3901                 (kernel_address + len - (sizeof(struct packet_msg_prot) * 2));
3902
3903         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3904                         (1 << GOYA_PKT_CTL_EB_SHIFT) |
3905                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3906         cq_pkt->ctl = cpu_to_le32(tmp);
3907         cq_pkt->value = cpu_to_le32(cq_val);
3908         cq_pkt->addr = cpu_to_le64(cq_addr);
3909
3910         cq_pkt++;
3911
3912         tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3913                         (1 << GOYA_PKT_CTL_MB_SHIFT);
3914         cq_pkt->ctl = cpu_to_le32(tmp);
3915         cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
3916         cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
3917 }
3918
3919 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
3920 {
3921         WREG32(mmPSOC_GLOBAL_CONF_SCRATCHPAD_6, val);
3922 }
3923
3924 void goya_restore_phase_topology(struct hl_device *hdev)
3925 {
3926         int i, num_of_sob_in_longs, num_of_mon_in_longs;
3927
3928         num_of_sob_in_longs =
3929                 ((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
3930
3931         num_of_mon_in_longs =
3932                 ((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
3933
3934         for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
3935                 WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
3936
3937         for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
3938                 WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
3939
3940         /* Flush all WREG to prevent race */
3941         i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
3942 }
3943
3944 /*
3945  * goya_debugfs_read32 - read a 32bit value from a given device address
3946  *
3947  * @hdev:       pointer to hl_device structure
3948  * @addr:       address in device
3949  * @val:        returned value
3950  *
3951  * In case of DDR address that is not mapped into the default aperture that
3952  * the DDR bar exposes, the function will configure the iATU so that the DDR
3953  * bar will be positioned at a base address that allows reading from the
3954  * required address. Configuring the iATU during normal operation can
3955  * lead to undefined behavior and therefore, should be done with extreme care
3956  *
3957  */
3958 static int goya_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val)
3959 {
3960         struct asic_fixed_properties *prop = &hdev->asic_prop;
3961         int rc = 0;
3962
3963         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
3964                 *val = RREG32(addr - CFG_BASE);
3965
3966         } else if ((addr >= SRAM_BASE_ADDR) &&
3967                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
3968
3969                 *val = readl(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
3970                                 (addr - SRAM_BASE_ADDR));
3971
3972         } else if ((addr >= DRAM_PHYS_BASE) &&
3973                         (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
3974
3975                 u64 bar_base_addr = DRAM_PHYS_BASE +
3976                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
3977
3978                 rc = goya_set_ddr_bar_base(hdev, bar_base_addr);
3979                 if (!rc) {
3980                         *val = readl(hdev->pcie_bar[DDR_BAR_ID] +
3981                                                 (addr - bar_base_addr));
3982
3983                         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
3984                                 (MMU_PAGE_TABLES_ADDR &
3985                                         ~(prop->dram_pci_bar_size - 0x1ull)));
3986                 }
3987         } else {
3988                 rc = -EFAULT;
3989         }
3990
3991         return rc;
3992 }
3993
3994 /*
3995  * goya_debugfs_write32 - write a 32bit value to a given device address
3996  *
3997  * @hdev:       pointer to hl_device structure
3998  * @addr:       address in device
3999  * @val:        returned value
4000  *
4001  * In case of DDR address that is not mapped into the default aperture that
4002  * the DDR bar exposes, the function will configure the iATU so that the DDR
4003  * bar will be positioned at a base address that allows writing to the
4004  * required address. Configuring the iATU during normal operation can
4005  * lead to undefined behavior and therefore, should be done with extreme care
4006  *
4007  */
4008 static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val)
4009 {
4010         struct asic_fixed_properties *prop = &hdev->asic_prop;
4011         int rc = 0;
4012
4013         if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) {
4014                 WREG32(addr - CFG_BASE, val);
4015
4016         } else if ((addr >= SRAM_BASE_ADDR) &&
4017                         (addr < SRAM_BASE_ADDR + SRAM_SIZE)) {
4018
4019                 writel(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
4020                                         (addr - SRAM_BASE_ADDR));
4021
4022         } else if ((addr >= DRAM_PHYS_BASE) &&
4023                         (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size)) {
4024
4025                 u64 bar_base_addr = DRAM_PHYS_BASE +
4026                                 (addr & ~(prop->dram_pci_bar_size - 0x1ull));
4027
4028                 rc = goya_set_ddr_bar_base(hdev, bar_base_addr);
4029                 if (!rc) {
4030                         writel(val, hdev->pcie_bar[DDR_BAR_ID] +
4031                                                 (addr - bar_base_addr));
4032
4033                         rc = goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE +
4034                                 (MMU_PAGE_TABLES_ADDR &
4035                                         ~(prop->dram_pci_bar_size - 0x1ull)));
4036                 }
4037         } else {
4038                 rc = -EFAULT;
4039         }
4040
4041         return rc;
4042 }
4043
4044 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4045 {
4046         struct goya_device *goya = hdev->asic_specific;
4047
4048         if (hdev->hard_reset_pending)
4049                 return U64_MAX;
4050
4051         return readq(hdev->pcie_bar[DDR_BAR_ID] +
4052                         (addr - goya->ddr_bar_cur_addr));
4053 }
4054
4055 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4056 {
4057         struct goya_device *goya = hdev->asic_specific;
4058
4059         if (hdev->hard_reset_pending)
4060                 return;
4061
4062         writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4063                         (addr - goya->ddr_bar_cur_addr));
4064 }
4065
4066 static const char *_goya_get_event_desc(u16 event_type)
4067 {
4068         switch (event_type) {
4069         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4070                 return "PCIe_dec";
4071         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4072         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4073         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4074         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4075         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4076         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4077         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4078         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4079                 return "TPC%d_dec";
4080         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4081                 return "MME_wacs";
4082         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4083                 return "MME_wacsd";
4084         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4085                 return "CPU_axi_splitter";
4086         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4087                 return "PSOC_axi_dec";
4088         case GOYA_ASYNC_EVENT_ID_PSOC:
4089                 return "PSOC";
4090         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4091         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4092         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4093         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4094         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4095         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4096         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4097         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4098                 return "TPC%d_krn_err";
4099         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4100                 return "TPC%d_cq";
4101         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4102                 return "TPC%d_qm";
4103         case GOYA_ASYNC_EVENT_ID_MME_QM:
4104                 return "MME_qm";
4105         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4106                 return "MME_cq";
4107         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4108                 return "DMA%d_qm";
4109         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4110                 return "DMA%d_ch";
4111         default:
4112                 return "N/A";
4113         }
4114 }
4115
4116 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4117 {
4118         u8 index;
4119
4120         switch (event_type) {
4121         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4122         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4123         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4124         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4125         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4126         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4127         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4128         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4129                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4130                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4131                 break;
4132         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4133         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4134         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4135         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4136         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4137         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4138         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4139         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4140                 index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4141                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4142                 break;
4143         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4144                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4145                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4146                 break;
4147         case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4148                 index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4149                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4150                 break;
4151         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4152                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4153                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4154                 break;
4155         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4156                 index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4157                 snprintf(desc, size, _goya_get_event_desc(event_type), index);
4158                 break;
4159         default:
4160                 snprintf(desc, size, _goya_get_event_desc(event_type));
4161                 break;
4162         }
4163 }
4164
4165 static void goya_print_razwi_info(struct hl_device *hdev)
4166 {
4167         if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4168                 dev_err(hdev->dev, "Illegal write to LBW\n");
4169                 WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4170         }
4171
4172         if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4173                 dev_err(hdev->dev, "Illegal read from LBW\n");
4174                 WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4175         }
4176
4177         if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4178                 dev_err(hdev->dev, "Illegal write to HBW\n");
4179                 WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4180         }
4181
4182         if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4183                 dev_err(hdev->dev, "Illegal read from HBW\n");
4184                 WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4185         }
4186 }
4187
4188 static void goya_print_mmu_error_info(struct hl_device *hdev)
4189 {
4190         struct goya_device *goya = hdev->asic_specific;
4191         u64 addr;
4192         u32 val;
4193
4194         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4195                 return;
4196
4197         val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4198         if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4199                 addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4200                 addr <<= 32;
4201                 addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4202
4203                 dev_err(hdev->dev, "MMU page fault on va 0x%llx\n", addr);
4204
4205                 WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4206         }
4207 }
4208
4209 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type)
4210 {
4211         char desc[20] = "";
4212
4213         goya_get_event_desc(event_type, desc, sizeof(desc));
4214         dev_err(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4215                 event_type, desc);
4216
4217         goya_print_razwi_info(hdev);
4218         goya_print_mmu_error_info(hdev);
4219 }
4220
4221 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4222                 size_t irq_arr_size)
4223 {
4224         struct armcp_unmask_irq_arr_packet *pkt;
4225         size_t total_pkt_size;
4226         long result;
4227         int rc;
4228
4229         total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) +
4230                         irq_arr_size;
4231
4232         /* data should be aligned to 8 bytes in order to ArmCP to copy it */
4233         total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4234
4235         /* total_pkt_size is casted to u16 later on */
4236         if (total_pkt_size > USHRT_MAX) {
4237                 dev_err(hdev->dev, "too many elements in IRQ array\n");
4238                 return -EINVAL;
4239         }
4240
4241         pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4242         if (!pkt)
4243                 return -ENOMEM;
4244
4245         pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0]));
4246         memcpy(&pkt->irqs, irq_arr, irq_arr_size);
4247
4248         pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4249                                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
4250
4251         rc = goya_send_cpu_message(hdev, (u32 *) pkt, total_pkt_size,
4252                         HL_DEVICE_TIMEOUT_USEC, &result);
4253
4254         if (rc)
4255                 dev_err(hdev->dev, "failed to unmask IRQ array\n");
4256
4257         kfree(pkt);
4258
4259         return rc;
4260 }
4261
4262 static int goya_soft_reset_late_init(struct hl_device *hdev)
4263 {
4264         /*
4265          * Unmask all IRQs since some could have been received
4266          * during the soft reset
4267          */
4268         return goya_unmask_irq_arr(hdev, goya_all_events,
4269                                         sizeof(goya_all_events));
4270 }
4271
4272 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4273 {
4274         struct armcp_packet pkt;
4275         long result;
4276         int rc;
4277
4278         memset(&pkt, 0, sizeof(pkt));
4279
4280         pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ <<
4281                                 ARMCP_PKT_CTL_OPCODE_SHIFT);
4282         pkt.value = cpu_to_le64(event_type);
4283
4284         rc = goya_send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4285                         HL_DEVICE_TIMEOUT_USEC, &result);
4286
4287         if (rc)
4288                 dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4289
4290         return rc;
4291 }
4292
4293 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4294 {
4295         u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4296         u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4297                                 >> EQ_CTL_EVENT_TYPE_SHIFT);
4298         struct goya_device *goya = hdev->asic_specific;
4299
4300         goya->events_stat[event_type]++;
4301
4302         switch (event_type) {
4303         case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4304         case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4305         case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4306         case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4307         case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4308         case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4309         case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4310         case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4311         case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4312         case GOYA_ASYNC_EVENT_ID_MME_ECC:
4313         case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4314         case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4315         case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4316         case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4317         case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4318         case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4319         case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4320         case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4321         case GOYA_ASYNC_EVENT_ID_GIC500:
4322         case GOYA_ASYNC_EVENT_ID_PLL0:
4323         case GOYA_ASYNC_EVENT_ID_PLL1:
4324         case GOYA_ASYNC_EVENT_ID_PLL3:
4325         case GOYA_ASYNC_EVENT_ID_PLL4:
4326         case GOYA_ASYNC_EVENT_ID_PLL5:
4327         case GOYA_ASYNC_EVENT_ID_PLL6:
4328         case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4329         case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4330         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4331         case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4332                 dev_err(hdev->dev,
4333                         "Received H/W interrupt %d, reset the chip\n",
4334                         event_type);
4335                 hl_device_reset(hdev, true, false);
4336                 break;
4337
4338         case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4339         case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4340         case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4341         case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4342         case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4343         case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4344         case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4345         case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4346         case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4347         case GOYA_ASYNC_EVENT_ID_MME_WACS:
4348         case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4349         case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4350         case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4351         case GOYA_ASYNC_EVENT_ID_PSOC:
4352         case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4353         case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4354         case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4355         case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4356         case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4357         case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4358         case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4359         case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4360         case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4361         case GOYA_ASYNC_EVENT_ID_MME_QM:
4362         case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4363         case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4364         case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4365                 goya_print_irq_info(hdev, event_type);
4366                 goya_unmask_irq(hdev, event_type);
4367                 break;
4368
4369         case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4370         case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4371         case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4372         case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4373         case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4374         case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4375         case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4376         case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4377         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0:
4378         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH1:
4379         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH2:
4380         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH3:
4381         case GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4382                 dev_info(hdev->dev, "Received H/W interrupt %d\n", event_type);
4383                 break;
4384
4385         default:
4386                 dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4387                                 event_type);
4388                 break;
4389         }
4390 }
4391
4392 void *goya_get_events_stat(struct hl_device *hdev, u32 *size)
4393 {
4394         struct goya_device *goya = hdev->asic_specific;
4395
4396         *size = (u32) sizeof(goya->events_stat);
4397
4398         return goya->events_stat;
4399 }
4400
4401 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u32 size,
4402                                 u64 val, bool is_dram)
4403 {
4404         struct packet_lin_dma *lin_dma_pkt;
4405         struct hl_cs_parser parser;
4406         struct hl_cs_job *job;
4407         u32 cb_size, ctl;
4408         struct hl_cb *cb;
4409         int rc;
4410
4411         cb = hl_cb_kernel_create(hdev, PAGE_SIZE);
4412         if (!cb)
4413                 return -EFAULT;
4414
4415         lin_dma_pkt = (struct packet_lin_dma *) (uintptr_t) cb->kernel_address;
4416
4417         memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4418         cb_size = sizeof(*lin_dma_pkt);
4419
4420         ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4421                         (1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4422                         (1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4423                         (1 << GOYA_PKT_CTL_RB_SHIFT) |
4424                         (1 << GOYA_PKT_CTL_MB_SHIFT));
4425         ctl |= (is_dram ? DMA_HOST_TO_DRAM : DMA_HOST_TO_SRAM) <<
4426                         GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4427         lin_dma_pkt->ctl = cpu_to_le32(ctl);
4428
4429         lin_dma_pkt->src_addr = cpu_to_le64(val);
4430         lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4431         lin_dma_pkt->tsize = cpu_to_le32(size);
4432
4433         job = hl_cs_allocate_job(hdev, true);
4434         if (!job) {
4435                 dev_err(hdev->dev, "Failed to allocate a new job\n");
4436                 rc = -ENOMEM;
4437                 goto release_cb;
4438         }
4439
4440         job->id = 0;
4441         job->user_cb = cb;
4442         job->user_cb->cs_cnt++;
4443         job->user_cb_size = cb_size;
4444         job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4445
4446         hl_debugfs_add_job(hdev, job);
4447
4448         parser.ctx_id = HL_KERNEL_ASID_ID;
4449         parser.cs_sequence = 0;
4450         parser.job_id = job->id;
4451         parser.hw_queue_id = job->hw_queue_id;
4452         parser.job_userptr_list = &job->userptr_list;
4453         parser.user_cb = job->user_cb;
4454         parser.user_cb_size = job->user_cb_size;
4455         parser.ext_queue = job->ext_queue;
4456         parser.use_virt_addr = hdev->mmu_enable;
4457
4458         rc = hdev->asic_funcs->cs_parser(hdev, &parser);
4459         if (rc) {
4460                 dev_err(hdev->dev, "Failed to parse kernel CB\n");
4461                 goto free_job;
4462         }
4463
4464         job->patched_cb = parser.patched_cb;
4465         job->job_cb_size = parser.patched_cb_size;
4466         job->patched_cb->cs_cnt++;
4467
4468         rc = goya_send_job_on_qman0(hdev, job);
4469
4470         job->patched_cb->cs_cnt--;
4471         hl_cb_put(job->patched_cb);
4472
4473 free_job:
4474         hl_userptr_delete_list(hdev, &job->userptr_list);
4475         hl_debugfs_remove_job(hdev, job);
4476         kfree(job);
4477         cb->cs_cnt--;
4478
4479 release_cb:
4480         hl_cb_put(cb);
4481         hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT);
4482
4483         return rc;
4484 }
4485
4486 int goya_context_switch(struct hl_device *hdev, u32 asid)
4487 {
4488         struct asic_fixed_properties *prop = &hdev->asic_prop;
4489         u64 addr = prop->sram_base_address;
4490         u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4491         u64 val = 0x7777777777777777ull;
4492         int rc;
4493
4494         rc = goya_memset_device_memory(hdev, addr, size, val, false);
4495         if (rc) {
4496                 dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
4497                 return rc;
4498         }
4499
4500         WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
4501         goya_mmu_prepare(hdev, asid);
4502
4503         return 0;
4504 }
4505
4506 int goya_mmu_clear_pgt_range(struct hl_device *hdev)
4507 {
4508         struct asic_fixed_properties *prop = &hdev->asic_prop;
4509         struct goya_device *goya = hdev->asic_specific;
4510         u64 addr = prop->mmu_pgt_addr;
4511         u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
4512                         MMU_CACHE_MNG_SIZE;
4513
4514         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4515                 return 0;
4516
4517         return goya_memset_device_memory(hdev, addr, size, 0, true);
4518 }
4519
4520 int goya_mmu_set_dram_default_page(struct hl_device *hdev)
4521 {
4522         struct goya_device *goya = hdev->asic_specific;
4523         u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
4524         u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
4525         u64 val = 0x9999999999999999ull;
4526
4527         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4528                 return 0;
4529
4530         return goya_memset_device_memory(hdev, addr, size, val, true);
4531 }
4532
4533 void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
4534 {
4535         struct goya_device *goya = hdev->asic_specific;
4536         int i;
4537
4538         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4539                 return;
4540
4541         if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
4542                 WARN(1, "asid %u is too big\n", asid);
4543                 return;
4544         }
4545
4546         /* zero the MMBP and ASID bits and then set the ASID */
4547         for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
4548                 goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
4549 }
4550
4551 static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard)
4552 {
4553         struct goya_device *goya = hdev->asic_specific;
4554         u32 status, timeout_usec;
4555         int rc;
4556
4557         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4558                 return;
4559
4560         /* no need in L1 only invalidation in Goya */
4561         if (!is_hard)
4562                 return;
4563
4564         if (hdev->pldm)
4565                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
4566         else
4567                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
4568
4569         mutex_lock(&hdev->mmu_cache_lock);
4570
4571         /* L0 & L1 invalidation */
4572         WREG32(mmSTLB_INV_ALL_START, 1);
4573
4574         rc = hl_poll_timeout(
4575                 hdev,
4576                 mmSTLB_INV_ALL_START,
4577                 status,
4578                 !status,
4579                 1000,
4580                 timeout_usec);
4581
4582         mutex_unlock(&hdev->mmu_cache_lock);
4583
4584         if (rc)
4585                 dev_notice_ratelimited(hdev->dev,
4586                         "Timeout when waiting for MMU cache invalidation\n");
4587 }
4588
4589 static void goya_mmu_invalidate_cache_range(struct hl_device *hdev,
4590                 bool is_hard, u32 asid, u64 va, u64 size)
4591 {
4592         struct goya_device *goya = hdev->asic_specific;
4593         u32 status, timeout_usec, inv_data, pi;
4594         int rc;
4595
4596         if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4597                 return;
4598
4599         /* no need in L1 only invalidation in Goya */
4600         if (!is_hard)
4601                 return;
4602
4603         if (hdev->pldm)
4604                 timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
4605         else
4606                 timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
4607
4608         mutex_lock(&hdev->mmu_cache_lock);
4609
4610         /*
4611          * TODO: currently invalidate entire L0 & L1 as in regular hard
4612          * invalidation. Need to apply invalidation of specific cache lines with
4613          * mask of ASID & VA & size.
4614          * Note that L1 with be flushed entirely in any case.
4615          */
4616
4617         /* L0 & L1 invalidation */
4618         inv_data = RREG32(mmSTLB_CACHE_INV);
4619         /* PI is 8 bit */
4620         pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF;
4621         WREG32(mmSTLB_CACHE_INV,
4622                         (inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi);
4623
4624         rc = hl_poll_timeout(
4625                 hdev,
4626                 mmSTLB_INV_CONSUMER_INDEX,
4627                 status,
4628                 status == pi,
4629                 1000,
4630                 timeout_usec);
4631
4632         mutex_unlock(&hdev->mmu_cache_lock);
4633
4634         if (rc)
4635                 dev_notice_ratelimited(hdev->dev,
4636                         "Timeout when waiting for MMU cache invalidation\n");
4637 }
4638
4639 int goya_send_heartbeat(struct hl_device *hdev)
4640 {
4641         struct goya_device *goya = hdev->asic_specific;
4642
4643         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
4644                 return 0;
4645
4646         return hl_fw_send_heartbeat(hdev);
4647 }
4648
4649 int goya_armcp_info_get(struct hl_device *hdev)
4650 {
4651         struct goya_device *goya = hdev->asic_specific;
4652         struct asic_fixed_properties *prop = &hdev->asic_prop;
4653         u64 dram_size;
4654         int rc;
4655
4656         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
4657                 return 0;
4658
4659         rc = hl_fw_armcp_info_get(hdev);
4660         if (rc)
4661                 return rc;
4662
4663         dram_size = le64_to_cpu(prop->armcp_info.dram_size);
4664         if (dram_size) {
4665                 if ((!is_power_of_2(dram_size)) ||
4666                                 (dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
4667                         dev_err(hdev->dev,
4668                                 "F/W reported invalid DRAM size %llu. Trying to use default size\n",
4669                                 dram_size);
4670                         dram_size = DRAM_PHYS_DEFAULT_SIZE;
4671                 }
4672
4673                 prop->dram_size = dram_size;
4674                 prop->dram_end_address = prop->dram_base_address + dram_size;
4675         }
4676
4677         return 0;
4678 }
4679
4680 static bool goya_is_device_idle(struct hl_device *hdev, char *buf, size_t size)
4681 {
4682         u64 offset, dma_qm_reg, tpc_qm_reg, tpc_cmdq_reg, tpc_cfg_reg;
4683         int i;
4684
4685         offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
4686
4687         for (i = 0 ; i < DMA_MAX_NUM ; i++) {
4688                 dma_qm_reg = mmDMA_QM_0_GLBL_STS0 + i * offset;
4689
4690                 if ((RREG32(dma_qm_reg) & DMA_QM_IDLE_MASK) !=
4691                                 DMA_QM_IDLE_MASK)
4692                         return HL_ENG_BUSY(buf, size, "DMA%d_QM", i);
4693         }
4694
4695         offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
4696
4697         for (i = 0 ; i < TPC_MAX_NUM ; i++) {
4698                 tpc_qm_reg = mmTPC0_QM_GLBL_STS0 + i * offset;
4699                 tpc_cmdq_reg = mmTPC0_CMDQ_GLBL_STS0 + i * offset;
4700                 tpc_cfg_reg = mmTPC0_CFG_STATUS + i * offset;
4701
4702                 if ((RREG32(tpc_qm_reg) & TPC_QM_IDLE_MASK) !=
4703                                 TPC_QM_IDLE_MASK)
4704                         return HL_ENG_BUSY(buf, size, "TPC%d_QM", i);
4705
4706                 if ((RREG32(tpc_cmdq_reg) & TPC_CMDQ_IDLE_MASK) !=
4707                                 TPC_CMDQ_IDLE_MASK)
4708                         return HL_ENG_BUSY(buf, size, "TPC%d_CMDQ", i);
4709
4710                 if ((RREG32(tpc_cfg_reg) & TPC_CFG_IDLE_MASK) !=
4711                                 TPC_CFG_IDLE_MASK)
4712                         return HL_ENG_BUSY(buf, size, "TPC%d_CFG", i);
4713         }
4714
4715         if ((RREG32(mmMME_QM_GLBL_STS0) & MME_QM_IDLE_MASK) !=
4716                         MME_QM_IDLE_MASK)
4717                 return HL_ENG_BUSY(buf, size, "MME_QM");
4718
4719         if ((RREG32(mmMME_CMDQ_GLBL_STS0) & MME_CMDQ_IDLE_MASK) !=
4720                         MME_CMDQ_IDLE_MASK)
4721                 return HL_ENG_BUSY(buf, size, "MME_CMDQ");
4722
4723         if ((RREG32(mmMME_ARCH_STATUS) & MME_ARCH_IDLE_MASK) !=
4724                         MME_ARCH_IDLE_MASK)
4725                 return HL_ENG_BUSY(buf, size, "MME_ARCH");
4726
4727         if (RREG32(mmMME_SHADOW_0_STATUS) & MME_SHADOW_IDLE_MASK)
4728                 return HL_ENG_BUSY(buf, size, "MME");
4729
4730         return true;
4731 }
4732
4733 static void goya_hw_queues_lock(struct hl_device *hdev)
4734 {
4735         struct goya_device *goya = hdev->asic_specific;
4736
4737         spin_lock(&goya->hw_queues_lock);
4738 }
4739
4740 static void goya_hw_queues_unlock(struct hl_device *hdev)
4741 {
4742         struct goya_device *goya = hdev->asic_specific;
4743
4744         spin_unlock(&goya->hw_queues_lock);
4745 }
4746
4747 static u32 goya_get_pci_id(struct hl_device *hdev)
4748 {
4749         return hdev->pdev->device;
4750 }
4751
4752 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
4753                                 size_t max_size)
4754 {
4755         struct goya_device *goya = hdev->asic_specific;
4756
4757         if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
4758                 return 0;
4759
4760         return hl_fw_get_eeprom_data(hdev, data, max_size);
4761 }
4762
4763 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
4764 {
4765         return RREG32(mmPSOC_GLOBAL_CONF_APP_STATUS);
4766 }
4767
4768 static const struct hl_asic_funcs goya_funcs = {
4769         .early_init = goya_early_init,
4770         .early_fini = goya_early_fini,
4771         .late_init = goya_late_init,
4772         .late_fini = goya_late_fini,
4773         .sw_init = goya_sw_init,
4774         .sw_fini = goya_sw_fini,
4775         .hw_init = goya_hw_init,
4776         .hw_fini = goya_hw_fini,
4777         .halt_engines = goya_halt_engines,
4778         .suspend = goya_suspend,
4779         .resume = goya_resume,
4780         .cb_mmap = goya_cb_mmap,
4781         .ring_doorbell = goya_ring_doorbell,
4782         .flush_pq_write = goya_flush_pq_write,
4783         .dma_alloc_coherent = goya_dma_alloc_coherent,
4784         .dma_free_coherent = goya_dma_free_coherent,
4785         .get_int_queue_base = goya_get_int_queue_base,
4786         .test_queues = goya_test_queues,
4787         .dma_pool_zalloc = goya_dma_pool_zalloc,
4788         .dma_pool_free = goya_dma_pool_free,
4789         .cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
4790         .cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
4791         .hl_dma_unmap_sg = goya_dma_unmap_sg,
4792         .cs_parser = goya_cs_parser,
4793         .asic_dma_map_sg = goya_dma_map_sg,
4794         .get_dma_desc_list_size = goya_get_dma_desc_list_size,
4795         .add_end_of_cb_packets = goya_add_end_of_cb_packets,
4796         .update_eq_ci = goya_update_eq_ci,
4797         .context_switch = goya_context_switch,
4798         .restore_phase_topology = goya_restore_phase_topology,
4799         .debugfs_read32 = goya_debugfs_read32,
4800         .debugfs_write32 = goya_debugfs_write32,
4801         .add_device_attr = goya_add_device_attr,
4802         .handle_eqe = goya_handle_eqe,
4803         .set_pll_profile = goya_set_pll_profile,
4804         .get_events_stat = goya_get_events_stat,
4805         .read_pte = goya_read_pte,
4806         .write_pte = goya_write_pte,
4807         .mmu_invalidate_cache = goya_mmu_invalidate_cache,
4808         .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
4809         .send_heartbeat = goya_send_heartbeat,
4810         .debug_coresight = goya_debug_coresight,
4811         .is_device_idle = goya_is_device_idle,
4812         .soft_reset_late_init = goya_soft_reset_late_init,
4813         .hw_queues_lock = goya_hw_queues_lock,
4814         .hw_queues_unlock = goya_hw_queues_unlock,
4815         .get_pci_id = goya_get_pci_id,
4816         .get_eeprom_data = goya_get_eeprom_data,
4817         .send_cpu_message = goya_send_cpu_message,
4818         .get_hw_state = goya_get_hw_state,
4819         .pci_bars_map = goya_pci_bars_map,
4820         .set_dram_bar_base = goya_set_ddr_bar_base,
4821         .init_iatu = goya_init_iatu,
4822         .rreg = hl_rreg,
4823         .wreg = hl_wreg
4824 };
4825
4826 /*
4827  * goya_set_asic_funcs - set Goya function pointers
4828  *
4829  * @*hdev: pointer to hl_device structure
4830  *
4831  */
4832 void goya_set_asic_funcs(struct hl_device *hdev)
4833 {
4834         hdev->asic_funcs = &goya_funcs;
4835 }