drivers/misc/habanalabs/goya/goyaP.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2019 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef GOYAP_H_
   9 #define GOYAP_H_
  10
  11 #include <uapi/misc/habanalabs.h>
  12 #include "habanalabs.h"
  13 #include "include/hl_boot_if.h"
  14 #include "include/goya/goya_packets.h"
  15 #include "include/goya/goya.h"
  16 #include "include/goya/goya_async_events.h"
  17 #include "include/goya/goya_fw_if.h"
  18
  19 #define NUMBER_OF_CMPLT_QUEUES          5
  20 #define NUMBER_OF_EXT_HW_QUEUES         5
  21 #define NUMBER_OF_CPU_HW_QUEUES         1
  22 #define NUMBER_OF_INT_HW_QUEUES         9
  23 #define NUMBER_OF_HW_QUEUES             (NUMBER_OF_EXT_HW_QUEUES + \
  24                                         NUMBER_OF_CPU_HW_QUEUES + \
  25                                         NUMBER_OF_INT_HW_QUEUES)
  26
  27 /*
  28  * Number of MSIX interrupts IDS:
  29  * Each completion queue has 1 ID
  30  * The event queue has 1 ID
  31  */
  32 #define NUMBER_OF_INTERRUPTS            (NUMBER_OF_CMPLT_QUEUES + 1)
  33
  34 #if (NUMBER_OF_HW_QUEUES >= HL_MAX_QUEUES)
  35 #error "Number of H/W queues must be smaller than HL_MAX_QUEUES"
  36 #endif
  37
  38 #if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
  39 #error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
  40 #endif
  41
  42 #define QMAN_FENCE_TIMEOUT_USEC         10000   /* 10 ms */
  43
  44 #define QMAN_STOP_TIMEOUT_USEC          100000  /* 100 ms */
  45
  46 #define TPC_ENABLED_MASK                0xFF
  47
  48 #define PLL_HIGH_DEFAULT                1575000000      /* 1.575 GHz */
  49
  50 #define GOYA_ARMCP_INFO_TIMEOUT         10000000        /* 10s */
  51
  52 #define DRAM_PHYS_DEFAULT_SIZE          0x100000000ull  /* 4GB */
  53
  54 /* DRAM Memory Map */
  55
  56 #define CPU_FW_IMAGE_SIZE       0x10000000      /* 256MB */
  57 #define MMU_PAGE_TABLES_SIZE    0x0E000000      /* 224MB */
  58 #define MMU_CACHE_MNG_SIZE      0x00001000      /* 4KB */
  59 #define CPU_PQ_PKT_SIZE         0x00001000      /* 4KB */
  60 #define CPU_PQ_DATA_SIZE        0x01FFE000      /* 32MB - 8KB  */
  61
  62 #define CPU_FW_IMAGE_ADDR       DRAM_PHYS_BASE
  63 #define MMU_PAGE_TABLES_ADDR    (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
  64 #define MMU_CACHE_MNG_ADDR      (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE)
  65 #define CPU_PQ_PKT_ADDR         (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE)
  66 #define CPU_PQ_DATA_ADDR        (CPU_PQ_PKT_ADDR + CPU_PQ_PKT_SIZE)
  67 #define DRAM_BASE_ADDR_USER     (CPU_PQ_DATA_ADDR + CPU_PQ_DATA_SIZE)
  68
  69 #if (DRAM_BASE_ADDR_USER != 0x20000000)
  70 #error "KMD must reserve 512MB"
  71 #endif
  72
  73 /*
  74  * SRAM Memory Map for KMD
  75  *
  76  * KMD occupies KMD_SRAM_SIZE bytes from the start of SRAM. It is used for
  77  * MME/TPC QMANs
  78  *
  79  */
  80
  81 #define MME_QMAN_BASE_OFFSET    0x000000        /* Must be 0 */
  82 #define MME_QMAN_LENGTH         64
  83 #define TPC_QMAN_LENGTH         64
  84
  85 #define TPC0_QMAN_BASE_OFFSET   (MME_QMAN_BASE_OFFSET + \
  86                                 (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
  87 #define TPC1_QMAN_BASE_OFFSET   (TPC0_QMAN_BASE_OFFSET + \
  88                                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
  89 #define TPC2_QMAN_BASE_OFFSET   (TPC1_QMAN_BASE_OFFSET + \
  90                                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
  91 #define TPC3_QMAN_BASE_OFFSET   (TPC2_QMAN_BASE_OFFSET + \
  92                                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
  93 #define TPC4_QMAN_BASE_OFFSET   (TPC3_QMAN_BASE_OFFSET + \
  94                                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
  95 #define TPC5_QMAN_BASE_OFFSET   (TPC4_QMAN_BASE_OFFSET + \
  96                                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
  97 #define TPC6_QMAN_BASE_OFFSET   (TPC5_QMAN_BASE_OFFSET + \
  98                                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
  99 #define TPC7_QMAN_BASE_OFFSET   (TPC6_QMAN_BASE_OFFSET + \
 100                                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
 101
 102 #define SRAM_KMD_RES_OFFSET     (TPC7_QMAN_BASE_OFFSET + \
 103                                 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
 104
 105 #if (SRAM_KMD_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
 106 #error "MME/TPC QMANs SRAM space exceeds limit"
 107 #endif
 108
 109 #define SRAM_USER_BASE_OFFSET   GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
 110
 111 /* Virtual address space */
 112 #define VA_HOST_SPACE_START     0x1000000000000ull      /* 256TB */
 113 #define VA_HOST_SPACE_END       0x3FF8000000000ull      /* 1PB - 1TB */
 114 #define VA_HOST_SPACE_SIZE      (VA_HOST_SPACE_END - \
 115                                         VA_HOST_SPACE_START) /* 767TB */
 116
 117 #define VA_DDR_SPACE_START      0x800000000ull          /* 32GB */
 118 #define VA_DDR_SPACE_END        0x2000000000ull         /* 128GB */
 119 #define VA_DDR_SPACE_SIZE       (VA_DDR_SPACE_END - \
 120                                         VA_DDR_SPACE_START)     /* 128GB */
 121
 122 #define DMA_MAX_TRANSFER_SIZE   0xFFFFFFFF
 123
 124 #define HW_CAP_PLL              0x00000001
 125 #define HW_CAP_DDR_0            0x00000002
 126 #define HW_CAP_DDR_1            0x00000004
 127 #define HW_CAP_MME              0x00000008
 128 #define HW_CAP_CPU              0x00000010
 129 #define HW_CAP_DMA              0x00000020
 130 #define HW_CAP_MSIX             0x00000040
 131 #define HW_CAP_CPU_Q            0x00000080
 132 #define HW_CAP_MMU              0x00000100
 133 #define HW_CAP_TPC_MBIST        0x00000200
 134 #define HW_CAP_GOLDEN           0x00000400
 135 #define HW_CAP_TPC              0x00000800
 136
 137 #define CPU_PKT_SHIFT           5
 138 #define CPU_PKT_SIZE            (1 << CPU_PKT_SHIFT)
 139 #define CPU_PKT_MASK            (~((1 << CPU_PKT_SHIFT) - 1))
 140 #define CPU_MAX_PKTS_IN_CB      32
 141 #define CPU_CB_SIZE             (CPU_PKT_SIZE * CPU_MAX_PKTS_IN_CB)
 142 #define CPU_ACCESSIBLE_MEM_SIZE (HL_QUEUE_LENGTH * CPU_CB_SIZE)
 143
 144 enum goya_fw_component {
 145         FW_COMP_UBOOT,
 146         FW_COMP_PREBOOT
 147 };
 148
 149 struct goya_device {
 150         int (*test_cpu_queue)(struct hl_device *hdev);
 151
 152         /* TODO: remove hw_queues_lock after moving to scheduler code */
 153         spinlock_t      hw_queues_lock;
 154         u64             ddr_bar_cur_addr;
 155         u32             events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
 156         u32             hw_cap_initialized;
 157 };
 158
 159 int goya_test_cpu_queue(struct hl_device *hdev);
 160 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
 161                                 u32 timeout, long *result);
 162 void goya_init_security(struct hl_device *hdev);
 163
 164 #endif /* GOYAP_H_ */