1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2019 HabanaLabs, Ltd.
11 #define pr_fmt(fmt) "habanalabs: " fmt
13 #include <linux/cdev.h>
15 #define HL_NAME "habanalabs"
17 #define HL_MAX_QUEUES 128
23 * struct asic_fixed_properties - ASIC specific immutable properties.
24 * @sram_base_address: SRAM physical start address.
25 * @sram_end_address: SRAM physical end address.
26 * @sram_user_base_address - SRAM physical start address for user access.
27 * @dram_base_address: DRAM physical start address.
28 * @dram_end_address: DRAM physical end address.
29 * @dram_user_base_address: DRAM physical start address for user access.
30 * @dram_size: DRAM total size.
31 * @dram_pci_bar_size: size of PCI bar towards DRAM.
32 * @host_phys_base_address: base physical address of host memory for
33 * transactions that the device generates.
34 * @va_space_host_start_address: base address of virtual memory range for
35 * mapping host memory.
36 * @va_space_host_end_address: end address of virtual memory range for
37 * mapping host memory.
38 * @va_space_dram_start_address: base address of virtual memory range for
39 * mapping DRAM memory.
40 * @va_space_dram_end_address: end address of virtual memory range for
41 * mapping DRAM memory.
42 * @cfg_size: configuration space size on SRAM.
43 * @sram_size: total size of SRAM.
44 * @max_asid: maximum number of open contexts (ASIDs).
45 * @completion_queues_count: number of completion queues.
46 * @high_pll: high PLL frequency used by the device.
47 * @tpc_enabled_mask: which TPCs are enabled.
49 struct asic_fixed_properties {
50 u64 sram_base_address;
52 u64 sram_user_base_address;
53 u64 dram_base_address;
55 u64 dram_user_base_address;
57 u64 dram_pci_bar_size;
58 u64 host_phys_base_address;
59 u64 va_space_host_start_address;
60 u64 va_space_host_end_address;
61 u64 va_space_dram_start_address;
62 u64 va_space_dram_end_address;
67 u8 completion_queues_count;
72 #define HL_QUEUE_LENGTH 256
78 * enum hl_asic_type - supported ASIC types.
79 * @ASIC_AUTO_DETECT: ASIC type will be automatically set.
80 * @ASIC_GOYA: Goya device.
81 * @ASIC_INVALID: Invalid ASIC type.
90 * struct hl_asic_funcs - ASIC specific functions that are can be called from
92 * @early_init: sets up early driver state (pre sw_init), doesn't configure H/W.
93 * @early_fini: tears down what was done in early_init.
94 * @sw_init: sets up driver state, does not configure H/W.
95 * @sw_fini: tears down driver state, does not configure H/W.
96 * @suspend: handles IP specific H/W or SW changes for suspend.
97 * @resume: handles IP specific H/W or SW changes for resume.
98 * @dma_alloc_coherent: Allocate coherent DMA memory by calling
99 * dma_alloc_coherent(). This is ASIC function because its
100 * implementation is not trivial when the driver is loaded
101 * in simulation mode (not upstreamed).
102 * @dma_free_coherent: Free coherent DMA memory by calling dma_free_coherent().
103 * This is ASIC function because its implementation is not
104 * trivial when the driver is loaded in simulation mode
107 struct hl_asic_funcs {
108 int (*early_init)(struct hl_device *hdev);
109 int (*early_fini)(struct hl_device *hdev);
110 int (*sw_init)(struct hl_device *hdev);
111 int (*sw_fini)(struct hl_device *hdev);
112 int (*suspend)(struct hl_device *hdev);
113 int (*resume)(struct hl_device *hdev);
114 void* (*dma_alloc_coherent)(struct hl_device *hdev, size_t size,
115 dma_addr_t *dma_handle, gfp_t flag);
116 void (*dma_free_coherent)(struct hl_device *hdev, size_t size,
117 void *cpu_addr, dma_addr_t dma_handle);
121 * FILE PRIVATE STRUCTURE
125 * struct hl_fpriv - process information stored in FD private data.
126 * @hdev: habanalabs device structure.
127 * @filp: pointer to the given file structure.
128 * @taskpid: current process ID.
129 * @refcount: number of related contexts.
132 struct hl_device *hdev;
135 struct kref refcount;
143 /* Theoretical limit only. A single host can only contain up to 4 or 8 PCIe
144 * x16 cards. In extereme cases, there are hosts that can accommodate 16 cards
146 #define HL_MAX_MINORS 256
149 * Registers read & write functions.
152 u32 hl_rreg(struct hl_device *hdev, u32 reg);
153 void hl_wreg(struct hl_device *hdev, u32 reg, u32 val);
155 #define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \
156 readl_poll_timeout(hdev->rmmio + addr, val, cond, sleep_us, timeout_us)
158 #define RREG32(reg) hl_rreg(hdev, (reg))
159 #define WREG32(reg, v) hl_wreg(hdev, (reg), (v))
160 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
161 hl_rreg(hdev, (reg)))
163 #define WREG32_P(reg, val, mask) \
165 u32 tmp_ = RREG32(reg); \
167 tmp_ |= ((val) & ~(mask)); \
170 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
171 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
173 #define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT
174 #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK
175 #define WREG32_FIELD(reg, field, val) \
176 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \
177 (val) << REG_FIELD_SHIFT(reg, field))
180 * struct hl_device - habanalabs device structure.
181 * @pdev: pointer to PCI device, can be NULL in case of simulator device.
182 * @pcie_bar: array of available PCIe bars.
183 * @rmmio: configuration area address on SRAM.
184 * @cdev: related char device.
185 * @dev: realted kernel basic device structure.
186 * @asic_name: ASIC specific nmae.
187 * @asic_type: ASIC specific type.
188 * @dma_pool: DMA pool for small allocations.
189 * @cpu_accessible_dma_mem: KMD <-> ArmCP shared memory CPU address.
190 * @cpu_accessible_dma_address: KMD <-> ArmCP shared memory DMA address.
191 * @cpu_accessible_dma_pool: KMD <-> ArmCP shared memory pool.
192 * @asic_prop: ASIC specific immutable properties.
193 * @asic_funcs: ASIC specific functions.
194 * @asic_specific: ASIC specific information to use only from ASIC files.
195 * @major: habanalabs KMD major.
197 * @disabled: is device disabled.
200 struct pci_dev *pdev;
201 void __iomem *pcie_bar[6];
206 enum hl_asic_type asic_type;
207 struct dma_pool *dma_pool;
208 void *cpu_accessible_dma_mem;
209 dma_addr_t cpu_accessible_dma_address;
210 struct gen_pool *cpu_accessible_dma_pool;
211 struct asic_fixed_properties asic_prop;
212 const struct hl_asic_funcs *asic_funcs;
218 /* Parameters for bring-up */
228 * typedef hl_ioctl_t - typedef for ioctl function in the driver
229 * @hpriv: pointer to the FD's private data, which contains state of
231 * @data: pointer to the input/output arguments structure of the IOCTL
233 * Return: 0 for success, negative value for error
235 typedef int hl_ioctl_t(struct hl_fpriv *hpriv, void *data);
238 * struct hl_ioctl_desc - describes an IOCTL entry of the driver.
239 * @cmd: the IOCTL code as created by the kernel macros.
240 * @func: pointer to the driver's function that should be called for this IOCTL.
242 struct hl_ioctl_desc {
249 * Kernel module functions that can be accessed by entire module
252 int hl_device_open(struct inode *inode, struct file *filp);
253 int create_hdev(struct hl_device **dev, struct pci_dev *pdev,
254 enum hl_asic_type asic_type, int minor);
255 void destroy_hdev(struct hl_device *hdev);
256 int hl_poll_timeout_memory(struct hl_device *hdev, u64 addr, u32 timeout_us,
258 int hl_poll_timeout_device_memory(struct hl_device *hdev, void __iomem *addr,
259 u32 timeout_us, u32 *val);
261 int hl_device_init(struct hl_device *hdev, struct class *hclass);
262 void hl_device_fini(struct hl_device *hdev);
263 int hl_device_suspend(struct hl_device *hdev);
264 int hl_device_resume(struct hl_device *hdev);
266 void goya_set_asic_funcs(struct hl_device *hdev);
268 #endif /* HABANALABSP_H_ */