1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2018 HabanaLabs, Ltd.
8 /************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
13 #ifndef ASIC_REG_DMA_QM_0_REGS_H_
14 #define ASIC_REG_DMA_QM_0_REGS_H_
17 *****************************************
18 * DMA_QM_0 (Prototype: QMAN)
19 *****************************************
22 #define mmDMA_QM_0_GLBL_CFG0 0x400000
24 #define mmDMA_QM_0_GLBL_CFG1 0x400004
26 #define mmDMA_QM_0_GLBL_PROT 0x400008
28 #define mmDMA_QM_0_GLBL_ERR_CFG 0x40000C
30 #define mmDMA_QM_0_GLBL_ERR_ADDR_LO 0x400010
32 #define mmDMA_QM_0_GLBL_ERR_ADDR_HI 0x400014
34 #define mmDMA_QM_0_GLBL_ERR_WDATA 0x400018
36 #define mmDMA_QM_0_GLBL_SECURE_PROPS 0x40001C
38 #define mmDMA_QM_0_GLBL_NON_SECURE_PROPS 0x400020
40 #define mmDMA_QM_0_GLBL_STS0 0x400024
42 #define mmDMA_QM_0_GLBL_STS1 0x400028
44 #define mmDMA_QM_0_PQ_BASE_LO 0x400060
46 #define mmDMA_QM_0_PQ_BASE_HI 0x400064
48 #define mmDMA_QM_0_PQ_SIZE 0x400068
50 #define mmDMA_QM_0_PQ_PI 0x40006C
52 #define mmDMA_QM_0_PQ_CI 0x400070
54 #define mmDMA_QM_0_PQ_CFG0 0x400074
56 #define mmDMA_QM_0_PQ_CFG1 0x400078
58 #define mmDMA_QM_0_PQ_ARUSER 0x40007C
60 #define mmDMA_QM_0_PQ_PUSH0 0x400080
62 #define mmDMA_QM_0_PQ_PUSH1 0x400084
64 #define mmDMA_QM_0_PQ_PUSH2 0x400088
66 #define mmDMA_QM_0_PQ_PUSH3 0x40008C
68 #define mmDMA_QM_0_PQ_STS0 0x400090
70 #define mmDMA_QM_0_PQ_STS1 0x400094
72 #define mmDMA_QM_0_PQ_RD_RATE_LIM_EN 0x4000A0
74 #define mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN 0x4000A4
76 #define mmDMA_QM_0_PQ_RD_RATE_LIM_SAT 0x4000A8
78 #define mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT 0x4000AC
80 #define mmDMA_QM_0_CQ_CFG0 0x4000B0
82 #define mmDMA_QM_0_CQ_CFG1 0x4000B4
84 #define mmDMA_QM_0_CQ_ARUSER 0x4000B8
86 #define mmDMA_QM_0_CQ_PTR_LO 0x4000C0
88 #define mmDMA_QM_0_CQ_PTR_HI 0x4000C4
90 #define mmDMA_QM_0_CQ_TSIZE 0x4000C8
92 #define mmDMA_QM_0_CQ_CTL 0x4000CC
94 #define mmDMA_QM_0_CQ_PTR_LO_STS 0x4000D4
96 #define mmDMA_QM_0_CQ_PTR_HI_STS 0x4000D8
98 #define mmDMA_QM_0_CQ_TSIZE_STS 0x4000DC
100 #define mmDMA_QM_0_CQ_CTL_STS 0x4000E0
102 #define mmDMA_QM_0_CQ_STS0 0x4000E4
104 #define mmDMA_QM_0_CQ_STS1 0x4000E8
106 #define mmDMA_QM_0_CQ_RD_RATE_LIM_EN 0x4000F0
108 #define mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN 0x4000F4
110 #define mmDMA_QM_0_CQ_RD_RATE_LIM_SAT 0x4000F8
112 #define mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT 0x4000FC
114 #define mmDMA_QM_0_CQ_IFIFO_CNT 0x400108
116 #define mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO 0x400120
118 #define mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI 0x400124
120 #define mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO 0x400128
122 #define mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI 0x40012C
124 #define mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO 0x400130
126 #define mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI 0x400134
128 #define mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO 0x400138
130 #define mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI 0x40013C
132 #define mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET 0x400140
134 #define mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET 0x400144
136 #define mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET 0x400148
138 #define mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET 0x40014C
140 #define mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET 0x400150
142 #define mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET 0x400154
144 #define mmDMA_QM_0_CP_FENCE0_RDATA 0x400158
146 #define mmDMA_QM_0_CP_FENCE1_RDATA 0x40015C
148 #define mmDMA_QM_0_CP_FENCE2_RDATA 0x400160
150 #define mmDMA_QM_0_CP_FENCE3_RDATA 0x400164
152 #define mmDMA_QM_0_CP_FENCE0_CNT 0x400168
154 #define mmDMA_QM_0_CP_FENCE1_CNT 0x40016C
156 #define mmDMA_QM_0_CP_FENCE2_CNT 0x400170
158 #define mmDMA_QM_0_CP_FENCE3_CNT 0x400174
160 #define mmDMA_QM_0_CP_STS 0x400178
162 #define mmDMA_QM_0_CP_CURRENT_INST_LO 0x40017C
164 #define mmDMA_QM_0_CP_CURRENT_INST_HI 0x400180
166 #define mmDMA_QM_0_CP_BARRIER_CFG 0x400184
168 #define mmDMA_QM_0_CP_DBG_0 0x400188
170 #define mmDMA_QM_0_PQ_BUF_ADDR 0x400300
172 #define mmDMA_QM_0_PQ_BUF_RDATA 0x400304
174 #define mmDMA_QM_0_CQ_BUF_ADDR 0x400308
176 #define mmDMA_QM_0_CQ_BUF_RDATA 0x40030C
178 #endif /* ASIC_REG_DMA_QM_0_REGS_H_ */