1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2003-2018, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
9 #include <linux/kthread.h>
10 #include <linux/interrupt.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/sizes.h>
18 #include "hw-me-regs.h"
20 #include "mei-trace.h"
23 * mei_me_reg_read - Reads 32bit data from the mei device
25 * @hw: the me hardware structure
26 * @offset: offset from which to read the data
28 * Return: register value (u32)
30 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
33 return ioread32(hw->mem_addr + offset);
38 * mei_me_reg_write - Writes 32bit data to the mei device
40 * @hw: the me hardware structure
41 * @offset: offset from which to write the data
42 * @value: register value to write (u32)
44 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
45 unsigned long offset, u32 value)
47 iowrite32(value, hw->mem_addr + offset);
51 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
52 * read window register
54 * @dev: the device structure
56 * Return: ME_CB_RW register value (u32)
58 static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
60 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
64 * mei_me_hcbww_write - write 32bit data to the host circular buffer
66 * @dev: the device structure
67 * @data: 32bit data to be written to the host circular buffer
69 static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
71 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
75 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
77 * @dev: the device structure
79 * Return: ME_CSR_HA register value (u32)
81 static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
85 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
86 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);
92 * mei_hcsr_read - Reads 32bit data from the host CSR
94 * @dev: the device structure
96 * Return: H_CSR register value (u32)
98 static inline u32 mei_hcsr_read(const struct mei_device *dev)
102 reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
103 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);
109 * mei_hcsr_write - writes H_CSR register to the mei device
111 * @dev: the device structure
112 * @reg: new register value
114 static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
116 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);
117 mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
121 * mei_hcsr_set - writes H_CSR register to the mei device,
122 * and ignores the H_IS bit for it is write-one-to-zero.
124 * @dev: the device structure
125 * @reg: new register value
127 static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
129 reg &= ~H_CSR_IS_MASK;
130 mei_hcsr_write(dev, reg);
134 * mei_hcsr_set_hig - set host interrupt (set H_IG)
136 * @dev: the device structure
138 static inline void mei_hcsr_set_hig(struct mei_device *dev)
142 hcsr = mei_hcsr_read(dev) | H_IG;
143 mei_hcsr_set(dev, hcsr);
147 * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register
149 * @dev: the device structure
151 * Return: H_D0I3C register value (u32)
153 static inline u32 mei_me_d0i3c_read(const struct mei_device *dev)
157 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C);
158 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg);
164 * mei_me_d0i3c_write - writes H_D0I3C register to device
166 * @dev: the device structure
167 * @reg: new register value
169 static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg)
171 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg);
172 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg);
176 * mei_me_fw_status - read fw status register from pci config space
179 * @fw_status: fw status register values
181 * Return: 0 on success, error otherwise
183 static int mei_me_fw_status(struct mei_device *dev,
184 struct mei_fw_status *fw_status)
186 struct pci_dev *pdev = to_pci_dev(dev->dev);
187 struct mei_me_hw *hw = to_me_hw(dev);
188 const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
195 fw_status->count = fw_src->count;
196 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
197 ret = pci_read_config_dword(pdev, fw_src->status[i],
198 &fw_status->status[i]);
199 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
201 fw_status->status[i]);
210 * mei_me_hw_config - configure hw dependent settings
214 static void mei_me_hw_config(struct mei_device *dev)
216 struct pci_dev *pdev = to_pci_dev(dev->dev);
217 struct mei_me_hw *hw = to_me_hw(dev);
220 /* Doesn't change in runtime */
221 hcsr = mei_hcsr_read(dev);
222 hw->hbuf_depth = (hcsr & H_CBD) >> 24;
225 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
226 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
228 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
230 hw->pg_state = MEI_PG_OFF;
231 if (hw->d0i3_supported) {
232 reg = mei_me_d0i3c_read(dev);
233 if (reg & H_D0I3C_I3)
234 hw->pg_state = MEI_PG_ON;
239 * mei_me_pg_state - translate internal pg state
240 * to the mei power gating state
244 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
246 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
248 struct mei_me_hw *hw = to_me_hw(dev);
253 static inline u32 me_intr_src(u32 hcsr)
255 return hcsr & H_CSR_IS_MASK;
259 * me_intr_disable - disables mei device interrupts
260 * using supplied hcsr register value.
262 * @dev: the device structure
263 * @hcsr: supplied hcsr register value
265 static inline void me_intr_disable(struct mei_device *dev, u32 hcsr)
267 hcsr &= ~H_CSR_IE_MASK;
268 mei_hcsr_set(dev, hcsr);
272 * mei_me_intr_clear - clear and stop interrupts
274 * @dev: the device structure
275 * @hcsr: supplied hcsr register value
277 static inline void me_intr_clear(struct mei_device *dev, u32 hcsr)
279 if (me_intr_src(hcsr))
280 mei_hcsr_write(dev, hcsr);
284 * mei_me_intr_clear - clear and stop interrupts
286 * @dev: the device structure
288 static void mei_me_intr_clear(struct mei_device *dev)
290 u32 hcsr = mei_hcsr_read(dev);
292 me_intr_clear(dev, hcsr);
295 * mei_me_intr_enable - enables mei device interrupts
297 * @dev: the device structure
299 static void mei_me_intr_enable(struct mei_device *dev)
301 u32 hcsr = mei_hcsr_read(dev);
303 hcsr |= H_CSR_IE_MASK;
304 mei_hcsr_set(dev, hcsr);
308 * mei_me_intr_disable - disables mei device interrupts
310 * @dev: the device structure
312 static void mei_me_intr_disable(struct mei_device *dev)
314 u32 hcsr = mei_hcsr_read(dev);
316 me_intr_disable(dev, hcsr);
320 * mei_me_synchronize_irq - wait for pending IRQ handlers
322 * @dev: the device structure
324 static void mei_me_synchronize_irq(struct mei_device *dev)
326 struct pci_dev *pdev = to_pci_dev(dev->dev);
328 synchronize_irq(pdev->irq);
332 * mei_me_hw_reset_release - release device from the reset
334 * @dev: the device structure
336 static void mei_me_hw_reset_release(struct mei_device *dev)
338 u32 hcsr = mei_hcsr_read(dev);
342 mei_hcsr_set(dev, hcsr);
346 * mei_me_host_set_ready - enable device
350 static void mei_me_host_set_ready(struct mei_device *dev)
352 u32 hcsr = mei_hcsr_read(dev);
354 hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
355 mei_hcsr_set(dev, hcsr);
359 * mei_me_host_is_ready - check whether the host has turned ready
364 static bool mei_me_host_is_ready(struct mei_device *dev)
366 u32 hcsr = mei_hcsr_read(dev);
368 return (hcsr & H_RDY) == H_RDY;
372 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
377 static bool mei_me_hw_is_ready(struct mei_device *dev)
379 u32 mecsr = mei_me_mecsr_read(dev);
381 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
385 * mei_me_hw_is_resetting - check whether the me(hw) is in reset
390 static bool mei_me_hw_is_resetting(struct mei_device *dev)
392 u32 mecsr = mei_me_mecsr_read(dev);
394 return (mecsr & ME_RST_HRA) == ME_RST_HRA;
398 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
399 * or timeout is reached
402 * Return: 0 on success, error otherwise
404 static int mei_me_hw_ready_wait(struct mei_device *dev)
406 mutex_unlock(&dev->device_lock);
407 wait_event_timeout(dev->wait_hw_ready,
409 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
410 mutex_lock(&dev->device_lock);
411 if (!dev->recvd_hw_ready) {
412 dev_err(dev->dev, "wait hw ready failed\n");
416 mei_me_hw_reset_release(dev);
417 dev->recvd_hw_ready = false;
422 * mei_me_hw_start - hw start routine
425 * Return: 0 on success, error otherwise
427 static int mei_me_hw_start(struct mei_device *dev)
429 int ret = mei_me_hw_ready_wait(dev);
433 dev_dbg(dev->dev, "hw is ready\n");
435 mei_me_host_set_ready(dev);
441 * mei_hbuf_filled_slots - gets number of device filled buffer slots
443 * @dev: the device structure
445 * Return: number of filled slots
447 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
450 char read_ptr, write_ptr;
452 hcsr = mei_hcsr_read(dev);
454 read_ptr = (char) ((hcsr & H_CBRP) >> 8);
455 write_ptr = (char) ((hcsr & H_CBWP) >> 16);
457 return (unsigned char) (write_ptr - read_ptr);
461 * mei_me_hbuf_is_empty - checks if host buffer is empty.
463 * @dev: the device structure
465 * Return: true if empty, false - otherwise.
467 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
469 return mei_hbuf_filled_slots(dev) == 0;
473 * mei_me_hbuf_empty_slots - counts write empty slots.
475 * @dev: the device structure
477 * Return: -EOVERFLOW if overflow, otherwise empty slots count
479 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
481 struct mei_me_hw *hw = to_me_hw(dev);
482 unsigned char filled_slots, empty_slots;
484 filled_slots = mei_hbuf_filled_slots(dev);
485 empty_slots = hw->hbuf_depth - filled_slots;
487 /* check for overflow */
488 if (filled_slots > hw->hbuf_depth)
495 * mei_me_hbuf_depth - returns depth of the hw buffer.
497 * @dev: the device structure
499 * Return: size of hw buffer in slots
501 static u32 mei_me_hbuf_depth(const struct mei_device *dev)
503 struct mei_me_hw *hw = to_me_hw(dev);
505 return hw->hbuf_depth;
509 * mei_me_hbuf_write - writes a message to host hw buffer.
511 * @dev: the device structure
512 * @hdr: header of message
513 * @hdr_len: header length in bytes: must be multiplication of a slot (4bytes)
515 * @data_len: payload length in bytes
517 * Return: 0 if success, < 0 - otherwise.
519 static int mei_me_hbuf_write(struct mei_device *dev,
520 const void *hdr, size_t hdr_len,
521 const void *data, size_t data_len)
529 if (WARN_ON(!hdr || !data || hdr_len & 0x3))
532 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr));
534 empty_slots = mei_hbuf_empty_slots(dev);
535 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
540 dw_cnt = mei_data2slots(hdr_len + data_len);
541 if (dw_cnt > (u32)empty_slots)
545 for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++)
546 mei_me_hcbww_write(dev, reg_buf[i]);
549 for (i = 0; i < data_len / MEI_SLOT_SIZE; i++)
550 mei_me_hcbww_write(dev, reg_buf[i]);
552 rem = data_len & 0x3;
556 memcpy(®, (const u8 *)data + data_len - rem, rem);
557 mei_me_hcbww_write(dev, reg);
560 mei_hcsr_set_hig(dev);
561 if (!mei_me_hw_is_ready(dev))
568 * mei_me_count_full_read_slots - counts read full slots.
570 * @dev: the device structure
572 * Return: -EOVERFLOW if overflow, otherwise filled slots count
574 static int mei_me_count_full_read_slots(struct mei_device *dev)
577 char read_ptr, write_ptr;
578 unsigned char buffer_depth, filled_slots;
580 me_csr = mei_me_mecsr_read(dev);
581 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
582 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
583 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
584 filled_slots = (unsigned char) (write_ptr - read_ptr);
586 /* check for overflow */
587 if (filled_slots > buffer_depth)
590 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
591 return (int)filled_slots;
595 * mei_me_read_slots - reads a message from mei device.
597 * @dev: the device structure
598 * @buffer: message buffer will be written
599 * @buffer_length: message size will be read
603 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
604 unsigned long buffer_length)
606 u32 *reg_buf = (u32 *)buffer;
608 for (; buffer_length >= MEI_SLOT_SIZE; buffer_length -= MEI_SLOT_SIZE)
609 *reg_buf++ = mei_me_mecbrw_read(dev);
611 if (buffer_length > 0) {
612 u32 reg = mei_me_mecbrw_read(dev);
614 memcpy(reg_buf, ®, buffer_length);
617 mei_hcsr_set_hig(dev);
622 * mei_me_pg_set - write pg enter register
624 * @dev: the device structure
626 static void mei_me_pg_set(struct mei_device *dev)
628 struct mei_me_hw *hw = to_me_hw(dev);
631 reg = mei_me_reg_read(hw, H_HPG_CSR);
632 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
634 reg |= H_HPG_CSR_PGI;
636 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
637 mei_me_reg_write(hw, H_HPG_CSR, reg);
641 * mei_me_pg_unset - write pg exit register
643 * @dev: the device structure
645 static void mei_me_pg_unset(struct mei_device *dev)
647 struct mei_me_hw *hw = to_me_hw(dev);
650 reg = mei_me_reg_read(hw, H_HPG_CSR);
651 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
653 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
655 reg |= H_HPG_CSR_PGIHEXR;
657 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
658 mei_me_reg_write(hw, H_HPG_CSR, reg);
662 * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure
664 * @dev: the device structure
666 * Return: 0 on success an error code otherwise
668 static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
670 struct mei_me_hw *hw = to_me_hw(dev);
671 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
674 dev->pg_event = MEI_PG_EVENT_WAIT;
676 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
680 mutex_unlock(&dev->device_lock);
681 wait_event_timeout(dev->wait_pg,
682 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
683 mutex_lock(&dev->device_lock);
685 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
692 dev->pg_event = MEI_PG_EVENT_IDLE;
693 hw->pg_state = MEI_PG_ON;
699 * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure
701 * @dev: the device structure
703 * Return: 0 on success an error code otherwise
705 static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
707 struct mei_me_hw *hw = to_me_hw(dev);
708 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
711 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
714 dev->pg_event = MEI_PG_EVENT_WAIT;
716 mei_me_pg_unset(dev);
718 mutex_unlock(&dev->device_lock);
719 wait_event_timeout(dev->wait_pg,
720 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
721 mutex_lock(&dev->device_lock);
724 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
729 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
730 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
734 mutex_unlock(&dev->device_lock);
735 wait_event_timeout(dev->wait_pg,
736 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
737 mutex_lock(&dev->device_lock);
739 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
745 dev->pg_event = MEI_PG_EVENT_IDLE;
746 hw->pg_state = MEI_PG_OFF;
752 * mei_me_pg_in_transition - is device now in pg transition
754 * @dev: the device structure
756 * Return: true if in pg transition, false otherwise
758 static bool mei_me_pg_in_transition(struct mei_device *dev)
760 return dev->pg_event >= MEI_PG_EVENT_WAIT &&
761 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
765 * mei_me_pg_is_enabled - detect if PG is supported by HW
767 * @dev: the device structure
769 * Return: true is pg supported, false otherwise
771 static bool mei_me_pg_is_enabled(struct mei_device *dev)
773 struct mei_me_hw *hw = to_me_hw(dev);
774 u32 reg = mei_me_mecsr_read(dev);
776 if (hw->d0i3_supported)
779 if ((reg & ME_PGIC_HRA) == 0)
782 if (!dev->hbm_f_pg_supported)
788 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n",
790 !!(reg & ME_PGIC_HRA),
791 dev->version.major_version,
792 dev->version.minor_version,
793 HBM_MAJOR_VERSION_PGI,
794 HBM_MINOR_VERSION_PGI);
800 * mei_me_d0i3_set - write d0i3 register bit on mei device.
802 * @dev: the device structure
803 * @intr: ask for interrupt
805 * Return: D0I3C register value
807 static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr)
809 u32 reg = mei_me_d0i3c_read(dev);
816 mei_me_d0i3c_write(dev, reg);
817 /* read it to ensure HW consistency */
818 reg = mei_me_d0i3c_read(dev);
823 * mei_me_d0i3_unset - clean d0i3 register bit on mei device.
825 * @dev: the device structure
827 * Return: D0I3C register value
829 static u32 mei_me_d0i3_unset(struct mei_device *dev)
831 u32 reg = mei_me_d0i3c_read(dev);
835 mei_me_d0i3c_write(dev, reg);
836 /* read it to ensure HW consistency */
837 reg = mei_me_d0i3c_read(dev);
842 * mei_me_d0i3_enter_sync - perform d0i3 entry procedure
844 * @dev: the device structure
846 * Return: 0 on success an error code otherwise
848 static int mei_me_d0i3_enter_sync(struct mei_device *dev)
850 struct mei_me_hw *hw = to_me_hw(dev);
851 unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
852 unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
856 reg = mei_me_d0i3c_read(dev);
857 if (reg & H_D0I3C_I3) {
858 /* we are in d0i3, nothing to do */
859 dev_dbg(dev->dev, "d0i3 set not needed\n");
864 /* PGI entry procedure */
865 dev->pg_event = MEI_PG_EVENT_WAIT;
867 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
869 /* FIXME: should we reset here? */
872 mutex_unlock(&dev->device_lock);
873 wait_event_timeout(dev->wait_pg,
874 dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout);
875 mutex_lock(&dev->device_lock);
877 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
881 /* end PGI entry procedure */
883 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
885 reg = mei_me_d0i3_set(dev, true);
886 if (!(reg & H_D0I3C_CIP)) {
887 dev_dbg(dev->dev, "d0i3 enter wait not needed\n");
892 mutex_unlock(&dev->device_lock);
893 wait_event_timeout(dev->wait_pg,
894 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout);
895 mutex_lock(&dev->device_lock);
897 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
898 reg = mei_me_d0i3c_read(dev);
899 if (!(reg & H_D0I3C_I3)) {
907 hw->pg_state = MEI_PG_ON;
909 dev->pg_event = MEI_PG_EVENT_IDLE;
910 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret);
915 * mei_me_d0i3_enter - perform d0i3 entry procedure
916 * no hbm PG handshake
917 * no waiting for confirmation; runs with interrupts
920 * @dev: the device structure
922 * Return: 0 on success an error code otherwise
924 static int mei_me_d0i3_enter(struct mei_device *dev)
926 struct mei_me_hw *hw = to_me_hw(dev);
929 reg = mei_me_d0i3c_read(dev);
930 if (reg & H_D0I3C_I3) {
931 /* we are in d0i3, nothing to do */
932 dev_dbg(dev->dev, "already d0i3 : set not needed\n");
936 mei_me_d0i3_set(dev, false);
938 hw->pg_state = MEI_PG_ON;
939 dev->pg_event = MEI_PG_EVENT_IDLE;
940 dev_dbg(dev->dev, "d0i3 enter\n");
945 * mei_me_d0i3_exit_sync - perform d0i3 exit procedure
947 * @dev: the device structure
949 * Return: 0 on success an error code otherwise
951 static int mei_me_d0i3_exit_sync(struct mei_device *dev)
953 struct mei_me_hw *hw = to_me_hw(dev);
954 unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
958 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
960 reg = mei_me_d0i3c_read(dev);
961 if (!(reg & H_D0I3C_I3)) {
962 /* we are not in d0i3, nothing to do */
963 dev_dbg(dev->dev, "d0i3 exit not needed\n");
968 reg = mei_me_d0i3_unset(dev);
969 if (!(reg & H_D0I3C_CIP)) {
970 dev_dbg(dev->dev, "d0i3 exit wait not needed\n");
975 mutex_unlock(&dev->device_lock);
976 wait_event_timeout(dev->wait_pg,
977 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
978 mutex_lock(&dev->device_lock);
980 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
981 reg = mei_me_d0i3c_read(dev);
982 if (reg & H_D0I3C_I3) {
990 hw->pg_state = MEI_PG_OFF;
992 dev->pg_event = MEI_PG_EVENT_IDLE;
994 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret);
999 * mei_me_pg_legacy_intr - perform legacy pg processing
1000 * in interrupt thread handler
1002 * @dev: the device structure
1004 static void mei_me_pg_legacy_intr(struct mei_device *dev)
1006 struct mei_me_hw *hw = to_me_hw(dev);
1008 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
1011 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1012 hw->pg_state = MEI_PG_OFF;
1013 if (waitqueue_active(&dev->wait_pg))
1014 wake_up(&dev->wait_pg);
1018 * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler
1020 * @dev: the device structure
1021 * @intr_source: interrupt source
1023 static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source)
1025 struct mei_me_hw *hw = to_me_hw(dev);
1027 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT &&
1028 (intr_source & H_D0I3C_IS)) {
1029 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1030 if (hw->pg_state == MEI_PG_ON) {
1031 hw->pg_state = MEI_PG_OFF;
1032 if (dev->hbm_state != MEI_HBM_IDLE) {
1034 * force H_RDY because it could be
1035 * wiped off during PG
1037 dev_dbg(dev->dev, "d0i3 set host ready\n");
1038 mei_me_host_set_ready(dev);
1041 hw->pg_state = MEI_PG_ON;
1044 wake_up(&dev->wait_pg);
1047 if (hw->pg_state == MEI_PG_ON && (intr_source & H_IS)) {
1049 * HW sent some data and we are in D0i3, so
1050 * we got here because of HW initiated exit from D0i3.
1051 * Start runtime pm resume sequence to exit low power state.
1053 dev_dbg(dev->dev, "d0i3 want resume\n");
1054 mei_hbm_pg_resume(dev);
1059 * mei_me_pg_intr - perform pg processing in interrupt thread handler
1061 * @dev: the device structure
1062 * @intr_source: interrupt source
1064 static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source)
1066 struct mei_me_hw *hw = to_me_hw(dev);
1068 if (hw->d0i3_supported)
1069 mei_me_d0i3_intr(dev, intr_source);
1071 mei_me_pg_legacy_intr(dev);
1075 * mei_me_pg_enter_sync - perform runtime pm entry procedure
1077 * @dev: the device structure
1079 * Return: 0 on success an error code otherwise
1081 int mei_me_pg_enter_sync(struct mei_device *dev)
1083 struct mei_me_hw *hw = to_me_hw(dev);
1085 if (hw->d0i3_supported)
1086 return mei_me_d0i3_enter_sync(dev);
1088 return mei_me_pg_legacy_enter_sync(dev);
1092 * mei_me_pg_exit_sync - perform runtime pm exit procedure
1094 * @dev: the device structure
1096 * Return: 0 on success an error code otherwise
1098 int mei_me_pg_exit_sync(struct mei_device *dev)
1100 struct mei_me_hw *hw = to_me_hw(dev);
1102 if (hw->d0i3_supported)
1103 return mei_me_d0i3_exit_sync(dev);
1105 return mei_me_pg_legacy_exit_sync(dev);
1109 * mei_me_hw_reset - resets fw via mei csr register.
1111 * @dev: the device structure
1112 * @intr_enable: if interrupt should be enabled after reset.
1114 * Return: 0 on success an error code otherwise
1116 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
1118 struct mei_me_hw *hw = to_me_hw(dev);
1123 mei_me_intr_enable(dev);
1124 if (hw->d0i3_supported) {
1125 ret = mei_me_d0i3_exit_sync(dev);
1131 pm_runtime_set_active(dev->dev);
1133 hcsr = mei_hcsr_read(dev);
1134 /* H_RST may be found lit before reset is started,
1135 * for example if preceding reset flow hasn't completed.
1136 * In that case asserting H_RST will be ignored, therefore
1137 * we need to clean H_RST bit to start a successful reset sequence.
1139 if ((hcsr & H_RST) == H_RST) {
1140 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
1142 mei_hcsr_set(dev, hcsr);
1143 hcsr = mei_hcsr_read(dev);
1146 hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
1149 hcsr &= ~H_CSR_IE_MASK;
1151 dev->recvd_hw_ready = false;
1152 mei_hcsr_write(dev, hcsr);
1155 * Host reads the H_CSR once to ensure that the
1156 * posted write to H_CSR completes.
1158 hcsr = mei_hcsr_read(dev);
1160 if ((hcsr & H_RST) == 0)
1161 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
1163 if ((hcsr & H_RDY) == H_RDY)
1164 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
1167 mei_me_hw_reset_release(dev);
1168 if (hw->d0i3_supported) {
1169 ret = mei_me_d0i3_enter(dev);
1178 * mei_me_irq_quick_handler - The ISR of the MEI device
1180 * @irq: The irq number
1181 * @dev_id: pointer to the device structure
1183 * Return: irqreturn_t
1185 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
1187 struct mei_device *dev = (struct mei_device *)dev_id;
1190 hcsr = mei_hcsr_read(dev);
1191 if (!me_intr_src(hcsr))
1194 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr));
1196 /* disable interrupts on device */
1197 me_intr_disable(dev, hcsr);
1198 return IRQ_WAKE_THREAD;
1202 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
1205 * @irq: The irq number
1206 * @dev_id: pointer to the device structure
1208 * Return: irqreturn_t
1211 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
1213 struct mei_device *dev = (struct mei_device *) dev_id;
1214 struct list_head cmpl_list;
1219 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
1220 /* initialize our complete list */
1221 mutex_lock(&dev->device_lock);
1223 hcsr = mei_hcsr_read(dev);
1224 me_intr_clear(dev, hcsr);
1226 INIT_LIST_HEAD(&cmpl_list);
1228 /* check if ME wants a reset */
1229 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
1230 dev_warn(dev->dev, "FW not ready: resetting.\n");
1231 schedule_work(&dev->reset_work);
1235 if (mei_me_hw_is_resetting(dev))
1236 mei_hcsr_set_hig(dev);
1238 mei_me_pg_intr(dev, me_intr_src(hcsr));
1240 /* check if we need to start the dev */
1241 if (!mei_host_is_ready(dev)) {
1242 if (mei_hw_is_ready(dev)) {
1243 dev_dbg(dev->dev, "we need to start the dev.\n");
1244 dev->recvd_hw_ready = true;
1245 wake_up(&dev->wait_hw_ready);
1247 dev_dbg(dev->dev, "Spurious Interrupt\n");
1251 /* check slots available for reading */
1252 slots = mei_count_full_read_slots(dev);
1254 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
1255 rets = mei_irq_read_handler(dev, &cmpl_list, &slots);
1256 /* There is a race between ME write and interrupt delivery:
1257 * Not all data is always available immediately after the
1258 * interrupt, so try to read again on the next interrupt.
1260 if (rets == -ENODATA)
1264 (dev->dev_state != MEI_DEV_RESETTING &&
1265 dev->dev_state != MEI_DEV_POWER_DOWN)) {
1266 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",
1268 schedule_work(&dev->reset_work);
1273 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1276 * During PG handshake only allowed write is the replay to the
1277 * PG exit message, so block calling write function
1278 * if the pg event is in PG handshake
1280 if (dev->pg_event != MEI_PG_EVENT_WAIT &&
1281 dev->pg_event != MEI_PG_EVENT_RECEIVED) {
1282 rets = mei_irq_write_handler(dev, &cmpl_list);
1283 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1286 mei_irq_compl_handler(dev, &cmpl_list);
1289 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1290 mei_me_intr_enable(dev);
1291 mutex_unlock(&dev->device_lock);
1295 static const struct mei_hw_ops mei_me_hw_ops = {
1297 .fw_status = mei_me_fw_status,
1298 .pg_state = mei_me_pg_state,
1300 .host_is_ready = mei_me_host_is_ready,
1302 .hw_is_ready = mei_me_hw_is_ready,
1303 .hw_reset = mei_me_hw_reset,
1304 .hw_config = mei_me_hw_config,
1305 .hw_start = mei_me_hw_start,
1307 .pg_in_transition = mei_me_pg_in_transition,
1308 .pg_is_enabled = mei_me_pg_is_enabled,
1310 .intr_clear = mei_me_intr_clear,
1311 .intr_enable = mei_me_intr_enable,
1312 .intr_disable = mei_me_intr_disable,
1313 .synchronize_irq = mei_me_synchronize_irq,
1315 .hbuf_free_slots = mei_me_hbuf_empty_slots,
1316 .hbuf_is_ready = mei_me_hbuf_is_empty,
1317 .hbuf_depth = mei_me_hbuf_depth,
1319 .write = mei_me_hbuf_write,
1321 .rdbuf_full_slots = mei_me_count_full_read_slots,
1322 .read_hdr = mei_me_mecbrw_read,
1323 .read = mei_me_read_slots
1326 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
1330 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
1331 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg);
1332 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
1333 return (reg & 0x600) == 0x200;
1336 #define MEI_CFG_FW_NM \
1337 .quirk_probe = mei_me_fw_type_nm
1339 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
1345 * Read ME FW Status register to check for SPS Firmware
1346 * The SPS FW is only signaled in pci function 0
1348 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1349 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, ®);
1350 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
1351 /* if bits [19:16] = 15, running SPS Firmware */
1352 return (reg & 0xf0000) == 0xf0000;
1355 #define MEI_CFG_FW_SPS \
1356 .quirk_probe = mei_me_fw_type_sps
1358 #define MEI_CFG_FW_VER_SUPP \
1359 .fw_ver_supported = 1
1361 #define MEI_CFG_ICH_HFS \
1362 .fw_status.count = 0
1364 #define MEI_CFG_ICH10_HFS \
1365 .fw_status.count = 1, \
1366 .fw_status.status[0] = PCI_CFG_HFS_1
1368 #define MEI_CFG_PCH_HFS \
1369 .fw_status.count = 2, \
1370 .fw_status.status[0] = PCI_CFG_HFS_1, \
1371 .fw_status.status[1] = PCI_CFG_HFS_2
1373 #define MEI_CFG_PCH8_HFS \
1374 .fw_status.count = 6, \
1375 .fw_status.status[0] = PCI_CFG_HFS_1, \
1376 .fw_status.status[1] = PCI_CFG_HFS_2, \
1377 .fw_status.status[2] = PCI_CFG_HFS_3, \
1378 .fw_status.status[3] = PCI_CFG_HFS_4, \
1379 .fw_status.status[4] = PCI_CFG_HFS_5, \
1380 .fw_status.status[5] = PCI_CFG_HFS_6
1382 #define MEI_CFG_DMA_128 \
1383 .dma_size[DMA_DSCR_HOST] = SZ_128K, \
1384 .dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
1385 .dma_size[DMA_DSCR_CTRL] = PAGE_SIZE
1387 /* ICH Legacy devices */
1388 static const struct mei_cfg mei_me_ich_cfg = {
1393 static const struct mei_cfg mei_me_ich10_cfg = {
1398 static const struct mei_cfg mei_me_pch6_cfg = {
1403 static const struct mei_cfg mei_me_pch7_cfg = {
1405 MEI_CFG_FW_VER_SUPP,
1408 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
1409 static const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
1411 MEI_CFG_FW_VER_SUPP,
1415 /* PCH8 Lynx Point and newer devices */
1416 static const struct mei_cfg mei_me_pch8_cfg = {
1418 MEI_CFG_FW_VER_SUPP,
1421 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1422 static const struct mei_cfg mei_me_pch8_sps_cfg = {
1424 MEI_CFG_FW_VER_SUPP,
1428 /* Cannon Lake and newer devices */
1429 static const struct mei_cfg mei_me_pch12_cfg = {
1431 MEI_CFG_FW_VER_SUPP,
1436 * mei_cfg_list - A list of platform platform specific configurations.
1437 * Note: has to be synchronized with enum mei_cfg_idx.
1439 static const struct mei_cfg *const mei_cfg_list[] = {
1440 [MEI_ME_UNDEF_CFG] = NULL,
1441 [MEI_ME_ICH_CFG] = &mei_me_ich_cfg,
1442 [MEI_ME_ICH10_CFG] = &mei_me_ich10_cfg,
1443 [MEI_ME_PCH6_CFG] = &mei_me_pch6_cfg,
1444 [MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg,
1445 [MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
1446 [MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
1447 [MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg,
1448 [MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
1451 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
1453 BUILD_BUG_ON(ARRAY_SIZE(mei_cfg_list) != MEI_ME_NUM_CFG);
1455 if (idx >= MEI_ME_NUM_CFG)
1458 return mei_cfg_list[idx];
1462 * mei_me_dev_init - allocates and initializes the mei device structure
1464 * @pdev: The pci device structure
1465 * @cfg: per device generation config
1467 * Return: The mei_device pointer on success, NULL on failure.
1469 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
1470 const struct mei_cfg *cfg)
1472 struct mei_device *dev;
1473 struct mei_me_hw *hw;
1476 dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) +
1477 sizeof(struct mei_me_hw), GFP_KERNEL);
1483 for (i = 0; i < DMA_DSCR_NUM; i++)
1484 dev->dr_dscr[i].size = cfg->dma_size[i];
1486 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);
1489 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;