3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
29 * mei_reg_read - Reads 32bit data from the mei device
31 * @dev: the device structure
32 * @offset: offset from which to read the data
34 * returns register value (u32)
36 static inline u32 mei_reg_read(const struct mei_me_hw *hw,
39 return ioread32(hw->mem_addr + offset);
44 * mei_reg_write - Writes 32bit data to the mei device
46 * @dev: the device structure
47 * @offset: offset from which to write the data
48 * @value: register value to write (u32)
50 static inline void mei_reg_write(const struct mei_me_hw *hw,
51 unsigned long offset, u32 value)
53 iowrite32(value, hw->mem_addr + offset);
57 * mei_mecbrw_read - Reads 32bit data from ME circular buffer
58 * read window register
60 * @dev: the device structure
62 * returns ME_CB_RW register value (u32)
64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
66 return mei_reg_read(to_me_hw(dev), ME_CB_RW);
69 * mei_mecsr_read - Reads 32bit data from the ME CSR
71 * @dev: the device structure
73 * returns ME_CSR_HA register value (u32)
75 static inline u32 mei_mecsr_read(const struct mei_me_hw *hw)
77 return mei_reg_read(hw, ME_CSR_HA);
81 * mei_hcsr_read - Reads 32bit data from the host CSR
83 * @dev: the device structure
85 * returns H_CSR register value (u32)
87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
89 return mei_reg_read(hw, H_CSR);
93 * mei_hcsr_set - writes H_CSR register to the mei device,
94 * and ignores the H_IS bit for it is write-one-to-zero.
96 * @dev: the device structure
98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
101 mei_reg_write(hw, H_CSR, hcsr);
106 * me_hw_config - configure hw dependent settings
110 static void mei_me_hw_config(struct mei_device *dev)
112 u32 hcsr = mei_hcsr_read(to_me_hw(dev));
113 /* Doesn't change in runtime */
114 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
117 * mei_clear_interrupts - clear and stop interrupts
119 * @dev: the device structure
121 static void mei_me_intr_clear(struct mei_device *dev)
123 struct mei_me_hw *hw = to_me_hw(dev);
124 u32 hcsr = mei_hcsr_read(hw);
125 if ((hcsr & H_IS) == H_IS)
126 mei_reg_write(hw, H_CSR, hcsr);
129 * mei_me_intr_enable - enables mei device interrupts
131 * @dev: the device structure
133 static void mei_me_intr_enable(struct mei_device *dev)
135 struct mei_me_hw *hw = to_me_hw(dev);
136 u32 hcsr = mei_hcsr_read(hw);
138 mei_hcsr_set(hw, hcsr);
142 * mei_disable_interrupts - disables mei device interrupts
144 * @dev: the device structure
146 static void mei_me_intr_disable(struct mei_device *dev)
148 struct mei_me_hw *hw = to_me_hw(dev);
149 u32 hcsr = mei_hcsr_read(hw);
151 mei_hcsr_set(hw, hcsr);
155 * mei_me_hw_reset_release - release device from the reset
157 * @dev: the device structure
159 static void mei_me_hw_reset_release(struct mei_device *dev)
161 struct mei_me_hw *hw = to_me_hw(dev);
162 u32 hcsr = mei_hcsr_read(hw);
166 mei_hcsr_set(hw, hcsr);
169 * mei_me_hw_reset - resets fw via mei csr register.
171 * @dev: the device structure
172 * @interrupts_enabled: if interrupt should be enabled after reset.
174 static void mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
176 struct mei_me_hw *hw = to_me_hw(dev);
177 u32 hcsr = mei_hcsr_read(hw);
179 dev_dbg(&dev->pdev->dev, "before reset HCSR = 0x%08x.\n", hcsr);
181 hcsr |= (H_RST | H_IG);
188 mei_hcsr_set(hw, hcsr);
190 if (dev->dev_state == MEI_DEV_POWER_DOWN)
191 mei_me_hw_reset_release(dev);
193 dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", mei_hcsr_read(hw));
197 * mei_me_host_set_ready - enable device
203 static void mei_me_host_set_ready(struct mei_device *dev)
205 struct mei_me_hw *hw = to_me_hw(dev);
206 hw->host_hw_state |= H_IE | H_IG | H_RDY;
207 mei_hcsr_set(hw, hw->host_hw_state);
210 * mei_me_host_is_ready - check whether the host has turned ready
215 static bool mei_me_host_is_ready(struct mei_device *dev)
217 struct mei_me_hw *hw = to_me_hw(dev);
218 hw->host_hw_state = mei_hcsr_read(hw);
219 return (hw->host_hw_state & H_RDY) == H_RDY;
223 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
228 static bool mei_me_hw_is_ready(struct mei_device *dev)
230 struct mei_me_hw *hw = to_me_hw(dev);
231 hw->me_hw_state = mei_mecsr_read(hw);
232 return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
236 * mei_hbuf_filled_slots - gets number of device filled buffer slots
238 * @dev: the device structure
240 * returns number of filled slots
242 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
244 struct mei_me_hw *hw = to_me_hw(dev);
245 char read_ptr, write_ptr;
247 hw->host_hw_state = mei_hcsr_read(hw);
249 read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
250 write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
252 return (unsigned char) (write_ptr - read_ptr);
256 * mei_hbuf_is_empty - checks if host buffer is empty.
258 * @dev: the device structure
260 * returns true if empty, false - otherwise.
262 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
264 return mei_hbuf_filled_slots(dev) == 0;
268 * mei_me_hbuf_empty_slots - counts write empty slots.
270 * @dev: the device structure
272 * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
274 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
276 unsigned char filled_slots, empty_slots;
278 filled_slots = mei_hbuf_filled_slots(dev);
279 empty_slots = dev->hbuf_depth - filled_slots;
281 /* check for overflow */
282 if (filled_slots > dev->hbuf_depth)
288 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
290 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
295 * mei_write_message - writes a message to mei device.
297 * @dev: the device structure
298 * @header: mei HECI header of message
299 * @buf: message payload will be written
301 * This function returns -EIO if write has failed
303 static int mei_me_write_message(struct mei_device *dev,
304 struct mei_msg_hdr *header,
307 struct mei_me_hw *hw = to_me_hw(dev);
308 unsigned long rem, dw_cnt;
309 unsigned long length = header->length;
310 u32 *reg_buf = (u32 *)buf;
315 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
317 empty_slots = mei_hbuf_empty_slots(dev);
318 dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
320 dw_cnt = mei_data2slots(length);
321 if (empty_slots < 0 || dw_cnt > empty_slots)
324 mei_reg_write(hw, H_CB_WW, *((u32 *) header));
326 for (i = 0; i < length / 4; i++)
327 mei_reg_write(hw, H_CB_WW, reg_buf[i]);
332 memcpy(®, &buf[length - rem], rem);
333 mei_reg_write(hw, H_CB_WW, reg);
336 hcsr = mei_hcsr_read(hw) | H_IG;
337 mei_hcsr_set(hw, hcsr);
338 if (!mei_me_hw_is_ready(dev))
345 * mei_me_count_full_read_slots - counts read full slots.
347 * @dev: the device structure
349 * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
351 static int mei_me_count_full_read_slots(struct mei_device *dev)
353 struct mei_me_hw *hw = to_me_hw(dev);
354 char read_ptr, write_ptr;
355 unsigned char buffer_depth, filled_slots;
357 hw->me_hw_state = mei_mecsr_read(hw);
358 buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
359 read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
360 write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
361 filled_slots = (unsigned char) (write_ptr - read_ptr);
363 /* check for overflow */
364 if (filled_slots > buffer_depth)
367 dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
368 return (int)filled_slots;
372 * mei_me_read_slots - reads a message from mei device.
374 * @dev: the device structure
375 * @buffer: message buffer will be written
376 * @buffer_length: message size will be read
378 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
379 unsigned long buffer_length)
381 struct mei_me_hw *hw = to_me_hw(dev);
382 u32 *reg_buf = (u32 *)buffer;
385 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
386 *reg_buf++ = mei_me_mecbrw_read(dev);
388 if (buffer_length > 0) {
389 u32 reg = mei_me_mecbrw_read(dev);
390 memcpy(reg_buf, ®, buffer_length);
393 hcsr = mei_hcsr_read(hw) | H_IG;
394 mei_hcsr_set(hw, hcsr);
399 * mei_me_irq_quick_handler - The ISR of the MEI device
401 * @irq: The irq number
402 * @dev_id: pointer to the device structure
404 * returns irqreturn_t
407 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
409 struct mei_device *dev = (struct mei_device *) dev_id;
410 struct mei_me_hw *hw = to_me_hw(dev);
411 u32 csr_reg = mei_hcsr_read(hw);
413 if ((csr_reg & H_IS) != H_IS)
416 /* clear H_IS bit in H_CSR */
417 mei_reg_write(hw, H_CSR, csr_reg);
419 return IRQ_WAKE_THREAD;
423 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
426 * @irq: The irq number
427 * @dev_id: pointer to the device structure
429 * returns irqreturn_t
432 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
434 struct mei_device *dev = (struct mei_device *) dev_id;
435 struct mei_cl_cb complete_list;
436 struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
440 bool bus_message_received;
443 dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
444 /* initialize our complete list */
445 mutex_lock(&dev->device_lock);
446 mei_io_list_init(&complete_list);
448 /* Ack the interrupt here
449 * In case of MSI we don't go through the quick handler */
450 if (pci_dev_msi_enabled(dev->pdev))
451 mei_clear_interrupts(dev);
453 /* check if ME wants a reset */
454 if (!mei_hw_is_ready(dev) &&
455 dev->dev_state != MEI_DEV_RESETING &&
456 dev->dev_state != MEI_DEV_INITIALIZING) {
457 dev_dbg(&dev->pdev->dev, "FW not ready.\n");
459 mutex_unlock(&dev->device_lock);
463 /* check if we need to start the dev */
464 if (!mei_host_is_ready(dev)) {
465 if (mei_hw_is_ready(dev)) {
466 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
468 mei_host_set_ready(dev);
470 dev_dbg(&dev->pdev->dev, "link is established start sending messages.\n");
471 /* link is established * start sending messages. */
473 dev->dev_state = MEI_DEV_INIT_CLIENTS;
475 mei_hbm_start_req(dev);
476 mutex_unlock(&dev->device_lock);
479 dev_dbg(&dev->pdev->dev, "Reset Completed.\n");
480 mei_me_hw_reset_release(dev);
481 mutex_unlock(&dev->device_lock);
485 /* check slots available for reading */
486 slots = mei_count_full_read_slots(dev);
488 /* we have urgent data to send so break the read */
489 if (dev->wr_ext_msg.hdr.length)
491 dev_dbg(&dev->pdev->dev, "slots =%08x\n", slots);
492 dev_dbg(&dev->pdev->dev, "call mei_irq_read_handler.\n");
493 rets = mei_irq_read_handler(dev, &complete_list, &slots);
497 rets = mei_irq_write_handler(dev, &complete_list);
499 dev_dbg(&dev->pdev->dev, "end of bottom half function.\n");
500 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
502 bus_message_received = false;
503 if (dev->recvd_msg && waitqueue_active(&dev->wait_recvd_msg)) {
504 dev_dbg(&dev->pdev->dev, "received waiting bus message\n");
505 bus_message_received = true;
507 mutex_unlock(&dev->device_lock);
508 if (bus_message_received) {
509 dev_dbg(&dev->pdev->dev, "wake up dev->wait_recvd_msg\n");
510 wake_up_interruptible(&dev->wait_recvd_msg);
511 bus_message_received = false;
513 if (list_empty(&complete_list.list))
517 list_for_each_entry_safe(cb_pos, cb_next, &complete_list.list, list) {
519 list_del(&cb_pos->list);
521 if (cl != &dev->iamthif_cl) {
522 dev_dbg(&dev->pdev->dev, "completing call back.\n");
523 mei_irq_complete_handler(cl, cb_pos);
525 } else if (cl == &dev->iamthif_cl) {
526 mei_amthif_complete(dev, cb_pos);
532 static const struct mei_hw_ops mei_me_hw_ops = {
534 .host_set_ready = mei_me_host_set_ready,
535 .host_is_ready = mei_me_host_is_ready,
537 .hw_is_ready = mei_me_hw_is_ready,
538 .hw_reset = mei_me_hw_reset,
539 .hw_config = mei_me_hw_config,
541 .intr_clear = mei_me_intr_clear,
542 .intr_enable = mei_me_intr_enable,
543 .intr_disable = mei_me_intr_disable,
545 .hbuf_free_slots = mei_me_hbuf_empty_slots,
546 .hbuf_is_ready = mei_me_hbuf_is_empty,
547 .hbuf_max_len = mei_me_hbuf_max_len,
549 .write = mei_me_write_message,
551 .rdbuf_full_slots = mei_me_count_full_read_slots,
552 .read_hdr = mei_me_mecbrw_read,
553 .read = mei_me_read_slots
557 * init_mei_device - allocates and initializes the mei device structure
559 * @pdev: The pci device structure
561 * returns The mei_device_device pointer on success, NULL on failure.
563 struct mei_device *mei_me_dev_init(struct pci_dev *pdev)
565 struct mei_device *dev;
567 dev = kzalloc(sizeof(struct mei_device) +
568 sizeof(struct mei_me_hw), GFP_KERNEL);
572 mei_device_init(dev);
574 INIT_LIST_HEAD(&dev->wd_cl.link);
575 INIT_LIST_HEAD(&dev->iamthif_cl.link);
576 mei_io_list_init(&dev->amthif_cmd_list);
577 mei_io_list_init(&dev->amthif_rd_complete_list);
579 INIT_DELAYED_WORK(&dev->timer_work, mei_timer);
580 INIT_WORK(&dev->init_work, mei_host_client_init);
582 dev->ops = &mei_me_hw_ops;