drivers/misc/mei/pci-me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/kernel.h>
  10 #include <linux/device.h>
  11 #include <linux/fs.h>
  12 #include <linux/errno.h>
  13 #include <linux/types.h>
  14 #include <linux/fcntl.h>
  15 #include <linux/pci.h>
  16 #include <linux/poll.h>
  17 #include <linux/ioctl.h>
  18 #include <linux/cdev.h>
  19 #include <linux/sched.h>
  20 #include <linux/uuid.h>
  21 #include <linux/compat.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/interrupt.h>
  24
  25 #include <linux/pm_domain.h>
  26 #include <linux/pm_runtime.h>
  27
  28 #include <linux/mei.h>
  29
  30 #include "mei_dev.h"
  31 #include "client.h"
  32 #include "hw-me-regs.h"
  33 #include "hw-me.h"
  34
  35 /* mei_pci_tbl - PCI Device ID Table */
  36 static const struct pci_device_id mei_me_pci_tbl[] = {
  37         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  38         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  39         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  40         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  41         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  42         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  43         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  44         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  45         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  48
  49         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  50         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  54         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  55         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  57         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  58
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  63
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  67         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  68         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  69         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
  72         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  74         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
  75         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  76         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  77
  78         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  79         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  80         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
  81         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
  82         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
  83
  84         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  86
  87         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  88
  89         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  90
  91         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  92         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  93
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
  95         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
  97         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
  98
  99         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
 100         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)},
 101         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
 102
 103         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
 104
 105         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH12_CFG)},
 106
 107         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)},
 108         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 109
 110         /* required last entry */
 111         {0, }
 112 };
 113
 114 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 115
 116 #ifdef CONFIG_PM
 117 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 118 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 119 #else
 120 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 121 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 122 #endif /* CONFIG_PM */
 123
 124 /**
 125  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 126  *
 127  * @pdev: PCI device structure
 128  * @cfg: per generation config
 129  *
 130  * Return: true if ME Interface is valid, false otherwise
 131  */
 132 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 133                                 const struct mei_cfg *cfg)
 134 {
 135         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 136                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 137                 return false;
 138         }
 139
 140         return true;
 141 }
 142
 143 /**
 144  * mei_me_probe - Device Initialization Routine
 145  *
 146  * @pdev: PCI device structure
 147  * @ent: entry in kcs_pci_tbl
 148  *
 149  * Return: 0 on success, <0 on failure.
 150  */
 151 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 152 {
 153         const struct mei_cfg *cfg;
 154         struct mei_device *dev;
 155         struct mei_me_hw *hw;
 156         unsigned int irqflags;
 157         int err;
 158
 159         cfg = mei_me_get_cfg(ent->driver_data);
 160         if (!cfg)
 161                 return -ENODEV;
 162
 163         if (!mei_me_quirk_probe(pdev, cfg))
 164                 return -ENODEV;
 165
 166         /* enable pci dev */
 167         err = pcim_enable_device(pdev);
 168         if (err) {
 169                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 170                 goto end;
 171         }
 172         /* set PCI host mastering  */
 173         pci_set_master(pdev);
 174         /* pci request regions and mapping IO device memory for mei driver */
 175         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 176         if (err) {
 177                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 178                 goto end;
 179         }
 180
 181         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
 182             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 183
 184                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 185                 if (err)
 186                         err = dma_set_coherent_mask(&pdev->dev,
 187                                                     DMA_BIT_MASK(32));
 188         }
 189         if (err) {
 190                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 191                 goto end;
 192         }
 193
 194         /* allocates and initializes the mei dev structure */
 195         dev = mei_me_dev_init(&pdev->dev, cfg);
 196         if (!dev) {
 197                 err = -ENOMEM;
 198                 goto end;
 199         }
 200         hw = to_me_hw(dev);
 201         hw->mem_addr = pcim_iomap_table(pdev)[0];
 202         hw->irq = pdev->irq;
 203
 204         pci_enable_msi(pdev);
 205
 206          /* request and enable interrupt */
 207         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 208
 209         err = request_threaded_irq(pdev->irq,
 210                         mei_me_irq_quick_handler,
 211                         mei_me_irq_thread_handler,
 212                         irqflags, KBUILD_MODNAME, dev);
 213         if (err) {
 214                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 215                        pdev->irq);
 216                 goto end;
 217         }
 218
 219         if (mei_start(dev)) {
 220                 dev_err(&pdev->dev, "init hw failure.\n");
 221                 err = -ENODEV;
 222                 goto release_irq;
 223         }
 224
 225         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 226         pm_runtime_use_autosuspend(&pdev->dev);
 227
 228         err = mei_register(dev, &pdev->dev);
 229         if (err)
 230                 goto stop;
 231
 232         pci_set_drvdata(pdev, dev);
 233
 234         /*
 235          * MEI requires to resume from runtime suspend mode
 236          * in order to perform link reset flow upon system suspend.
 237          */
 238         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
 239
 240         /*
 241          * ME maps runtime suspend/resume to D0i states,
 242          * hence we need to go around native PCI runtime service which
 243          * eventually brings the device into D3cold/hot state,
 244          * but the mei device cannot wake up from D3 unlike from D0i3.
 245          * To get around the PCI device native runtime pm,
 246          * ME uses runtime pm domain handlers which take precedence
 247          * over the driver's pm handlers.
 248          */
 249         mei_me_set_pm_domain(dev);
 250
 251         if (mei_pg_is_enabled(dev)) {
 252                 pm_runtime_put_noidle(&pdev->dev);
 253                 if (hw->d0i3_supported)
 254                         pm_runtime_allow(&pdev->dev);
 255         }
 256
 257         dev_dbg(&pdev->dev, "initialization successful.\n");
 258
 259         return 0;
 260
 261 stop:
 262         mei_stop(dev);
 263 release_irq:
 264         mei_cancel_work(dev);
 265         mei_disable_interrupts(dev);
 266         free_irq(pdev->irq, dev);
 267 end:
 268         dev_err(&pdev->dev, "initialization failed.\n");
 269         return err;
 270 }
 271
 272 /**
 273  * mei_me_shutdown - Device Removal Routine
 274  *
 275  * @pdev: PCI device structure
 276  *
 277  * mei_me_shutdown is called from the reboot notifier
 278  * it's a simplified version of remove so we go down
 279  * faster.
 280  */
 281 static void mei_me_shutdown(struct pci_dev *pdev)
 282 {
 283         struct mei_device *dev;
 284
 285         dev = pci_get_drvdata(pdev);
 286         if (!dev)
 287                 return;
 288
 289         dev_dbg(&pdev->dev, "shutdown\n");
 290         mei_stop(dev);
 291
 292         mei_me_unset_pm_domain(dev);
 293
 294         mei_disable_interrupts(dev);
 295         free_irq(pdev->irq, dev);
 296 }
 297
 298 /**
 299  * mei_me_remove - Device Removal Routine
 300  *
 301  * @pdev: PCI device structure
 302  *
 303  * mei_me_remove is called by the PCI subsystem to alert the driver
 304  * that it should release a PCI device.
 305  */
 306 static void mei_me_remove(struct pci_dev *pdev)
 307 {
 308         struct mei_device *dev;
 309
 310         dev = pci_get_drvdata(pdev);
 311         if (!dev)
 312                 return;
 313
 314         if (mei_pg_is_enabled(dev))
 315                 pm_runtime_get_noresume(&pdev->dev);
 316
 317         dev_dbg(&pdev->dev, "stop\n");
 318         mei_stop(dev);
 319
 320         mei_me_unset_pm_domain(dev);
 321
 322         mei_disable_interrupts(dev);
 323
 324         free_irq(pdev->irq, dev);
 325
 326         mei_deregister(dev);
 327 }
 328
 329 #ifdef CONFIG_PM_SLEEP
 330 static int mei_me_pci_suspend(struct device *device)
 331 {
 332         struct pci_dev *pdev = to_pci_dev(device);
 333         struct mei_device *dev = pci_get_drvdata(pdev);
 334
 335         if (!dev)
 336                 return -ENODEV;
 337
 338         dev_dbg(&pdev->dev, "suspend\n");
 339
 340         mei_stop(dev);
 341
 342         mei_disable_interrupts(dev);
 343
 344         free_irq(pdev->irq, dev);
 345         pci_disable_msi(pdev);
 346
 347         return 0;
 348 }
 349
 350 static int mei_me_pci_resume(struct device *device)
 351 {
 352         struct pci_dev *pdev = to_pci_dev(device);
 353         struct mei_device *dev;
 354         unsigned int irqflags;
 355         int err;
 356
 357         dev = pci_get_drvdata(pdev);
 358         if (!dev)
 359                 return -ENODEV;
 360
 361         pci_enable_msi(pdev);
 362
 363         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 364
 365         /* request and enable interrupt */
 366         err = request_threaded_irq(pdev->irq,
 367                         mei_me_irq_quick_handler,
 368                         mei_me_irq_thread_handler,
 369                         irqflags, KBUILD_MODNAME, dev);
 370
 371         if (err) {
 372                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 373                                 pdev->irq);
 374                 return err;
 375         }
 376
 377         err = mei_restart(dev);
 378         if (err)
 379                 return err;
 380
 381         /* Start timer if stopped in suspend */
 382         schedule_delayed_work(&dev->timer_work, HZ);
 383
 384         return 0;
 385 }
 386 #endif /* CONFIG_PM_SLEEP */
 387
 388 #ifdef CONFIG_PM
 389 static int mei_me_pm_runtime_idle(struct device *device)
 390 {
 391         struct mei_device *dev;
 392
 393         dev_dbg(device, "rpm: me: runtime_idle\n");
 394
 395         dev = dev_get_drvdata(device);
 396         if (!dev)
 397                 return -ENODEV;
 398         if (mei_write_is_idle(dev))
 399                 pm_runtime_autosuspend(device);
 400
 401         return -EBUSY;
 402 }
 403
 404 static int mei_me_pm_runtime_suspend(struct device *device)
 405 {
 406         struct mei_device *dev;
 407         int ret;
 408
 409         dev_dbg(device, "rpm: me: runtime suspend\n");
 410
 411         dev = dev_get_drvdata(device);
 412         if (!dev)
 413                 return -ENODEV;
 414
 415         mutex_lock(&dev->device_lock);
 416
 417         if (mei_write_is_idle(dev))
 418                 ret = mei_me_pg_enter_sync(dev);
 419         else
 420                 ret = -EAGAIN;
 421
 422         mutex_unlock(&dev->device_lock);
 423
 424         dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
 425
 426         if (ret && ret != -EAGAIN)
 427                 schedule_work(&dev->reset_work);
 428
 429         return ret;
 430 }
 431
 432 static int mei_me_pm_runtime_resume(struct device *device)
 433 {
 434         struct mei_device *dev;
 435         int ret;
 436
 437         dev_dbg(device, "rpm: me: runtime resume\n");
 438
 439         dev = dev_get_drvdata(device);
 440         if (!dev)
 441                 return -ENODEV;
 442
 443         mutex_lock(&dev->device_lock);
 444
 445         ret = mei_me_pg_exit_sync(dev);
 446
 447         mutex_unlock(&dev->device_lock);
 448
 449         dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
 450
 451         if (ret)
 452                 schedule_work(&dev->reset_work);
 453
 454         return ret;
 455 }
 456
 457 /**
 458  * mei_me_set_pm_domain - fill and set pm domain structure for device
 459  *
 460  * @dev: mei_device
 461  */
 462 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 463 {
 464         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 465
 466         if (pdev->dev.bus && pdev->dev.bus->pm) {
 467                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 468
 469                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 470                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 471                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 472
 473                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 474         }
 475 }
 476
 477 /**
 478  * mei_me_unset_pm_domain - clean pm domain structure for device
 479  *
 480  * @dev: mei_device
 481  */
 482 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 483 {
 484         /* stop using pm callbacks if any */
 485         dev_pm_domain_set(dev->dev, NULL);
 486 }
 487
 488 static const struct dev_pm_ops mei_me_pm_ops = {
 489         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 490                                 mei_me_pci_resume)
 491         SET_RUNTIME_PM_OPS(
 492                 mei_me_pm_runtime_suspend,
 493                 mei_me_pm_runtime_resume,
 494                 mei_me_pm_runtime_idle)
 495 };
 496
 497 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 498 #else
 499 #define MEI_ME_PM_OPS   NULL
 500 #endif /* CONFIG_PM */
 501 /*
 502  *  PCI driver structure
 503  */
 504 static struct pci_driver mei_me_driver = {
 505         .name = KBUILD_MODNAME,
 506         .id_table = mei_me_pci_tbl,
 507         .probe = mei_me_probe,
 508         .remove = mei_me_remove,
 509         .shutdown = mei_me_shutdown,
 510         .driver.pm = MEI_ME_PM_OPS,
 511         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 512 };
 513
 514 module_pci_driver(mei_me_driver);
 515
 516 MODULE_AUTHOR("Intel Corporation");
 517 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 518 MODULE_LICENSE("GPL v2");